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intermediate3-prompt3_lfsr | // This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
// on reset set the value of r_reg to 1
// otherwise assign r_next to r_reg
// assign the xor of bit positions 2 and 4 of r_reg to feedback_value
// concatenate feedback value with 4 MSBs of r_reg and assign it to r_next
// assign r_reg to the output q |
intermediate3-prompt2_lfsr | // This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
// r_reg is reset to 1 and is updated to r_next otherwise
// feedback_value is concatenated with r_next for the update |
intermediate3-prompt1_lfsr | // This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value; |
basic3-prompt1_priority_encoder | // This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos ); |
basic3-prompt2_priority_encoder | // This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
// If none of the input bits are high (i.e., input is zero), output zero.
// assign the position of the highest bit of in to pos |
basic3-prompt3_priority_encoder | // This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
// If in==0, assign zero to pos
// If in[0] is high, assign 0 to pos
// If in[1] is high, assign 1 to pos
// If in[2] is high, assign 2 to pos |
advanced1-prompt2_signed-addition-overflow | // This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow );
// The numbers a and b are added to the output s.
// The signed overflow of a and b is assigned to the output overflow. |
advanced1-prompt1_signed-addition-overflow | // This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow ); |
advanced1-prompt3_signed-addition-overflow | // This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow );
// The numbers a and b are added to the output s.
// assign the occurence of the signed overflow of a and b to the output overflow.
// a signed overflow occurs if the most significant bits of a and b are low and the most significant bit of s is high
// a signed overflow may also occur if the most significant bits of a and b are high and the most significant bit of s is low
|
basic4-prompt3_mux | // This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
// When sel=0, assign a to out.
// When sel=1, assign b to out. |
basic4-prompt2_mux | // This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
// select a when sel is low, otherwise select b |
basic4-prompt1_mux | // This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out ); |
basic1-prompt1_wire_assign | // This is a module that assigns the output to the input
module wire_assign( input in, output out ); |
basic1-prompt2_wire_assign | // This is a module that assigns the output to the input
module wire_assign( input in, output out );
// assign the output to the input |
basic1-prompt3_wire_assign | // This is a module that assigns the output to the input
module wire_assign( input in, output out );
// assign the output out to the input in |
intermediate2-prompt1_counter | // This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
); |
intermediate2-prompt3_counter | // This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
);
// update q on the positive edge of the clock according to the following cases:
// on reset, assign q to 1
// else if q is 12, assign q to 1
// else, increment q by 1 |
intermediate2-prompt2_counter | // This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
);
// update q on the positive edge of the clock
// q increments by 1 from 1 to 12 |
intermediate8-prompt2_truthtable | // This is a circuit synthesized from a truth table
// The truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column.
// There are four inputs combinations where the output is 1, and four where the output is 0.
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f ); |
intermediate8-prompt1_truthtable | // This is a circuit synthesized from a truth table
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f ); |
intermediate8-prompt3_truthtable | // This is a circuit synthesized from a truth table
// The truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column.
// There are four inputs combinations where the output is 1, and four where the output is 0.
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f );
// If x3 is low and x2 is low and x3 is low, assign 1 to f
// If x3 is low and x2 is low and x3 is high, assign 1 to f
// If x3 is low and x2 is high and x3 is low, assign 0 to f
// If x3 is low and x2 is high and x3 is high, assign 1 to f
// If x3 is high and x2 is low and x3 is low, assign 0 to f
// If x3 is high and x2 is low and x3 is high, assign 0 to f
// If x3 is high and x2 is high and x3 is low, assign 1 to f
// If x3 is high and x2 is high and x3 is high, assign 0 to f
|
advanced5-prompt3_abro | // This is an FSM
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro( input clk, input reset,input a, input b, output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
// Update state or reset on every clock edge
// Output z depends only on the state SAB
// The output z is high when cur_state is SAB
// cur_state is reset to IDLE when reset is high. Otherwise, it takes value of next_state.
// Next state generation logic:
// If cur_state is IDLE and a and b are both high, state changes to SAB
// If cur_state is IDLE, and a is high, state changes to SA
// If cur_state is IDLE, and b is high, state changes to SB
// If cur_state is SA, and b is high, state changes to SAB
// If cur_state is SB, and a is high, state changes to SAB
// If cur_state is SAB, state changes to IDLE
// Implements an FSM in Verilog |
advanced5-prompt1_abro | // This is an ABRO FSM.
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro(
input clk,
input reset,
input a,
input b,
output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state; |
advanced5-prompt2_abro | // This is an ABRO FSM.
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro(
input clk,
input reset,
input a,
input b,
output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
// The output z is high when 1 is received for signals a and b in any order. |
advanced2-prompt3_countslow | // This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q);
// On the positive edge of the clock:
// if reset is high, reset the output q to 0.
// Otherwise, only increment the output q if the slowena input is high and q is not 9. |
advanced2-prompt1_countslow | // This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q); |
advanced2-prompt2_countslow | // This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q);
// Increment q if slowena is high and q is not 9. |
advanced3-prompt2_advfsm | // This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
|
advanced3-prompt3_advfsm | // https://www.chipverify.com/verilog/verilog-sequence-detector
// This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
assign z = present_state == S101 ? 1 : 0;
always @ (posedge clk) begin
if (reset)
present_state <= IDLE;
else
present_state <= next_state;
end
always @ (present_state or x) begin
case (present_state)
IDLE : begin
if (x) next_state = S1;
else next_state = IDLE;
end
S1: begin
if (x) next_state = IDLE;
else next_state = S10;
end
S10 : begin
if (x) next_state = S101;
else next_state = IDLE;
end
S101: begin
next_state = IDLE;
end
endcase
end
endmodule |
advanced3-prompt1_advfsm | // This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
|
intermediate7-prompt1_permutation | // This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
|
intermediate7-prompt2_permutation | // This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
// The input signal bits are permuted according to the table In32table.
|
intermediate7-prompt3_permutation | // This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
// The input signal bits are permuted according to the table In32table.
// For i=0 till i<32, assign the bit of in32 indexed by In32table[i] to Out32[i]
|
intermediate1-prompt1_half_adder | // This is a half adder.
module half_adder(
input a, b,
output cout, sum ); |
intermediate1-prompt3_half_adder | // This is a half adder.
module half_adder(
input a, b,
output cout, sum );
// A half adder adds two bits and produces a sum and carry-out.
// assign the xor of a and b to sum
// assign the and of a and b to cout |
intermediate1-prompt2_half_adder | // This is a half adder.
module half_adder(
input a, b,
output cout, sum );
// A half adder adds two bits and produces a sum and carry-out. |
intermediate5-prompt1_shift-left-rotate | // This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out); |
intermediate5-prompt3_shift-left-rotate | // This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
// when load is high, load data to out
// when load is low, shift left and rotate the register out by amount bits |
intermediate5-prompt2_shift-left-rotate | // This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
// when load is high, load data to out
// shift left and rotate the register out by amount bits |
intermediate4-prompt3_simple-fsm | // This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
// In state 0, if in=1, stay in state 0. In state 0, if in=0, go to state 1
// In state 1, if in=1, stay in state 1. In state 1, if in=0, go to state 0
// out=1 in state 0 and out=0 in state 1 |
intermediate4-prompt2_simple-fsm | // This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
// Output out is high only in state 0, it is low otherwise
// state toggles when input in is low. state does not change when input in is high |
intermediate4-prompt1_simple-fsm | // This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
|
advanced4-prompt1_advshifter | // Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// shift according to the following values of amount:
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits. |
advanced4-prompt3_advshifter | // Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// when load is high, assign data[63:0] to shift register q.
// if ena is high, shift q.
// amount: Chooses which direction and how much to shift.
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
|
advanced4-prompt2_advshifter | // Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// when load is high, data is loaded.
// if ena is high, shift q according to the following values of amount:
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
|
basic2-prompt1_and_gate | // This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out ); |
basic2-prompt3_and_gate | // This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
// assign the AND of a and b to out |
basic2-prompt2_and_gate | // This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
// ouput the AND of a and b |
intermediate6-prompt1_ram | // This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; |
intermediate6-prompt3_ram | // This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram at address addr
// assign the ram value at address addr to q |
intermediate6-prompt2_ram | // This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram
// read teh value of ram at address addr |
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Disclaimer: I am not the original author and uploaded this here only for convenience. Please refer to the original repo for any information. https://github.com/shailja-thakur/VGen
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