system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void jacobi(double * uold, double * unew, double * f, int N, double lambda2){
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int index = blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
if(index < N*N){
int M = N+2;
int i = index + M + 1 + 2 * (index / N);
unew[i] = 0.25 * (uold[i-1] + uold[i+1] + uold[i-M] + uold[i+M] + lambda2*f[i]);
}
} | .text
.file "jacobi.hip"
.globl _Z21__device_stub__jacobiPdS_S_id # -- Begin function _Z21__device_stub__jacobiPdS_S_id
.p2align 4, 0x90
.type _Z21__device_stub__jacobiPdS_S_id,@function
_Z21__device_stub__jacobiPdS_S_id: # @_Z21__device_stub__jacobiPdS_S_id
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movsd %xmm0, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6jacobiPdS_S_id, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__jacobiPdS_S_id, .Lfunc_end0-_Z21__device_stub__jacobiPdS_S_id
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6jacobiPdS_S_id, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6jacobiPdS_S_id,@object # @_Z6jacobiPdS_S_id
.section .rodata,"a",@progbits
.globl _Z6jacobiPdS_S_id
.p2align 3, 0x0
_Z6jacobiPdS_S_id:
.quad _Z21__device_stub__jacobiPdS_S_id
.size _Z6jacobiPdS_S_id, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6jacobiPdS_S_id"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__jacobiPdS_S_id
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6jacobiPdS_S_id
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6jacobiPdS_S_id
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR5, UR5, URZ ; /* 0x00000005050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*00d0*/ UIADD3 UR4, UR5, 0x2, URZ ; /* 0x0000000205047890 */
/* 0x000fe4000fffe03f */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0150*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0160*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0180*/ LOP3.LUT R2, R0.reuse, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0000027a12 */
/* 0x040fe400078e3cff */
/*0190*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe4000fffe0ff */
/*01a0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01f0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0200*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0230*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*0240*/ @!P1 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03039210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff03aa12 */
/* 0x000fca00078e33ff */
/*0260*/ IMAD R4, R3, 0x2, R0 ; /* 0x0000000203047824 */
/* 0x000fe200078e0200 */
/*0270*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fc80000000f00 */
/*0280*/ IADD3 R0, R4.reuse, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x040fe20007ffe0ff */
/*0290*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0203 */
/*02a0*/ IADD3 R10, R0.reuse, -UR4, RZ ; /* 0x80000004000a7c10 */
/* 0x040fe4000fffe0ff */
/*02b0*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100604067981 */
/* 0x000ea2000c1e1b00 */
/*02c0*/ IADD3 R12, R0, UR4, RZ ; /* 0x00000004000c7c10 */
/* 0x000fe4000fffe0ff */
/*02d0*/ IMAD.WIDE R10, R10, R3.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe200078e0203 */
/*02e0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea6000c1e1b00 */
/*02f0*/ IMAD.WIDE R12, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe400078e0203 */
/*0300*/ LDG.E.64 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee4000c1e1b00 */
/*0310*/ IMAD.WIDE R14, R0, R3, c[0x0][0x170] ; /* 0x00005c00000e7625 */
/* 0x000fc400078e0203 */
/*0320*/ LDG.E.64 R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f28000c1e1b00 */
/*0330*/ LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f62000c1e1b00 */
/*0340*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0203 */
/*0350*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004ecc0000000008 */
/*0360*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x008f0c000000000a */
/*0370*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x010f4c000000000c */
/*0380*/ DFMA R6, R14, c[0x0][0x180], R6 ; /* 0x000060000e067a2b */
/* 0x020e0c0000000006 */
/*0390*/ DMUL R6, R6, 0.25 ; /* 0x3fd0000006067828 */
/* 0x001e0e0000000000 */
/*03a0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b06 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6jacobiPdS_S_id
.globl _Z6jacobiPdS_S_id
.p2align 8
.type _Z6jacobiPdS_S_id,@function
_Z6jacobiPdS_S_id:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v0
s_add_i32 s4, s2, s3
s_add_i32 s8, s2, 2
s_xor_b32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
v_add_nc_u32_e32 v4, v0, v3
v_add_nc_u32_e32 v0, s8, v0
v_rcp_iflag_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s3, v3
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v4, 1, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_lshl_add_u32 v0, v1, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_subrev_nc_u32_e32 v7, s8, v2
v_add_nc_u32_e32 v9, s8, v2
v_lshlrev_b64 v[3:4], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[5:6], v[5:6], off offset:8
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_lshlrev_b64 v[9:10], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v11, vcc_lo, s2, v3
global_load_b64 v[9:10], v[9:10], off
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(3)
v_add_f64 v[0:1], v[0:1], v[5:6]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[0:1], v[9:10]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[11:12], s[0:1], v[0:1]
v_ldexp_f64 v[0:1], v[0:1], -2
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6jacobiPdS_S_id
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6jacobiPdS_S_id, .Lfunc_end0-_Z6jacobiPdS_S_id
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6jacobiPdS_S_id
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6jacobiPdS_S_id.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014925a_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id
.type _Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id, @function
_Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id:
.LFB2081:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6jacobiPdS_S_id(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id, .-_Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id
.globl _Z6jacobiPdS_S_id
.type _Z6jacobiPdS_S_id, @function
_Z6jacobiPdS_S_id:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6jacobiPdS_S_idPdS_S_id
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z6jacobiPdS_S_id, .-_Z6jacobiPdS_S_id
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6jacobiPdS_S_id"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6jacobiPdS_S_id(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "jacobi.hip"
.globl _Z21__device_stub__jacobiPdS_S_id # -- Begin function _Z21__device_stub__jacobiPdS_S_id
.p2align 4, 0x90
.type _Z21__device_stub__jacobiPdS_S_id,@function
_Z21__device_stub__jacobiPdS_S_id: # @_Z21__device_stub__jacobiPdS_S_id
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movsd %xmm0, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6jacobiPdS_S_id, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__jacobiPdS_S_id, .Lfunc_end0-_Z21__device_stub__jacobiPdS_S_id
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6jacobiPdS_S_id, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6jacobiPdS_S_id,@object # @_Z6jacobiPdS_S_id
.section .rodata,"a",@progbits
.globl _Z6jacobiPdS_S_id
.p2align 3, 0x0
_Z6jacobiPdS_S_id:
.quad _Z21__device_stub__jacobiPdS_S_id
.size _Z6jacobiPdS_S_id, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6jacobiPdS_S_id"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__jacobiPdS_S_id
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6jacobiPdS_S_id
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} | code for sm_80
Function : _Z15check_if_uniquePKjPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0x1b0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe40000011600 */
/*0100*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fe20007f1e0ff */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0003 */
/*0120*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x000fc600007fe4ff */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R6, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f3e0ff */
/*0160*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fe40000ffe4ff */
/*0170*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fc80003f05270 */
/*0180*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fca0004000000 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} | .file "tmpxft_001670ac_00000000-6_check_if_unique.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
.type _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm, @function
_Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15check_if_uniquePKjPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm, .-_Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
.globl _Z15check_if_uniquePKjPjm
.type _Z15check_if_uniquePKjPjm, @function
_Z15check_if_uniquePKjPjm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15check_if_uniquePKjPjm, .-_Z15check_if_uniquePKjPjm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15check_if_uniquePKjPjm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15check_if_uniquePKjPjm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15check_if_uniquePKjPjm
.globl _Z15check_if_uniquePKjPjm
.p2align 8
.type _Z15check_if_uniquePKjPjm,@function
_Z15check_if_uniquePKjPjm:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execnz .LBB0_6
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v2, v0
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15check_if_uniquePKjPjm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15check_if_uniquePKjPjm, .Lfunc_end0-_Z15check_if_uniquePKjPjm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15check_if_uniquePKjPjm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15check_if_uniquePKjPjm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_if_unique(const unsigned *keys, unsigned *is_unique, size_t kSize) {
unsigned id = threadIdx.x +
blockIdx.x * blockDim.x +
blockIdx.y * blockDim.x * gridDim.x;
if (id == 0) {
is_unique[0] = 1;
} else if (id < kSize) {
is_unique[id] = (keys[id] != keys[id - 1] ? 1 : 0);
}
} | .text
.file "check_if_unique.hip"
.globl _Z30__device_stub__check_if_uniquePKjPjm # -- Begin function _Z30__device_stub__check_if_uniquePKjPjm
.p2align 4, 0x90
.type _Z30__device_stub__check_if_uniquePKjPjm,@function
_Z30__device_stub__check_if_uniquePKjPjm: # @_Z30__device_stub__check_if_uniquePKjPjm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15check_if_uniquePKjPjm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__check_if_uniquePKjPjm, .Lfunc_end0-_Z30__device_stub__check_if_uniquePKjPjm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15check_if_uniquePKjPjm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15check_if_uniquePKjPjm,@object # @_Z15check_if_uniquePKjPjm
.section .rodata,"a",@progbits
.globl _Z15check_if_uniquePKjPjm
.p2align 3, 0x0
_Z15check_if_uniquePKjPjm:
.quad _Z30__device_stub__check_if_uniquePKjPjm
.size _Z15check_if_uniquePKjPjm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15check_if_uniquePKjPjm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__check_if_uniquePKjPjm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15check_if_uniquePKjPjm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15check_if_uniquePKjPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0x1b0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe40000011600 */
/*0100*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fe20007f1e0ff */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0003 */
/*0120*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x000fc600007fe4ff */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R6, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f3e0ff */
/*0160*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fe40000ffe4ff */
/*0170*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fc80003f05270 */
/*0180*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fca0004000000 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15check_if_uniquePKjPjm
.globl _Z15check_if_uniquePKjPjm
.p2align 8
.type _Z15check_if_uniquePKjPjm,@function
_Z15check_if_uniquePKjPjm:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execnz .LBB0_6
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v2, v0
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15check_if_uniquePKjPjm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15check_if_uniquePKjPjm, .Lfunc_end0-_Z15check_if_uniquePKjPjm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15check_if_uniquePKjPjm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15check_if_uniquePKjPjm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001670ac_00000000-6_check_if_unique.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
.type _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm, @function
_Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15check_if_uniquePKjPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm, .-_Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
.globl _Z15check_if_uniquePKjPjm
.type _Z15check_if_uniquePKjPjm, @function
_Z15check_if_uniquePKjPjm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15check_if_uniquePKjPjmPKjPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15check_if_uniquePKjPjm, .-_Z15check_if_uniquePKjPjm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15check_if_uniquePKjPjm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15check_if_uniquePKjPjm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_if_unique.hip"
.globl _Z30__device_stub__check_if_uniquePKjPjm # -- Begin function _Z30__device_stub__check_if_uniquePKjPjm
.p2align 4, 0x90
.type _Z30__device_stub__check_if_uniquePKjPjm,@function
_Z30__device_stub__check_if_uniquePKjPjm: # @_Z30__device_stub__check_if_uniquePKjPjm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15check_if_uniquePKjPjm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__check_if_uniquePKjPjm, .Lfunc_end0-_Z30__device_stub__check_if_uniquePKjPjm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15check_if_uniquePKjPjm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15check_if_uniquePKjPjm,@object # @_Z15check_if_uniquePKjPjm
.section .rodata,"a",@progbits
.globl _Z15check_if_uniquePKjPjm
.p2align 3, 0x0
_Z15check_if_uniquePKjPjm:
.quad _Z30__device_stub__check_if_uniquePKjPjm
.size _Z15check_if_uniquePKjPjm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15check_if_uniquePKjPjm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__check_if_uniquePKjPjm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15check_if_uniquePKjPjm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} | code for sm_80
Function : _Z8aypb_i32iPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R5, R0, R5, c[0x0][0x170] ; /* 0x00005c0000057624 */
/* 0x004fca00078e0205 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} | .file "tmpxft_00082c70_00000000-6_aypb_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8aypb_i32iPiiiiPiii
.type _Z30__device_stub__Z8aypb_i32iPiiiiPiii, @function
_Z30__device_stub__Z8aypb_i32iPiiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8aypb_i32iPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8aypb_i32iPiiiiPiii, .-_Z30__device_stub__Z8aypb_i32iPiiiiPiii
.globl _Z8aypb_i32iPiii
.type _Z8aypb_i32iPiii, @function
_Z8aypb_i32iPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8aypb_i32iPiiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8aypb_i32iPiii, .-_Z8aypb_i32iPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8aypb_i32iPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8aypb_i32iPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8aypb_i32iPiii
.globl _Z8aypb_i32iPiii
.p2align 8
.type _Z8aypb_i32iPiii,@function
_Z8aypb_i32iPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, s0, s[4:5]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8aypb_i32iPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8aypb_i32iPiii, .Lfunc_end0-_Z8aypb_i32iPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8aypb_i32iPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8aypb_i32iPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aypb_i32 (int a, int* y, int b, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
y[idx] = a * y[idx] + b;
}
} | .text
.file "aypb_i32.hip"
.globl _Z23__device_stub__aypb_i32iPiii # -- Begin function _Z23__device_stub__aypb_i32iPiii
.p2align 4, 0x90
.type _Z23__device_stub__aypb_i32iPiii,@function
_Z23__device_stub__aypb_i32iPiii: # @_Z23__device_stub__aypb_i32iPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8aypb_i32iPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__aypb_i32iPiii, .Lfunc_end0-_Z23__device_stub__aypb_i32iPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8aypb_i32iPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8aypb_i32iPiii,@object # @_Z8aypb_i32iPiii
.section .rodata,"a",@progbits
.globl _Z8aypb_i32iPiii
.p2align 3, 0x0
_Z8aypb_i32iPiii:
.quad _Z23__device_stub__aypb_i32iPiii
.size _Z8aypb_i32iPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8aypb_i32iPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__aypb_i32iPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8aypb_i32iPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8aypb_i32iPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R5, R0, R5, c[0x0][0x170] ; /* 0x00005c0000057624 */
/* 0x004fca00078e0205 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8aypb_i32iPiii
.globl _Z8aypb_i32iPiii
.p2align 8
.type _Z8aypb_i32iPiii,@function
_Z8aypb_i32iPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, s0, s[4:5]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8aypb_i32iPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8aypb_i32iPiii, .Lfunc_end0-_Z8aypb_i32iPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8aypb_i32iPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8aypb_i32iPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00082c70_00000000-6_aypb_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8aypb_i32iPiiiiPiii
.type _Z30__device_stub__Z8aypb_i32iPiiiiPiii, @function
_Z30__device_stub__Z8aypb_i32iPiiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8aypb_i32iPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8aypb_i32iPiiiiPiii, .-_Z30__device_stub__Z8aypb_i32iPiiiiPiii
.globl _Z8aypb_i32iPiii
.type _Z8aypb_i32iPiii, @function
_Z8aypb_i32iPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8aypb_i32iPiiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8aypb_i32iPiii, .-_Z8aypb_i32iPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8aypb_i32iPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8aypb_i32iPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aypb_i32.hip"
.globl _Z23__device_stub__aypb_i32iPiii # -- Begin function _Z23__device_stub__aypb_i32iPiii
.p2align 4, 0x90
.type _Z23__device_stub__aypb_i32iPiii,@function
_Z23__device_stub__aypb_i32iPiii: # @_Z23__device_stub__aypb_i32iPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8aypb_i32iPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__aypb_i32iPiii, .Lfunc_end0-_Z23__device_stub__aypb_i32iPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8aypb_i32iPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8aypb_i32iPiii,@object # @_Z8aypb_i32iPiii
.section .rodata,"a",@progbits
.globl _Z8aypb_i32iPiii
.p2align 3, 0x0
_Z8aypb_i32iPiii:
.quad _Z23__device_stub__aypb_i32iPiii
.size _Z8aypb_i32iPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8aypb_i32iPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__aypb_i32iPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8aypb_i32iPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(cudaGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
cudaEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
cudaEventCreate(&start); // инициализация
cudaEventCreate(&stop); // событий
cudaEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
cudaDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
cudaEventRecord(stop,0); // привязка события stop
cudaEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
cudaEventDestroy(start); // освобождение
cudaEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(cudaGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
cudaFree(vector1_d);
cudaFree(vector2_d);
cudaFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} | code for sm_80
Function : _Z15gVectorAdditionPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GT.AND P0, PT, R8, 0xfffff, PT ; /* 0x000fffff0800780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12gInitVectorsPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0d7624 */
/* 0x000fe200078e00ff */
/*0020*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe200078e00ff */
/*0060*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe20000000000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ UMOV UR5, 0x7 ; /* 0x0000000700057882 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, 0xf ; /* 0x0000000fff007424 */
/* 0x000fe200078e00ff */
/*00a0*/ UMOV UR6, 0x6 ; /* 0x0000000600067882 */
/* 0x000fe40000000000 */
/*00b0*/ UMOV UR7, 0x5 ; /* 0x0000000500077882 */
/* 0x000fc40000000000 */
/*00c0*/ UMOV UR8, 0x4 ; /* 0x0000000400087882 */
/* 0x000fe40000000000 */
/*00d0*/ UMOV UR9, 0x3 ; /* 0x0000000300097882 */
/* 0x000fe40000000000 */
/*00e0*/ UMOV UR10, 0x2 ; /* 0x00000002000a7882 */
/* 0x000fe40000000000 */
/*00f0*/ UMOV UR11, 0x1 ; /* 0x00000001000b7882 */
/* 0x000fe40000000000 */
/*0100*/ I2F.F64 R26, UR11 ; /* 0x0000000b001a7d12 */
/* 0x000e220008201c00 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0120*/ IADD3 R16, R0.reuse, -0x6, RZ ; /* 0xfffffffa00107810 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000d */
/*0140*/ IADD3 R14, R0.reuse, -0x5, RZ ; /* 0xfffffffb000e7810 */
/* 0x040fe20007ffe0ff */
/*0150*/ UIADD3 UR11, UR11, 0x10, URZ ; /* 0x000000100b0b7890 */
/* 0x000fe2000fffe03f */
/*0160*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b0c */
/*0170*/ IADD3 R12, R0, -0x4, RZ ; /* 0xfffffffc000c7810 */
/* 0x000fe20007ffe0ff */
/*0180*/ I2F.F64 R28, UR10 ; /* 0x0000000a001c7d12 */
/* 0x000e620008201c00 */
/*0190*/ UIADD3 UR10, UR10, 0x10, URZ ; /* 0x000000100a0a7890 */
/* 0x000fe2000fffe03f */
/*01a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0005ec000c101b0c */
/*01b0*/ I2F.F64 R24, UR9 ; /* 0x0000000900187d12 */
/* 0x000ee20008201c00 */
/*01c0*/ STG.E.64 [R4.64+0x8], R26 ; /* 0x0000081a04007986 */
/* 0x001fe2000c101b0c */
/*01d0*/ UIADD3 UR9, UR9, 0x10, URZ ; /* 0x0000001009097890 */
/* 0x000fc6000fffe03f */
/*01e0*/ STG.E.64 [R6.64+0x8], R26 ; /* 0x0000081a06007986 */
/* 0x0001e6000c101b0c */
/*01f0*/ I2F.F64 R22, UR8 ; /* 0x0000000800167d12 */
/* 0x000f220008201c00 */
/*0200*/ STG.E.64 [R4.64+0x10], R28 ; /* 0x0000101c04007986 */
/* 0x002fe2000c101b0c */
/*0210*/ UIADD3 UR8, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000fffe03f */
/*0220*/ DADD R2, R2, 16 ; /* 0x4030000002027429 */
/* 0x004e640000000000 */
/*0230*/ STG.E.64 [R6.64+0x10], R28 ; /* 0x0000101c06007986 */
/* 0x0005e6000c101b0c */
/*0240*/ I2F.F64 R20, UR7 ; /* 0x0000000700147d12 */
/* 0x000f620008201c00 */
/*0250*/ STG.E.64 [R4.64+0x18], R24 ; /* 0x0000181804007986 */
/* 0x008fe2000c101b0c */
/*0260*/ UIADD3 UR7, UR7, 0x10, URZ ; /* 0x0000001007077890 */
/* 0x000fe2000fffe03f */
/*0270*/ IADD3 R26, R0, -0x3, RZ ; /* 0xfffffffd001a7810 */
/* 0x001fc40007ffe0ff */
/*0280*/ STG.E.64 [R6.64+0x18], R24 ; /* 0x0000181806007986 */
/* 0x0001e6000c101b0c */
/*0290*/ I2F.F64 R10, UR6 ; /* 0x00000006000a7d12 */
/* 0x000ee20008201c00 */
/*02a0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x010fe2000c101b0c */
/*02b0*/ UIADD3 UR6, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000fffe03f */
/*02c0*/ IADD3 R28, R0.reuse, -0x2, RZ ; /* 0xfffffffe001c7810 */
/* 0x044fe40007ffe0ff */
/*02d0*/ STG.E.64 [R6.64+0x20], R22 ; /* 0x0000201606007986 */
/* 0x0005e6000c101b0c */
/*02e0*/ I2F.F64 R18, UR5 ; /* 0x0000000500127d12 */
/* 0x000f220008201c00 */
/*02f0*/ STG.E.64 [R4.64+0x28], R20 ; /* 0x0000281404007986 */
/* 0x020fe2000c101b0c */
/*0300*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*0310*/ IADD3 R24, R0, -0x1, RZ ; /* 0xffffffff00187810 */
/* 0x001fc40007ffe0ff */
/*0320*/ STG.E.64 [R6.64+0x28], R20 ; /* 0x0000281406007986 */
/* 0x000fe6000c101b0c */
/*0330*/ I2F.F64 R8, UR4 ; /* 0x0000000400087d12 */
/* 0x000e220008201c00 */
/*0340*/ STG.E.64 [R4.64+0x30], R10 ; /* 0x0000300a04007986 */
/* 0x008fe2000c101b0c */
/*0350*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0360*/ STG.E.64 [R6.64+0x30], R10 ; /* 0x0000300a06007986 */
/* 0x000fe6000c101b0c */
/*0370*/ I2F.F64 R16, R16 ; /* 0x0000001000107312 */
/* 0x000ee20000201c00 */
/*0380*/ STG.E.64 [R4.64+0x38], R18 ; /* 0x0000381204007986 */
/* 0x010fe8000c101b0c */
/*0390*/ STG.E.64 [R6.64+0x38], R18 ; /* 0x0000381206007986 */
/* 0x000fe6000c101b0c */
/*03a0*/ I2F.F64 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x000f220000201c00 */
/*03b0*/ STG.E.64 [R4.64+0x40], R8 ; /* 0x0000400804007986 */
/* 0x001fe8000c101b0c */
/*03c0*/ STG.E.64 [R6.64+0x40], R8 ; /* 0x0000400806007986 */
/* 0x000fe6000c101b0c */
/*03d0*/ I2F.F64 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000e220000201c00 */
/*03e0*/ STG.E.64 [R4.64+0x48], R16 ; /* 0x0000481004007986 */
/* 0x008fe8000c101b0c */
/*03f0*/ STG.E.64 [R6.64+0x48], R16 ; /* 0x0000481006007986 */
/* 0x000fe6000c101b0c */
/*0400*/ I2F.F64 R26, R26 ; /* 0x0000001a001a7312 */
/* 0x000ee20000201c00 */
/*0410*/ STG.E.64 [R4.64+0x50], R14 ; /* 0x0000500e04007986 */
/* 0x010fe8000c101b0c */
/*0420*/ STG.E.64 [R6.64+0x50], R14 ; /* 0x0000500e06007986 */
/* 0x000fe6000c101b0c */
/*0430*/ I2F.F64 R28, R28 ; /* 0x0000001c001c7312 */
/* 0x000f220000201c00 */
/*0440*/ STG.E.64 [R4.64+0x58], R12 ; /* 0x0000580c04007986 */
/* 0x001fe8000c101b0c */
/*0450*/ STG.E.64 [R6.64+0x58], R12 ; /* 0x0000580c06007986 */
/* 0x0001e6000c101b0c */
/*0460*/ I2F.F64 R24, R24 ; /* 0x0000001800187312 */
/* 0x000f620000201c00 */
/*0470*/ STG.E.64 [R4.64+0x60], R26 ; /* 0x0000601a04007986 */
/* 0x008fe8000c101b0c */
/*0480*/ STG.E.64 [R6.64+0x60], R26 ; /* 0x0000601a06007986 */
/* 0x000fe6000c101b0c */
/*0490*/ I2F.F64 R22, R0 ; /* 0x0000000000167312 */
/* 0x0044e20000201c00 */
/*04a0*/ STG.E.64 [R4.64+0x68], R28 ; /* 0x0000681c04007986 */
/* 0x010fe2000c101b0c */
/*04b0*/ IADD3 R12, P1, R4, 0x80, RZ ; /* 0x00000080040c7810 */
/* 0x001fc60007f3e0ff */
/*04c0*/ STG.E.64 [R6.64+0x68], R28 ; /* 0x0000681c06007986 */
/* 0x000fe2000c101b0c */
/*04d0*/ IADD3 R13, P2, R6, 0x80, RZ ; /* 0x00000080060d7810 */
/* 0x000fe40007f5e0ff */
/*04e0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x004fe20007ffe0ff */
/*04f0*/ STG.E.64 [R4.64+0x70], R24 ; /* 0x0000701804007986 */
/* 0x020fe6000c101b0c */
/*0500*/ ISETP.NE.AND P0, PT, R0, 0x10000f, PT ; /* 0x0010000f0000780c */
/* 0x000fe20003f05270 */
/*0510*/ STG.E.64 [R6.64+0x70], R24 ; /* 0x0000701806007986 */
/* 0x000fe8000c101b0c */
/*0520*/ STG.E.64 [R4.64+0x78], R22 ; /* 0x0000781604007986 */
/* 0x0081e8000c101b0c */
/*0530*/ STG.E.64 [R6.64+0x78], R22 ; /* 0x0000781606007986 */
/* 0x0005e2000c101b0c */
/*0540*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x001fc400008e0605 */
/*0550*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x004fe200010e0607 */
/*0560*/ @P0 BRA 0x100 ; /* 0xfffffb9000000947 */
/* 0x002fea000383ffff */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(cudaGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
cudaEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
cudaEventCreate(&start); // инициализация
cudaEventCreate(&stop); // событий
cudaEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
cudaDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
cudaEventRecord(stop,0); // привязка события stop
cudaEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
cudaEventDestroy(start); // освобождение
cudaEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(cudaGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
cudaFree(vector1_d);
cudaFree(vector2_d);
cudaFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} | .file "tmpxft_001330fa_00000000-6_lab2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12gInitVectorsPdS_PdS_
.type _Z34__device_stub__Z12gInitVectorsPdS_PdS_, @function
_Z34__device_stub__Z12gInitVectorsPdS_PdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12gInitVectorsPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z12gInitVectorsPdS_PdS_, .-_Z34__device_stub__Z12gInitVectorsPdS_PdS_
.globl _Z12gInitVectorsPdS_
.type _Z12gInitVectorsPdS_, @function
_Z12gInitVectorsPdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12gInitVectorsPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12gInitVectorsPdS_, .-_Z12gInitVectorsPdS_
.globl _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
.type _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i, @function
_Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gVectorAdditionPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i, .-_Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.type _Z15gVectorAdditionPdS_S_i, @function
_Z15gVectorAdditionPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15gVectorAdditionPdS_S_i, .-_Z15gVectorAdditionPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gedenteen/CUDA/main/lab2/lab2.cu"
.align 8
.LC1:
.string "Error \"%s\" at line %d in file %s\n"
.align 8
.LC3:
.string "blocks = %d, threads per block = %d milliseconds = %e \n"
.text
.globl _Z22testingThreadsOfDeviceii
.type _Z22testingThreadsOfDeviceii, @function
_Z22testingThreadsOfDeviceii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
movl $32, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
cmpl $1, %ebp
je .L38
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
.L26:
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1048576, %eax
movl $0, %edx
idivl %ebx
movl %eax, %r12d
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L27:
call cudaDeviceSynchronize@PLT
cmpl $1, %ebp
je .L40
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
leaq 52(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
.L29:
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movss 52(%rsp), %xmm0
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $34, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $36, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $37, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12gInitVectorsPdS_PdS_
jmp .L23
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $39, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
jmp .L26
.L39:
movl %ebx, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
jmp .L27
.L40:
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 52(%rsp)
jmp .L29
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $65, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $69, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z22testingThreadsOfDeviceii, .-_Z22testingThreadsOfDeviceii
.section .rodata.str1.8
.align 8
.LC5:
.string "\n time in milliseconds by clock_gettime:\n"
.align 8
.LC6:
.string "\t avg_time = %e min_time = %e max_time = %e\n\n"
.align 8
.LC7:
.string "\n time in milliseconds by Events:\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $1, %r13d
leaq .LC7(%rip), %r15
leaq .LC6(%rip), %r14
.L51:
movl %r13d, %esi
movl $32, %edi
call _Z22testingThreadsOfDeviceii
movss %xmm0, 4(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movl $5, %ebp
movl $64, %ebx
movl .LC4(%rip), %r12d
.L47:
movl %r13d, %esi
movl %ebx, %edi
call _Z22testingThreadsOfDeviceii
movaps %xmm0, %xmm3
maxss 8(%rsp), %xmm3
movss %xmm3, 8(%rsp)
movaps %xmm0, %xmm4
minss 4(%rsp), %xmm4
movss %xmm4, 4(%rsp)
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movd %r12d, %xmm5
addss .LC4(%rip), %xmm5
movd %xmm5, %r12d
addl %ebx, %ebx
subl $1, %ebp
jne .L47
movaps %xmm0, %xmm6
divss %xmm5, %xmm6
movss %xmm6, 12(%rsp)
cmpl $1, %r13d
je .L56
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl $3, %r13d
jne .L51
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %r13d
jmp .L51
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z15gVectorAdditionPdS_S_i"
.LC9:
.string "_Z12gInitVectorsPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gVectorAdditionPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gInitVectorsPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(cudaMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(cudaGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
cudaEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
cudaEventCreate(&start); // инициализация
cudaEventCreate(&stop); // событий
cudaEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
cudaDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
cudaEventRecord(stop,0); // привязка события stop
cudaEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
cudaEventDestroy(start); // освобождение
cudaEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(cudaGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
cudaFree(vector1_d);
cudaFree(vector2_d);
cudaFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(hipMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(hipMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(hipMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(hipGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
hipEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
hipEventCreate(&start); // инициализация
hipEventCreate(&stop); // событий
hipEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
hipDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
hipEventRecord(stop,0); // привязка события stop
hipEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
hipEventDestroy(start); // освобождение
hipEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(hipGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
hipFree(vector1_d);
hipFree(vector2_d);
hipFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(hipMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(hipMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(hipMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(hipGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
hipEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
hipEventCreate(&start); // инициализация
hipEventCreate(&stop); // событий
hipEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
hipDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
hipEventRecord(stop,0); // привязка события stop
hipEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
hipEventDestroy(start); // освобождение
hipEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(hipGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
hipFree(vector1_d);
hipFree(vector2_d);
hipFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gInitVectorsPdS_
.globl _Z12gInitVectorsPdS_
.p2align 8
.type _Z12gInitVectorsPdS_,@function
_Z12gInitVectorsPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_clause 0x1
global_store_b64 v2, v[0:1], s[6:7]
global_store_b64 v2, v[0:1], s[8:9]
v_add_f64 v[0:1], v[0:1], 1.0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 0x800000
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gInitVectorsPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gInitVectorsPdS_, .Lfunc_end0-_Z12gInitVectorsPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15gVectorAdditionPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.p2align 8
.type _Z15gVectorAdditionPdS_S_i,@function
_Z15gVectorAdditionPdS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gVectorAdditionPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15gVectorAdditionPdS_S_i, .Lfunc_end1-_Z15gVectorAdditionPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gInitVectorsPdS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12gInitVectorsPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gVectorAdditionPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gVectorAdditionPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <malloc.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error \"%s\" at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}\
} //макрос для обработки ошибок
const int N = 1 << 20;
__global__ void gInitVectors(double* vector1, double* vector2) {
for (int i = 0; i < N; i++) {
vector1[i] = (double)i; //rand();
vector2[i] = (double)i;
}
}
__global__ void gVectorAddition(double* vector1, double* vector2, double* vectorSum, int threads_cnt) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= N)
return;
vectorSum[i] = vector1[i] + vector2[i];
}
float testingThreadsOfDevice(int threads_cnt, int type_time) {
double *vectorSum_d, *vectorSum_h;
vectorSum_h = (double*) calloc(N, sizeof(double));
CUDA_CHECK_RETURN(hipMalloc((void**)&vectorSum_d, N * sizeof(double)));
double *vector1_d, *vector2_d;
CUDA_CHECK_RETURN(hipMalloc((void**)&vector1_d, N * sizeof(double)));
CUDA_CHECK_RETURN(hipMalloc((void**)&vector2_d, N * sizeof(double)));
gInitVectors <<< 1, 32 >>> (vector1_d, vector2_d);
CUDA_CHECK_RETURN(hipGetLastError());
float elapsedTime;
struct timespec mt1, mt2; //для type_time = 1
hipEvent_t start, stop; //для type_time = 2
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt1);
}
else {
hipEventCreate(&start); // инициализация
hipEventCreate(&stop); // событий
hipEventRecord(start,0); // привязка (регистрация) события start
}
gVectorAddition <<< N / threads_cnt, threads_cnt >>>
(vector1_d, vector2_d, vectorSum_d, threads_cnt); //запуск фу-ии на GPU
hipDeviceSynchronize(); //синхронизация потоков
if (type_time == 1) {
clock_gettime(CLOCK_REALTIME, &mt2);
elapsedTime = (float)(mt2.tv_sec - mt1.tv_sec) +
(float)(mt2.tv_nsec - mt1.tv_nsec) / 1e6; ///время в миллисекундах
}
else {
hipEventRecord(stop,0); // привязка события stop
hipEventSynchronize(stop); // синхронизация по событию
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime,start,stop); // вычисление затраченного времени
hipEventDestroy(start); // освобождение
hipEventDestroy(stop); // памяти
CUDA_CHECK_RETURN(hipGetLastError());
}
printf("blocks = %d, threads per block = %d milliseconds = %e \n",
N / threads_cnt, threads_cnt, elapsedTime);
/// проверка: ///
/*cudaMemcpy(vectorSum_h, vectorSum_d, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
fprintf(stderr, "%g ", vectorSum_h[i]);
printf("\n");
*/
hipFree(vector1_d);
hipFree(vector2_d);
hipFree(vectorSum_d);
free(vectorSum_h);
return elapsedTime;
}
int main() {
for (int type_time = 1; type_time <= 2; type_time++) {
float min_time, max_time, avg_time, cnt_tests = 1;
//запустить тест с 32 потоками на блок:
min_time = max_time = avg_time = testingThreadsOfDevice(32, type_time);
for (int i = 64; i <= 1024; i *= 2) {
float new_time = testingThreadsOfDevice(i, type_time);
if (new_time > max_time)
max_time = new_time;
if (new_time < min_time)
min_time = new_time;
avg_time += new_time;
cnt_tests++;
}
avg_time = avg_time / cnt_tests;
if (type_time == 1)
printf("\n time in milliseconds by clock_gettime:\n");
else
printf("\n time in milliseconds by Events:\n");
printf("\t avg_time = %e min_time = %e max_time = %e\n\n", avg_time, min_time, max_time);
}
return 0;
} | .text
.file "lab2.hip"
.globl _Z27__device_stub__gInitVectorsPdS_ # -- Begin function _Z27__device_stub__gInitVectorsPdS_
.p2align 4, 0x90
.type _Z27__device_stub__gInitVectorsPdS_,@function
_Z27__device_stub__gInitVectorsPdS_: # @_Z27__device_stub__gInitVectorsPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12gInitVectorsPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__gInitVectorsPdS_, .Lfunc_end0-_Z27__device_stub__gInitVectorsPdS_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gVectorAdditionPdS_S_i # -- Begin function _Z30__device_stub__gVectorAdditionPdS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__gVectorAdditionPdS_S_i,@function
_Z30__device_stub__gVectorAdditionPdS_S_i: # @_Z30__device_stub__gVectorAdditionPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gVectorAdditionPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__gVectorAdditionPdS_S_i, .Lfunc_end1-_Z30__device_stub__gVectorAdditionPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22testingThreadsOfDeviceii
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z22testingThreadsOfDeviceii
.p2align 4, 0x90
.type _Z22testingThreadsOfDeviceii,@function
_Z22testingThreadsOfDeviceii: # @_Z22testingThreadsOfDeviceii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
leaq 120(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rdi
leaq 32(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12gInitVectorsPdS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11:
cmpl $1, %ebp
jne .LBB2_13
# %bb.12:
leaq 104(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
jmp .LBB2_14
.LBB2_13:
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
.LBB2_14:
movl $1048576, %eax # imm = 0x100000
xorl %edx, %edx
idivl %ebx
movl %eax, %r14d
movq %r14, %rdi
orq %r15, %rdi
movl %ebx, %edx
orq %r15, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 120(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ebx, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 176(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15gVectorAdditionPdS_S_i, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
callq hipDeviceSynchronize
cmpl $1, %ebp
jne .LBB2_19
# %bb.17:
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 128(%rsp), %rax
subq 104(%rsp), %rax
cvtsi2ss %rax, %xmm0
movq 136(%rsp), %rax
subq 112(%rsp), %rax
cvtsi2ss %rax, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 8(%rsp)
jmp .LBB2_18
.LBB2_19:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
.LBB2_18:
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %r14d, %esi
movl %ebx, %edx
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $36, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $39, %ecx
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $41, %ecx
jmp .LBB2_2
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $67, %ecx
jmp .LBB2_2
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %ecx
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z22testingThreadsOfDeviceii, .Lfunc_end2-_Z22testingThreadsOfDeviceii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
movl $.Lstr.1, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl $32, %edi
movl %ebx, %esi
callq _Z22testingThreadsOfDeviceii
movaps %xmm0, %xmm1
movl $64, %r14d
movss .LCPI3_0(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm3, 4(%rsp) # 4-byte Spill
movss %xmm1, 8(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movss %xmm2, 12(%rsp) # 4-byte Spill
movl %r14d, %edi
movl %ebx, %esi
callq _Z22testingThreadsOfDeviceii
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
maxss 12(%rsp), %xmm2 # 4-byte Folded Reload
addss %xmm0, %xmm1
minss (%rsp), %xmm0 # 4-byte Folded Reload
addss .LCPI3_0(%rip), %xmm3
leal (%r14,%r14), %eax
cmpl $513, %r14d # imm = 0x201
movl %eax, %r14d
jb .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
divss %xmm3, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
cmpl $1, %ebx
movl $.Lstr, %edi
cmoveq %r15, %rdi
movss %xmm2, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 4(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
incl %ebx
cmpl $3, %ebx
jne .LBB3_1
# %bb.4:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gInitVectorsPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gVectorAdditionPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gInitVectorsPdS_,@object # @_Z12gInitVectorsPdS_
.section .rodata,"a",@progbits
.globl _Z12gInitVectorsPdS_
.p2align 3, 0x0
_Z12gInitVectorsPdS_:
.quad _Z27__device_stub__gInitVectorsPdS_
.size _Z12gInitVectorsPdS_, 8
.type _Z15gVectorAdditionPdS_S_i,@object # @_Z15gVectorAdditionPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.p2align 3, 0x0
_Z15gVectorAdditionPdS_S_i:
.quad _Z30__device_stub__gVectorAdditionPdS_S_i
.size _Z15gVectorAdditionPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error \"%s\" at line %d in file %s\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gedenteen/CUDA/main/lab2/lab2.hip"
.size .L.str.1, 91
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "blocks = %d, threads per block = %d milliseconds = %e \n"
.size .L.str.2, 56
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\t avg_time = %e min_time = %e max_time = %e\n\n"
.size .L.str.5, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12gInitVectorsPdS_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15gVectorAdditionPdS_S_i"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n time in milliseconds by Events:"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n time in milliseconds by clock_gettime:"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gInitVectorsPdS_
.addrsig_sym _Z30__device_stub__gVectorAdditionPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gInitVectorsPdS_
.addrsig_sym _Z15gVectorAdditionPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15gVectorAdditionPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GT.AND P0, PT, R8, 0xfffff, PT ; /* 0x000fffff0800780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12gInitVectorsPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0d7624 */
/* 0x000fe200078e00ff */
/*0020*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe200078e00ff */
/*0060*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe20000000000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ UMOV UR5, 0x7 ; /* 0x0000000700057882 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, 0xf ; /* 0x0000000fff007424 */
/* 0x000fe200078e00ff */
/*00a0*/ UMOV UR6, 0x6 ; /* 0x0000000600067882 */
/* 0x000fe40000000000 */
/*00b0*/ UMOV UR7, 0x5 ; /* 0x0000000500077882 */
/* 0x000fc40000000000 */
/*00c0*/ UMOV UR8, 0x4 ; /* 0x0000000400087882 */
/* 0x000fe40000000000 */
/*00d0*/ UMOV UR9, 0x3 ; /* 0x0000000300097882 */
/* 0x000fe40000000000 */
/*00e0*/ UMOV UR10, 0x2 ; /* 0x00000002000a7882 */
/* 0x000fe40000000000 */
/*00f0*/ UMOV UR11, 0x1 ; /* 0x00000001000b7882 */
/* 0x000fe40000000000 */
/*0100*/ I2F.F64 R26, UR11 ; /* 0x0000000b001a7d12 */
/* 0x000e220008201c00 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0120*/ IADD3 R16, R0.reuse, -0x6, RZ ; /* 0xfffffffa00107810 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000d */
/*0140*/ IADD3 R14, R0.reuse, -0x5, RZ ; /* 0xfffffffb000e7810 */
/* 0x040fe20007ffe0ff */
/*0150*/ UIADD3 UR11, UR11, 0x10, URZ ; /* 0x000000100b0b7890 */
/* 0x000fe2000fffe03f */
/*0160*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b0c */
/*0170*/ IADD3 R12, R0, -0x4, RZ ; /* 0xfffffffc000c7810 */
/* 0x000fe20007ffe0ff */
/*0180*/ I2F.F64 R28, UR10 ; /* 0x0000000a001c7d12 */
/* 0x000e620008201c00 */
/*0190*/ UIADD3 UR10, UR10, 0x10, URZ ; /* 0x000000100a0a7890 */
/* 0x000fe2000fffe03f */
/*01a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0005ec000c101b0c */
/*01b0*/ I2F.F64 R24, UR9 ; /* 0x0000000900187d12 */
/* 0x000ee20008201c00 */
/*01c0*/ STG.E.64 [R4.64+0x8], R26 ; /* 0x0000081a04007986 */
/* 0x001fe2000c101b0c */
/*01d0*/ UIADD3 UR9, UR9, 0x10, URZ ; /* 0x0000001009097890 */
/* 0x000fc6000fffe03f */
/*01e0*/ STG.E.64 [R6.64+0x8], R26 ; /* 0x0000081a06007986 */
/* 0x0001e6000c101b0c */
/*01f0*/ I2F.F64 R22, UR8 ; /* 0x0000000800167d12 */
/* 0x000f220008201c00 */
/*0200*/ STG.E.64 [R4.64+0x10], R28 ; /* 0x0000101c04007986 */
/* 0x002fe2000c101b0c */
/*0210*/ UIADD3 UR8, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000fffe03f */
/*0220*/ DADD R2, R2, 16 ; /* 0x4030000002027429 */
/* 0x004e640000000000 */
/*0230*/ STG.E.64 [R6.64+0x10], R28 ; /* 0x0000101c06007986 */
/* 0x0005e6000c101b0c */
/*0240*/ I2F.F64 R20, UR7 ; /* 0x0000000700147d12 */
/* 0x000f620008201c00 */
/*0250*/ STG.E.64 [R4.64+0x18], R24 ; /* 0x0000181804007986 */
/* 0x008fe2000c101b0c */
/*0260*/ UIADD3 UR7, UR7, 0x10, URZ ; /* 0x0000001007077890 */
/* 0x000fe2000fffe03f */
/*0270*/ IADD3 R26, R0, -0x3, RZ ; /* 0xfffffffd001a7810 */
/* 0x001fc40007ffe0ff */
/*0280*/ STG.E.64 [R6.64+0x18], R24 ; /* 0x0000181806007986 */
/* 0x0001e6000c101b0c */
/*0290*/ I2F.F64 R10, UR6 ; /* 0x00000006000a7d12 */
/* 0x000ee20008201c00 */
/*02a0*/ STG.E.64 [R4.64+0x20], R22 ; /* 0x0000201604007986 */
/* 0x010fe2000c101b0c */
/*02b0*/ UIADD3 UR6, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000fffe03f */
/*02c0*/ IADD3 R28, R0.reuse, -0x2, RZ ; /* 0xfffffffe001c7810 */
/* 0x044fe40007ffe0ff */
/*02d0*/ STG.E.64 [R6.64+0x20], R22 ; /* 0x0000201606007986 */
/* 0x0005e6000c101b0c */
/*02e0*/ I2F.F64 R18, UR5 ; /* 0x0000000500127d12 */
/* 0x000f220008201c00 */
/*02f0*/ STG.E.64 [R4.64+0x28], R20 ; /* 0x0000281404007986 */
/* 0x020fe2000c101b0c */
/*0300*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*0310*/ IADD3 R24, R0, -0x1, RZ ; /* 0xffffffff00187810 */
/* 0x001fc40007ffe0ff */
/*0320*/ STG.E.64 [R6.64+0x28], R20 ; /* 0x0000281406007986 */
/* 0x000fe6000c101b0c */
/*0330*/ I2F.F64 R8, UR4 ; /* 0x0000000400087d12 */
/* 0x000e220008201c00 */
/*0340*/ STG.E.64 [R4.64+0x30], R10 ; /* 0x0000300a04007986 */
/* 0x008fe2000c101b0c */
/*0350*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0360*/ STG.E.64 [R6.64+0x30], R10 ; /* 0x0000300a06007986 */
/* 0x000fe6000c101b0c */
/*0370*/ I2F.F64 R16, R16 ; /* 0x0000001000107312 */
/* 0x000ee20000201c00 */
/*0380*/ STG.E.64 [R4.64+0x38], R18 ; /* 0x0000381204007986 */
/* 0x010fe8000c101b0c */
/*0390*/ STG.E.64 [R6.64+0x38], R18 ; /* 0x0000381206007986 */
/* 0x000fe6000c101b0c */
/*03a0*/ I2F.F64 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x000f220000201c00 */
/*03b0*/ STG.E.64 [R4.64+0x40], R8 ; /* 0x0000400804007986 */
/* 0x001fe8000c101b0c */
/*03c0*/ STG.E.64 [R6.64+0x40], R8 ; /* 0x0000400806007986 */
/* 0x000fe6000c101b0c */
/*03d0*/ I2F.F64 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000e220000201c00 */
/*03e0*/ STG.E.64 [R4.64+0x48], R16 ; /* 0x0000481004007986 */
/* 0x008fe8000c101b0c */
/*03f0*/ STG.E.64 [R6.64+0x48], R16 ; /* 0x0000481006007986 */
/* 0x000fe6000c101b0c */
/*0400*/ I2F.F64 R26, R26 ; /* 0x0000001a001a7312 */
/* 0x000ee20000201c00 */
/*0410*/ STG.E.64 [R4.64+0x50], R14 ; /* 0x0000500e04007986 */
/* 0x010fe8000c101b0c */
/*0420*/ STG.E.64 [R6.64+0x50], R14 ; /* 0x0000500e06007986 */
/* 0x000fe6000c101b0c */
/*0430*/ I2F.F64 R28, R28 ; /* 0x0000001c001c7312 */
/* 0x000f220000201c00 */
/*0440*/ STG.E.64 [R4.64+0x58], R12 ; /* 0x0000580c04007986 */
/* 0x001fe8000c101b0c */
/*0450*/ STG.E.64 [R6.64+0x58], R12 ; /* 0x0000580c06007986 */
/* 0x0001e6000c101b0c */
/*0460*/ I2F.F64 R24, R24 ; /* 0x0000001800187312 */
/* 0x000f620000201c00 */
/*0470*/ STG.E.64 [R4.64+0x60], R26 ; /* 0x0000601a04007986 */
/* 0x008fe8000c101b0c */
/*0480*/ STG.E.64 [R6.64+0x60], R26 ; /* 0x0000601a06007986 */
/* 0x000fe6000c101b0c */
/*0490*/ I2F.F64 R22, R0 ; /* 0x0000000000167312 */
/* 0x0044e20000201c00 */
/*04a0*/ STG.E.64 [R4.64+0x68], R28 ; /* 0x0000681c04007986 */
/* 0x010fe2000c101b0c */
/*04b0*/ IADD3 R12, P1, R4, 0x80, RZ ; /* 0x00000080040c7810 */
/* 0x001fc60007f3e0ff */
/*04c0*/ STG.E.64 [R6.64+0x68], R28 ; /* 0x0000681c06007986 */
/* 0x000fe2000c101b0c */
/*04d0*/ IADD3 R13, P2, R6, 0x80, RZ ; /* 0x00000080060d7810 */
/* 0x000fe40007f5e0ff */
/*04e0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x004fe20007ffe0ff */
/*04f0*/ STG.E.64 [R4.64+0x70], R24 ; /* 0x0000701804007986 */
/* 0x020fe6000c101b0c */
/*0500*/ ISETP.NE.AND P0, PT, R0, 0x10000f, PT ; /* 0x0010000f0000780c */
/* 0x000fe20003f05270 */
/*0510*/ STG.E.64 [R6.64+0x70], R24 ; /* 0x0000701806007986 */
/* 0x000fe8000c101b0c */
/*0520*/ STG.E.64 [R4.64+0x78], R22 ; /* 0x0000781604007986 */
/* 0x0081e8000c101b0c */
/*0530*/ STG.E.64 [R6.64+0x78], R22 ; /* 0x0000781606007986 */
/* 0x0005e2000c101b0c */
/*0540*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x001fc400008e0605 */
/*0550*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x004fe200010e0607 */
/*0560*/ @P0 BRA 0x100 ; /* 0xfffffb9000000947 */
/* 0x002fea000383ffff */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gInitVectorsPdS_
.globl _Z12gInitVectorsPdS_
.p2align 8
.type _Z12gInitVectorsPdS_,@function
_Z12gInitVectorsPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_clause 0x1
global_store_b64 v2, v[0:1], s[6:7]
global_store_b64 v2, v[0:1], s[8:9]
v_add_f64 v[0:1], v[0:1], 1.0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 0x800000
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gInitVectorsPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gInitVectorsPdS_, .Lfunc_end0-_Z12gInitVectorsPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15gVectorAdditionPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.p2align 8
.type _Z15gVectorAdditionPdS_S_i,@function
_Z15gVectorAdditionPdS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gVectorAdditionPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15gVectorAdditionPdS_S_i, .Lfunc_end1-_Z15gVectorAdditionPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gInitVectorsPdS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12gInitVectorsPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gVectorAdditionPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gVectorAdditionPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001330fa_00000000-6_lab2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12gInitVectorsPdS_PdS_
.type _Z34__device_stub__Z12gInitVectorsPdS_PdS_, @function
_Z34__device_stub__Z12gInitVectorsPdS_PdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12gInitVectorsPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z12gInitVectorsPdS_PdS_, .-_Z34__device_stub__Z12gInitVectorsPdS_PdS_
.globl _Z12gInitVectorsPdS_
.type _Z12gInitVectorsPdS_, @function
_Z12gInitVectorsPdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12gInitVectorsPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12gInitVectorsPdS_, .-_Z12gInitVectorsPdS_
.globl _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
.type _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i, @function
_Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gVectorAdditionPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i, .-_Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.type _Z15gVectorAdditionPdS_S_i, @function
_Z15gVectorAdditionPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15gVectorAdditionPdS_S_i, .-_Z15gVectorAdditionPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gedenteen/CUDA/main/lab2/lab2.cu"
.align 8
.LC1:
.string "Error \"%s\" at line %d in file %s\n"
.align 8
.LC3:
.string "blocks = %d, threads per block = %d milliseconds = %e \n"
.text
.globl _Z22testingThreadsOfDeviceii
.type _Z22testingThreadsOfDeviceii, @function
_Z22testingThreadsOfDeviceii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
movl $32, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
cmpl $1, %ebp
je .L38
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
.L26:
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1048576, %eax
movl $0, %edx
idivl %ebx
movl %eax, %r12d
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L27:
call cudaDeviceSynchronize@PLT
cmpl $1, %ebp
je .L40
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
leaq 52(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
.L29:
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movss 52(%rsp), %xmm0
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $34, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $36, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $37, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12gInitVectorsPdS_PdS_
jmp .L23
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $39, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
jmp .L26
.L39:
movl %ebx, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z15gVectorAdditionPdS_S_iPdS_S_i
jmp .L27
.L40:
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 52(%rsp)
jmp .L29
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $65, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $69, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z22testingThreadsOfDeviceii, .-_Z22testingThreadsOfDeviceii
.section .rodata.str1.8
.align 8
.LC5:
.string "\n time in milliseconds by clock_gettime:\n"
.align 8
.LC6:
.string "\t avg_time = %e min_time = %e max_time = %e\n\n"
.align 8
.LC7:
.string "\n time in milliseconds by Events:\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $1, %r13d
leaq .LC7(%rip), %r15
leaq .LC6(%rip), %r14
.L51:
movl %r13d, %esi
movl $32, %edi
call _Z22testingThreadsOfDeviceii
movss %xmm0, 4(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movl $5, %ebp
movl $64, %ebx
movl .LC4(%rip), %r12d
.L47:
movl %r13d, %esi
movl %ebx, %edi
call _Z22testingThreadsOfDeviceii
movaps %xmm0, %xmm3
maxss 8(%rsp), %xmm3
movss %xmm3, 8(%rsp)
movaps %xmm0, %xmm4
minss 4(%rsp), %xmm4
movss %xmm4, 4(%rsp)
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movd %r12d, %xmm5
addss .LC4(%rip), %xmm5
movd %xmm5, %r12d
addl %ebx, %ebx
subl $1, %ebp
jne .L47
movaps %xmm0, %xmm6
divss %xmm5, %xmm6
movss %xmm6, 12(%rsp)
cmpl $1, %r13d
je .L56
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl $3, %r13d
jne .L51
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %r13d
jmp .L51
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z15gVectorAdditionPdS_S_i"
.LC9:
.string "_Z12gInitVectorsPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gVectorAdditionPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gInitVectorsPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab2.hip"
.globl _Z27__device_stub__gInitVectorsPdS_ # -- Begin function _Z27__device_stub__gInitVectorsPdS_
.p2align 4, 0x90
.type _Z27__device_stub__gInitVectorsPdS_,@function
_Z27__device_stub__gInitVectorsPdS_: # @_Z27__device_stub__gInitVectorsPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12gInitVectorsPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__gInitVectorsPdS_, .Lfunc_end0-_Z27__device_stub__gInitVectorsPdS_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gVectorAdditionPdS_S_i # -- Begin function _Z30__device_stub__gVectorAdditionPdS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__gVectorAdditionPdS_S_i,@function
_Z30__device_stub__gVectorAdditionPdS_S_i: # @_Z30__device_stub__gVectorAdditionPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gVectorAdditionPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__gVectorAdditionPdS_S_i, .Lfunc_end1-_Z30__device_stub__gVectorAdditionPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22testingThreadsOfDeviceii
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z22testingThreadsOfDeviceii
.p2align 4, 0x90
.type _Z22testingThreadsOfDeviceii,@function
_Z22testingThreadsOfDeviceii: # @_Z22testingThreadsOfDeviceii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
leaq 120(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rdi
leaq 32(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12gInitVectorsPdS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11:
cmpl $1, %ebp
jne .LBB2_13
# %bb.12:
leaq 104(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
jmp .LBB2_14
.LBB2_13:
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
.LBB2_14:
movl $1048576, %eax # imm = 0x100000
xorl %edx, %edx
idivl %ebx
movl %eax, %r14d
movq %r14, %rdi
orq %r15, %rdi
movl %ebx, %edx
orq %r15, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 120(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ebx, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 176(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15gVectorAdditionPdS_S_i, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
callq hipDeviceSynchronize
cmpl $1, %ebp
jne .LBB2_19
# %bb.17:
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 128(%rsp), %rax
subq 104(%rsp), %rax
cvtsi2ss %rax, %xmm0
movq 136(%rsp), %rax
subq 112(%rsp), %rax
cvtsi2ss %rax, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 8(%rsp)
jmp .LBB2_18
.LBB2_19:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
.LBB2_18:
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %r14d, %esi
movl %ebx, %edx
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $36, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $39, %ecx
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $41, %ecx
jmp .LBB2_2
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $67, %ecx
jmp .LBB2_2
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %ecx
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z22testingThreadsOfDeviceii, .Lfunc_end2-_Z22testingThreadsOfDeviceii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
movl $.Lstr.1, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl $32, %edi
movl %ebx, %esi
callq _Z22testingThreadsOfDeviceii
movaps %xmm0, %xmm1
movl $64, %r14d
movss .LCPI3_0(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm3, 4(%rsp) # 4-byte Spill
movss %xmm1, 8(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
movss %xmm2, 12(%rsp) # 4-byte Spill
movl %r14d, %edi
movl %ebx, %esi
callq _Z22testingThreadsOfDeviceii
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
maxss 12(%rsp), %xmm2 # 4-byte Folded Reload
addss %xmm0, %xmm1
minss (%rsp), %xmm0 # 4-byte Folded Reload
addss .LCPI3_0(%rip), %xmm3
leal (%r14,%r14), %eax
cmpl $513, %r14d # imm = 0x201
movl %eax, %r14d
jb .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
divss %xmm3, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
cmpl $1, %ebx
movl $.Lstr, %edi
cmoveq %r15, %rdi
movss %xmm2, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 4(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
incl %ebx
cmpl $3, %ebx
jne .LBB3_1
# %bb.4:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gInitVectorsPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gVectorAdditionPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gInitVectorsPdS_,@object # @_Z12gInitVectorsPdS_
.section .rodata,"a",@progbits
.globl _Z12gInitVectorsPdS_
.p2align 3, 0x0
_Z12gInitVectorsPdS_:
.quad _Z27__device_stub__gInitVectorsPdS_
.size _Z12gInitVectorsPdS_, 8
.type _Z15gVectorAdditionPdS_S_i,@object # @_Z15gVectorAdditionPdS_S_i
.globl _Z15gVectorAdditionPdS_S_i
.p2align 3, 0x0
_Z15gVectorAdditionPdS_S_i:
.quad _Z30__device_stub__gVectorAdditionPdS_S_i
.size _Z15gVectorAdditionPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error \"%s\" at line %d in file %s\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gedenteen/CUDA/main/lab2/lab2.hip"
.size .L.str.1, 91
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "blocks = %d, threads per block = %d milliseconds = %e \n"
.size .L.str.2, 56
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\t avg_time = %e min_time = %e max_time = %e\n\n"
.size .L.str.5, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12gInitVectorsPdS_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15gVectorAdditionPdS_S_i"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n time in milliseconds by Events:"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n time in milliseconds by clock_gettime:"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gInitVectorsPdS_
.addrsig_sym _Z30__device_stub__gVectorAdditionPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gInitVectorsPdS_
.addrsig_sym _Z15gVectorAdditionPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
cudaMalloc(&dev_array, sizeof(int)*16);
cudaMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
cudaMemcpy(host_array, dev_array, sizeof(int)*16, cudaMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
cudaFree(dev_array);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z7kernel3Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
cudaMalloc(&dev_array, sizeof(int)*16);
cudaMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
cudaMemcpy(host_array, dev_array, sizeof(int)*16, cudaMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
cudaFree(dev_array);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000b7ce0_00000000-6_2index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7kernel1PiPi
.type _Z26__device_stub__Z7kernel1PiPi, @function
_Z26__device_stub__Z7kernel1PiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7kernel1PiPi, .-_Z26__device_stub__Z7kernel1PiPi
.globl _Z7kernel1Pi
.type _Z7kernel1Pi, @function
_Z7kernel1Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7kernel1Pi, .-_Z7kernel1Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $16, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 64(%r13), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel1PiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z7kernel2PiPi
.type _Z26__device_stub__Z7kernel2PiPi, @function
_Z26__device_stub__Z7kernel2PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7kernel2PiPi, .-_Z26__device_stub__Z7kernel2PiPi
.globl _Z7kernel2Pi
.type _Z7kernel2Pi, @function
_Z7kernel2Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7kernel2Pi, .-_Z7kernel2Pi
.globl _Z26__device_stub__Z7kernel3PiPi
.type _Z26__device_stub__Z7kernel3PiPi, @function
_Z26__device_stub__Z7kernel3PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel3Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z7kernel3PiPi, .-_Z26__device_stub__Z7kernel3PiPi
.globl _Z7kernel3Pi
.type _Z7kernel3Pi, @function
_Z7kernel3Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel3PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7kernel3Pi, .-_Z7kernel3Pi
.section .rodata.str1.1
.LC2:
.string "_Z7kernel3Pi"
.LC3:
.string "_Z7kernel2Pi"
.LC4:
.string "_Z7kernel1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel3Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
cudaMalloc(&dev_array, sizeof(int)*16);
cudaMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
cudaMemcpy(host_array, dev_array, sizeof(int)*16, cudaMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
cudaFree(dev_array);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
hipMalloc(&dev_array, sizeof(int)*16);
hipMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
hipMemcpy(host_array, dev_array, sizeof(int)*16, hipMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
hipFree(dev_array);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
hipMalloc(&dev_array, sizeof(int)*16);
hipMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
hipMemcpy(host_array, dev_array, sizeof(int)*16, hipMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
hipFree(dev_array);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1Pi
.globl _Z7kernel1Pi
.p2align 8
.type _Z7kernel1Pi,@function
_Z7kernel1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 7
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1Pi, .Lfunc_end0-_Z7kernel1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 8
.type _Z7kernel2Pi,@function
_Z7kernel2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s15
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2Pi, .Lfunc_end1-_Z7kernel2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel3Pi
.globl _Z7kernel3Pi
.p2align 8
.type _Z7kernel3Pi,@function
_Z7kernel3Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel3Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7kernel3Pi, .Lfunc_end2-_Z7kernel3Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel3Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel3Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel1( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = 7; // output: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
}
__global__ void kernel2( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = blockIdx.x; // output: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3
}
__global__ void kernel3( int *a )
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = threadIdx.x; // output: 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3
}
int main()
{
int *host_array;
int *dev_array;
host_array = (int *) malloc(sizeof(int)*16);
hipMalloc(&dev_array, sizeof(int)*16);
hipMemset(dev_array, 0, 16);
kernel1<<<4, 4>>>(dev_array);
hipMemcpy(host_array, dev_array, sizeof(int)*16, hipMemcpyDeviceToHost);
for(int i = 0; i < 16; i++) printf(" %d ", host_array[i]);
printf("\n");
free(host_array);
hipFree(dev_array);
hipDeviceReset();
return 0;
} | .text
.file "2index.hip"
.globl _Z22__device_stub__kernel1Pi # -- Begin function _Z22__device_stub__kernel1Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pi,@function
_Z22__device_stub__kernel1Pi: # @_Z22__device_stub__kernel1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1Pi, .Lfunc_end0-_Z22__device_stub__kernel1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2Pi # -- Begin function _Z22__device_stub__kernel2Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2Pi,@function
_Z22__device_stub__kernel2Pi: # @_Z22__device_stub__kernel2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2Pi, .Lfunc_end1-_Z22__device_stub__kernel2Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel3Pi # -- Begin function _Z22__device_stub__kernel3Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel3Pi,@function
_Z22__device_stub__kernel3Pi: # @_Z22__device_stub__kernel3Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel3Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel3Pi, .Lfunc_end2-_Z22__device_stub__kernel3Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $16, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel1Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel3Pi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1Pi,@object # @_Z7kernel1Pi
.section .rodata,"a",@progbits
.globl _Z7kernel1Pi
.p2align 3, 0x0
_Z7kernel1Pi:
.quad _Z22__device_stub__kernel1Pi
.size _Z7kernel1Pi, 8
.type _Z7kernel2Pi,@object # @_Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 3, 0x0
_Z7kernel2Pi:
.quad _Z22__device_stub__kernel2Pi
.size _Z7kernel2Pi, 8
.type _Z7kernel3Pi,@object # @_Z7kernel3Pi
.globl _Z7kernel3Pi
.p2align 3, 0x0
_Z7kernel3Pi:
.quad _Z22__device_stub__kernel3Pi
.size _Z7kernel3Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1Pi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2Pi"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7kernel3Pi"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1Pi
.addrsig_sym _Z22__device_stub__kernel2Pi
.addrsig_sym _Z22__device_stub__kernel3Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1Pi
.addrsig_sym _Z7kernel2Pi
.addrsig_sym _Z7kernel3Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel3Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x7 ; /* 0x0000000700077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1Pi
.globl _Z7kernel1Pi
.p2align 8
.type _Z7kernel1Pi,@function
_Z7kernel1Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 7
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1Pi, .Lfunc_end0-_Z7kernel1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 8
.type _Z7kernel2Pi,@function
_Z7kernel2Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s15
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2Pi, .Lfunc_end1-_Z7kernel2Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel3Pi
.globl _Z7kernel3Pi
.p2align 8
.type _Z7kernel3Pi,@function
_Z7kernel3Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel3Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7kernel3Pi, .Lfunc_end2-_Z7kernel3Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel3Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel3Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7ce0_00000000-6_2index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7kernel1PiPi
.type _Z26__device_stub__Z7kernel1PiPi, @function
_Z26__device_stub__Z7kernel1PiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7kernel1PiPi, .-_Z26__device_stub__Z7kernel1PiPi
.globl _Z7kernel1Pi
.type _Z7kernel1Pi, @function
_Z7kernel1Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7kernel1Pi, .-_Z7kernel1Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $16, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 64(%r13), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7kernel1PiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z7kernel2PiPi
.type _Z26__device_stub__Z7kernel2PiPi, @function
_Z26__device_stub__Z7kernel2PiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7kernel2PiPi, .-_Z26__device_stub__Z7kernel2PiPi
.globl _Z7kernel2Pi
.type _Z7kernel2Pi, @function
_Z7kernel2Pi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7kernel2Pi, .-_Z7kernel2Pi
.globl _Z26__device_stub__Z7kernel3PiPi
.type _Z26__device_stub__Z7kernel3PiPi, @function
_Z26__device_stub__Z7kernel3PiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel3Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z7kernel3PiPi, .-_Z26__device_stub__Z7kernel3PiPi
.globl _Z7kernel3Pi
.type _Z7kernel3Pi, @function
_Z7kernel3Pi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel3PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7kernel3Pi, .-_Z7kernel3Pi
.section .rodata.str1.1
.LC2:
.string "_Z7kernel3Pi"
.LC3:
.string "_Z7kernel2Pi"
.LC4:
.string "_Z7kernel1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel3Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2index.hip"
.globl _Z22__device_stub__kernel1Pi # -- Begin function _Z22__device_stub__kernel1Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel1Pi,@function
_Z22__device_stub__kernel1Pi: # @_Z22__device_stub__kernel1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1Pi, .Lfunc_end0-_Z22__device_stub__kernel1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2Pi # -- Begin function _Z22__device_stub__kernel2Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2Pi,@function
_Z22__device_stub__kernel2Pi: # @_Z22__device_stub__kernel2Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel2Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2Pi, .Lfunc_end1-_Z22__device_stub__kernel2Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel3Pi # -- Begin function _Z22__device_stub__kernel3Pi
.p2align 4, 0x90
.type _Z22__device_stub__kernel3Pi,@function
_Z22__device_stub__kernel3Pi: # @_Z22__device_stub__kernel3Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7kernel3Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel3Pi, .Lfunc_end2-_Z22__device_stub__kernel3Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $16, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7kernel1Pi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2Pi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel3Pi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1Pi,@object # @_Z7kernel1Pi
.section .rodata,"a",@progbits
.globl _Z7kernel1Pi
.p2align 3, 0x0
_Z7kernel1Pi:
.quad _Z22__device_stub__kernel1Pi
.size _Z7kernel1Pi, 8
.type _Z7kernel2Pi,@object # @_Z7kernel2Pi
.globl _Z7kernel2Pi
.p2align 3, 0x0
_Z7kernel2Pi:
.quad _Z22__device_stub__kernel2Pi
.size _Z7kernel2Pi, 8
.type _Z7kernel3Pi,@object # @_Z7kernel3Pi
.globl _Z7kernel3Pi
.p2align 3, 0x0
_Z7kernel3Pi:
.quad _Z22__device_stub__kernel3Pi
.size _Z7kernel3Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1Pi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2Pi"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7kernel3Pi"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1Pi
.addrsig_sym _Z22__device_stub__kernel2Pi
.addrsig_sym _Z22__device_stub__kernel3Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1Pi
.addrsig_sym _Z7kernel2Pi
.addrsig_sym _Z7kernel3Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
cudaMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
cudaMemcpy(dev_arr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
cudaMemcpy(arr, dev_arr, N * sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_arr );
return 0;
} | code for sm_80
Function : _Z9fillArrayPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.NE.AND P0, PT, R5.reuse, 0x5, PT ; /* 0x000000050500780c */
/* 0x041fe40003f05270 */
/*0050*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101924 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x001fe200078e00ff */
/*00c0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x69 ; /* 0x00000069ff057424 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0180*/ STG.E [R2.64+0x14], R5 ; /* 0x0000140502007986 */
/* 0x000fe2000c101924 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
cudaMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
cudaMemcpy(dev_arr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
cudaMemcpy(arr, dev_arr, N * sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_arr );
return 0;
} | .file "tmpxft_000aa2ee_00000000-6_ArrayBlock.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9fillArrayPiPi
.type _Z28__device_stub__Z9fillArrayPiPi, @function
_Z28__device_stub__Z9fillArrayPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z9fillArrayPiPi, .-_Z28__device_stub__Z9fillArrayPiPi
.globl _Z9fillArrayPi
.type _Z9fillArrayPi, @function
_Z9fillArrayPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9fillArrayPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9fillArrayPi, .-_Z9fillArrayPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "------------ initialising device and host arrays"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "host arr[%d] = %d\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "------------ allocate device memory dev_arr"
.align 8
.LC3:
.string "------------ copy arr to dev_arr"
.align 8
.LC4:
.string "------------ calling kernel fillArray"
.align 8
.LC5:
.string "------------ copy dev_arr to arr"
.align 8
.LC6:
.string "------------ printing changed host array"
.section .rodata.str1.1
.LC7:
.string "** changed host arr[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L12:
movl $0, 32(%rsp,%rbx,4)
movl $0, %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L12
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC7(%rip), %rbp
.L14:
movl 32(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z28__device_stub__Z9fillArrayPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9fillArrayPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
cudaMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
cudaMemcpy(dev_arr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
cudaMemcpy(arr, dev_arr, N * sizeof(int), cudaMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
cudaFree( dev_arr );
return 0;
} | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
hipMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
hipMemcpy(dev_arr, arr, N * sizeof(int), hipMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
hipMemcpy(arr, dev_arr, N * sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_arr );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
hipMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
hipMemcpy(dev_arr, arr, N * sizeof(int), hipMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
hipMemcpy(arr, dev_arr, N * sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_arr );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9fillArrayPi
.globl _Z9fillArrayPi
.p2align 8
.type _Z9fillArrayPi,@function
_Z9fillArrayPi:
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s15
s_lshl_b64 s[6:7], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_cmp_lg_u32 s15, 5
global_store_b32 v0, v1, s[2:3]
s_cbranch_scc1 .LBB0_135
s_load_b64 s[4:5], s[0:1], 0x58
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[5:6], v0, s[4:5]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_6
s_mov_b32 s7, 0
.p2align 6
.LBB0_4:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[10:11], v0, s[4:5]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s7
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[4:5] offset:40
global_load_b128 v[0:3], v5, s[4:5]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[8:9], s[6:7], s[8:9]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, 0
s_mul_i32 s10, s9, 24
s_mul_hi_u32 s11, s8, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s11, s11, s10
s_mul_i32 s10, s8, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[10:11], s[8:9], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s12
v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
v_mov_b32_e32 v11, s15
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s6
v_mov_b32_e32 v12, s7
s_clause 0x1
global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
global_load_b64 v[2:3], v10, s[4:5] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v2
v_readfirstlane_b32 s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[6:7]
s_mul_i32 s11, s11, 24
s_mul_hi_u32 s12, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s12, s12, s11
v_add_co_u32 v8, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v9, vcc_lo, s12, v1, vcc_lo
s_mov_b32 s10, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_13
s_mov_b32 s11, 0
.LBB0_12:
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_12
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v2, 0
s_mov_b32 s11, exec_lo
s_mov_b32 s10, exec_lo
v_mbcnt_lo_u32_b32 v4, s11, 0
global_load_b64 v[2:3], v2, s[4:5] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_15
s_bcnt1_i32_b32 s11, s11
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s11
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_17
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s10, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s9, 24
s_mul_hi_u32 s9, s8, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s1
s_mul_i32 s1, s8, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_21
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_20
s_sleep 1
s_cbranch_execnz .LBB0_21
s_branch .LBB0_23
.p2align 6
.LBB0_20:
s_branch .LBB0_23
.LBB0_21:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_18
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_18
.LBB0_23:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[4:5] offset:40
global_load_b64 v[7:8], v6, s[4:5] offset:24 glc
global_load_b64 v[4:5], v6, s[4:5]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s6
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
s_mov_b32 s0, 0
.LBB0_26:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, .str@rel32@lo+4
s_addc_u32 s7, s7, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_106
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[8:9], 28
s_branch .LBB0_30
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s8, s8, s10
s_subb_u32 s9, s9, s11
s_add_u32 s6, s6, s10
s_addc_u32 s7, s7, s11
s_cmp_lg_u64 s[8:9], 0
s_cbranch_scc0 .LBB0_105
.LBB0_30:
v_cmp_lt_u64_e64 s0, s[8:9], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s10, s8, 56
s_cselect_b32 s11, s9, 0
s_cmp_gt_u32 s10, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_35
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_34
s_lshl_b64 s[0:1], s[10:11], 3
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], s[6:7]
.LBB0_33:
global_load_u8 v4, v25, s[14:15]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s14, s14, 1
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s0, s12
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_33
.LBB0_34:
s_mov_b32 s0, 0
s_mov_b32 s17, 0
.LBB0_35:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[6:7]
s_cbranch_vccnz .LBB0_37
global_load_b64 v[2:3], v25, s[6:7]
s_add_i32 s17, s10, -8
s_add_u32 s0, s6, 8
s_addc_u32 s1, s7, 0
.LBB0_37:
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_42
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_41
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], 0
.LBB0_40:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s14
s_addc_u32 s19, s1, s15
s_add_u32 s14, s14, 1
global_load_u8 v6, v25, s[18:19]
s_addc_u32 s15, s15, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s17, s14
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_40
.LBB0_41:
s_mov_b32 s16, 0
s_cbranch_execz .LBB0_43
s_branch .LBB0_44
.LBB0_42:
.LBB0_43:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44:
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_49
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_48
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], 0
.LBB0_47:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s14
s_addc_u32 s19, s1, s15
s_add_u32 s14, s14, 1
global_load_u8 v8, v25, s[18:19]
s_addc_u32 s15, s15, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s16, s14
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_47
.LBB0_48:
s_mov_b32 s17, 0
s_cbranch_execz .LBB0_50
s_branch .LBB0_51
.LBB0_49:
.LBB0_50:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s17, s16, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_51:
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_56
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_55
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], 0
.LBB0_54:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s14
s_addc_u32 s19, s1, s15
s_add_u32 s14, s14, 1
global_load_u8 v10, v25, s[18:19]
s_addc_u32 s15, s15, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s17, s14
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_54
.LBB0_55:
s_mov_b32 s16, 0
s_cbranch_execz .LBB0_57
s_branch .LBB0_58
.LBB0_56:
.LBB0_57:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_58:
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_63
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_62
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], 0
.LBB0_61:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s14
s_addc_u32 s19, s1, s15
s_add_u32 s14, s14, 1
global_load_u8 v12, v25, s[18:19]
s_addc_u32 s15, s15, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s16, s14
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_61
.LBB0_62:
s_mov_b32 s17, 0
s_cbranch_execz .LBB0_64
s_branch .LBB0_65
.LBB0_63:
.LBB0_64:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s17, s16, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_65:
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_70
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_69
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], 0
.LBB0_68:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s14
s_addc_u32 s19, s1, s15
s_add_u32 s14, s14, 1
global_load_u8 v14, v25, s[18:19]
s_addc_u32 s15, s15, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s17, s14
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_68
.LBB0_69:
s_mov_b32 s16, 0
s_cbranch_execz .LBB0_71
s_branch .LBB0_72
.LBB0_70:
.LBB0_71:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_72:
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_77
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_76
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], s[0:1]
.LBB0_75:
global_load_u8 v16, v25, s[14:15]
s_add_i32 s16, s16, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s12, v[24:25]
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s14, s14, 1
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s16, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_75
.LBB0_76:
s_cbranch_execz .LBB0_78
s_branch .LBB0_79
.LBB0_77:
.LBB0_78:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_79:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_85
global_load_b64 v[18:19], v25, s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[4:5] offset:40
global_load_b64 v[26:27], v25, s[4:5]
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_84
s_mov_b32 s13, 0
.p2align 6
.LBB0_82:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[4:5] offset:40
global_load_b64 v[28:29], v25, s[4:5]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_82
s_or_b32 exec_lo, exec_lo, s13
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s12
.LBB0_85:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[4:5] offset:40
global_load_b128 v[16:19], v25, s[4:5]
v_readfirstlane_b32 s12, v26
v_readfirstlane_b32 s13, v27
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s14, v28
v_readfirstlane_b32 s15, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[14:15], s[12:13], s[14:15]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_87
v_dual_mov_b32 v26, s16 :: v_dual_mov_b32 v27, 0
s_mul_i32 s16, s15, 24
s_mul_hi_u32 s17, s14, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s17, s17, s16
s_mul_i32 s16, s14, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s16
v_add_co_ci_u32_e32 v31, vcc_lo, s17, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_87:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[16:17], s[14:15], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s10, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s16
v_add_co_ci_u32_e32 v19, vcc_lo, s17, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
s_clause 0x1
global_load_b64 v[8:9], v25, s[4:5] offset:32 glc
global_load_b64 v[0:1], v25, s[4:5] offset:40
v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s16, v0
v_readfirstlane_b32 s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[16:17], s[16:17], s[12:13]
s_mul_i32 s17, s17, 24
s_mul_hi_u32 s18, s16, 24
s_mul_i32 s16, s16, 24
s_add_i32 s18, s18, s17
v_add_co_u32 v4, vcc_lo, v16, s16
v_add_co_ci_u32_e32 v5, vcc_lo, s18, v17, vcc_lo
s_mov_b32 s16, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_91
s_mov_b32 s17, 0
.LBB0_90:
v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_90
.LBB0_91:
s_or_b32 exec_lo, exec_lo, s16
global_load_b64 v[0:1], v25, s[4:5] offset:16
s_mov_b32 s17, exec_lo
s_mov_b32 s16, exec_lo
v_mbcnt_lo_u32_b32 v2, s17, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_93
s_bcnt1_i32_b32 s17, s17
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s17
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_93:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_95
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s16, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s16, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s15, 24
s_mul_hi_u32 s15, s14, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s15, s15, s1
s_mul_i32 s1, s14, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_99
.p2align 6
.LBB0_96:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_98
s_sleep 1
s_cbranch_execnz .LBB0_99
s_branch .LBB0_101
.p2align 6
.LBB0_98:
s_branch .LBB0_101
.LBB0_99:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_96
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_96
.LBB0_101:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_29
s_clause 0x2
global_load_b64 v[4:5], v25, s[4:5] offset:40
global_load_b64 v[8:9], v25, s[4:5] offset:24 glc
global_load_b64 v[6:7], v25, s[4:5]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s12
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_29
s_mov_b32 s0, 0
.LBB0_104:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_104
s_branch .LBB0_29
.LBB0_105:
s_mov_b32 s0, 0
.LBB0_106:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_134
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_113
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s6, exec_lo
global_load_b64 v[6:7], v0, s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[3:4], v0, s[4:5]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_112
s_mov_b32 s7, 0
.p2align 6
.LBB0_110:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[8:9], v0, s[4:5]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_110
s_or_b32 exec_lo, exec_lo, s7
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
.LBB0_113:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s6, v4
v_readfirstlane_b32 s7, v5
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[4:5] offset:40
global_load_b128 v[0:3], v21, s[4:5]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s8, v6
v_readfirstlane_b32 s9, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[8:9], s[6:7], s[8:9]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_115
v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v5, 0
s_mul_i32 s10, s9, 24
s_mul_hi_u32 s11, s8, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s11, s11, s10
s_mul_i32 s10, s8, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_115:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[10:11], s[8:9], 12
s_mov_b32 s12, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_mov_b32_e32 v6, 0
v_and_or_b32 v22, v22, 0xffffff1d, 34
v_add_co_u32 v8, vcc_lo, v4, v2
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v5, s15
v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s14
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s6
v_mov_b32_e32 v10, s7
s_clause 0x1
global_load_b64 v[11:12], v8, s[4:5] offset:32 glc
global_load_b64 v[2:3], v8, s[4:5] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v2
v_readfirstlane_b32 s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[6:7]
s_mul_i32 s11, s11, 24
s_mul_hi_u32 s12, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s12, s12, s11
v_add_co_u32 v6, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s12, v1, vcc_lo
s_mov_b32 s10, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_119
s_mov_b32 s11, 0
.LBB0_118:
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_118
.LBB0_119:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v2, 0
s_mov_b32 s11, exec_lo
s_mov_b32 s10, exec_lo
v_mbcnt_lo_u32_b32 v4, s11, 0
global_load_b64 v[2:3], v2, s[4:5] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_121
s_bcnt1_i32_b32 s11, s11
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s11
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_121:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_123
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s10, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s9, 24
s_mul_hi_u32 s9, s8, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s1
s_mul_i32 s1, s8, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_127
.p2align 6
.LBB0_124:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_126
s_sleep 1
s_cbranch_execnz .LBB0_127
s_branch .LBB0_129
.p2align 6
.LBB0_126:
s_branch .LBB0_129
.LBB0_127:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_124
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_124
.LBB0_129:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_133
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[4:5] offset:40
global_load_b64 v[7:8], v6, s[4:5] offset:24 glc
global_load_b64 v[4:5], v6, s[4:5]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s6
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_133
s_mov_b32 s0, 0
.LBB0_132:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_132
.LBB0_133:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_134:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x69
global_store_b32 v0, v1, s[2:3]
.LBB0_135:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9fillArrayPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9fillArrayPi, .Lfunc_end0-_Z9fillArrayPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "**blockIdx.x 5 is called!!\n"
.size .str, 28
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 88
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9fillArrayPi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z9fillArrayPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ##########################################################
// By Eugene Ch'ng | www.complexity.io
// Email: [email protected]
// ----------------------------------------------------------
// The ERC 'Lost Frontiers' Project
// Development for the Parallelisation of ABM Simulation
// ----------------------------------------------------------
// A Basic CUDA Application for ABM Development
//
// Filling arrays with block generated IDs
// identify a specific block ID and make changes for that kernel
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
//
// LIMITS OF THREADS AND BLOCKS (use 01.DeviceInfo to check your GPU)
// The particular GPU used here has 1024 threads per block
// This presents a limit, but we can also use blocks per grid
// Each block (for this old AlienWare GPU) has 65535 blocks per grid
// Blocks and Threads have 3 dimensions (type dim3)
// We will explore how to combine both blocks and threads to create
// arbitrarily long numbers
// ----------------------------------------------------------
// How to compile:
// nvcc <filename>.cu -o <outputfile>
// ##########################################################
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
// blockIdx is limited at 65535
#define N 10
// --------------------- CUDA KERNELS
// Fill arrays with device thread IDs
__global__ void fillArray(int *dev_arr)
{
// note that we no longer use the for loop here
// blockIdx.x is a device variable - it's the ID of the block
// fillArray kernel is called for each block and has its own ID
int bid = blockIdx.x;
// assign the dev_array element with threadIDx.x
dev_arr[bid] = bid;
// identifying a threads
if(bid == 5)
{
printf("**blockIdx.x 5 is called!!\n");
dev_arr[bid] = bid + 100;
}
}
// the main is a host code
int main(int argc, const char * argv[])
{
cout << "------------ initialising device and host arrays" << endl;
int arr[N]; // host variable
int *dev_arr; // device variable
for(int i=0; i<N; i++)
{
arr[i] = 0;
printf("host arr[%d] = %d\n", i, arr[i]);
}
cout << "------------ allocate device memory dev_arr" << endl;
// allocating a device array to copy to
// note the N * sizeof(int)
hipMalloc( (void**)&dev_arr, N * sizeof(int) );
cout << "------------ copy arr to dev_arr" << endl;
// copying host array to device
// note the N * sizeof(int)
hipMemcpy(dev_arr, arr, N * sizeof(int), hipMemcpyHostToDevice);
cout << "------------ calling kernel fillArray" << endl;
// N block, and 1 thread
// previously we used fillArray<<1,N>>, 1 block and N threads
// we now use <<N,1>> for N blocks and 1 thread
fillArray<<<N,1>>>(dev_arr);
cout << "------------ copy dev_arr to arr" << endl;
// note the N * sizeof(int)
hipMemcpy(arr, dev_arr, N * sizeof(int), hipMemcpyDeviceToHost);
cout << "------------ printing changed host array" << endl;
for(int i=0; i<N; i++)
{
printf("** changed host arr[%d] = %d\n", i, arr[i]);
}
// ---- FREE ALLOCATED KERNEL MEMORY
hipFree( dev_arr );
return 0;
} | .text
.file "ArrayBlock.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__fillArrayPi # -- Begin function _Z24__device_stub__fillArrayPi
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPi,@function
_Z24__device_stub__fillArrayPi: # @_Z24__device_stub__fillArrayPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9fillArrayPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__fillArrayPi, .Lfunc_end0-_Z24__device_stub__fillArrayPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $0, 80(%rsp,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %edx, %edx
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %eax
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9fillArrayPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %eax
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
cmpb $0, 56(%rbx)
je .LBB1_27
# %bb.26:
movzbl 67(%rbx), %eax
jmp .LBB1_28
.LBB1_27:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_29: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %edx
movl $.L.str.7, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_29
# %bb.30:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPi,@object # @_Z9fillArrayPi
.section .rodata,"a",@progbits
.globl _Z9fillArrayPi
.p2align 3, 0x0
_Z9fillArrayPi:
.quad _Z24__device_stub__fillArrayPi
.size _Z9fillArrayPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "------------ initialising device and host arrays"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "host arr[%d] = %d\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "------------ allocate device memory dev_arr"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "------------ copy arr to dev_arr"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "------------ calling kernel fillArray"
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "------------ copy dev_arr to arr"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "------------ printing changed host array"
.size .L.str.6, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "** changed host arr[%d] = %d\n"
.size .L.str.7, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9fillArrayPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa2ee_00000000-6_ArrayBlock.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9fillArrayPiPi
.type _Z28__device_stub__Z9fillArrayPiPi, @function
_Z28__device_stub__Z9fillArrayPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9fillArrayPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z9fillArrayPiPi, .-_Z28__device_stub__Z9fillArrayPiPi
.globl _Z9fillArrayPi
.type _Z9fillArrayPi, @function
_Z9fillArrayPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9fillArrayPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9fillArrayPi, .-_Z9fillArrayPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "------------ initialising device and host arrays"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "host arr[%d] = %d\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "------------ allocate device memory dev_arr"
.align 8
.LC3:
.string "------------ copy arr to dev_arr"
.align 8
.LC4:
.string "------------ calling kernel fillArray"
.align 8
.LC5:
.string "------------ copy dev_arr to arr"
.align 8
.LC6:
.string "------------ printing changed host array"
.section .rodata.str1.1
.LC7:
.string "** changed host arr[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L12:
movl $0, 32(%rsp,%rbx,4)
movl $0, %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L12
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC7(%rip), %rbp
.L14:
movl 32(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z28__device_stub__Z9fillArrayPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9fillArrayPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9fillArrayPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ArrayBlock.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__fillArrayPi # -- Begin function _Z24__device_stub__fillArrayPi
.p2align 4, 0x90
.type _Z24__device_stub__fillArrayPi,@function
_Z24__device_stub__fillArrayPi: # @_Z24__device_stub__fillArrayPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9fillArrayPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__fillArrayPi, .Lfunc_end0-_Z24__device_stub__fillArrayPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $0, 80(%rsp,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %edx, %edx
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %eax
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9fillArrayPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %eax
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_31
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
cmpb $0, 56(%rbx)
je .LBB1_27
# %bb.26:
movzbl 67(%rbx), %eax
jmp .LBB1_28
.LBB1_27:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_29: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %edx
movl $.L.str.7, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_29
# %bb.30:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9fillArrayPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9fillArrayPi,@object # @_Z9fillArrayPi
.section .rodata,"a",@progbits
.globl _Z9fillArrayPi
.p2align 3, 0x0
_Z9fillArrayPi:
.quad _Z24__device_stub__fillArrayPi
.size _Z9fillArrayPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "------------ initialising device and host arrays"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "host arr[%d] = %d\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "------------ allocate device memory dev_arr"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "------------ copy arr to dev_arr"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "------------ calling kernel fillArray"
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "------------ copy dev_arr to arr"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "------------ printing changed host array"
.size .L.str.6, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "** changed host arr[%d] = %d\n"
.size .L.str.7, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9fillArrayPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__fillArrayPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9fillArrayPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} | code for sm_80
Function : _Z6squarePiPyPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff147624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff157624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0000a8000c1e1900 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0060*/ IADD3 R21, R6, 0x1, RZ ; /* 0x0000000106157810 */
/* 0x001fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R21, R20, PT ; /* 0x000000141500720c */
/* 0x004fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000164000c1e1b00 */
/*00c0*/ IADD3 R4, R21, -0x1, RZ ; /* 0xffffffff15047810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x004ea2000c1e1b00 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0110*/ I2F.F64 R14, R21 ; /* 0x00000015000e7312 */
/* 0x0022e20000201c00 */
/*0120*/ BSSY B0, 0x270 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0130*/ IADD3 R21, R21, c[0x0][0x0], RZ ; /* 0x0000000015157a10 */
/* 0x002fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P1, PT, R21, R20, PT ; /* 0x000000141500720c */
/* 0x000fe20003f26270 */
/*0150*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x008e540000000000 */
/*0160*/ FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fe20003f4e200 */
/*0170*/ I2F.F64.U64 R2, R2 ; /* 0x0000000200027312 */
/* 0x004e700000301800 */
/*0180*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x002e640000001800 */
/*0190*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x002e4c000000010a */
/*01a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x002e4c000000000c */
/*01b0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002e4c000000000a */
/*01c0*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x002e4c000000010c */
/*01d0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x002e4c000000000c */
/*01e0*/ DMUL R4, R14, R10 ; /* 0x0000000a0e047228 */
/* 0x002e4c0000000000 */
/*01f0*/ DFMA R12, -R2, R4, R14 ; /* 0x00000004020c722b */
/* 0x002e4c000000010e */
/*0200*/ DFMA R4, R10, R12, R4 ; /* 0x0000000c0a04722b */
/* 0x002e540000000004 */
/*0210*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x002fca0000000005 */
/*0220*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0230*/ @P0 BRA P2, 0x260 ; /* 0x0000002000000947 */
/* 0x000fea0001000000 */
/*0240*/ MOV R0, 0x260 ; /* 0x0000026000007802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x2b0 ; /* 0x0000005000007944 */
/* 0x021fea0003c00000 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ DADD R8, R4, R8 ; /* 0x0000000004087229 */
/* 0x020e8e0000000008 */
/*0280*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0045e2000c101b04 */
/*0290*/ @!P1 BRA 0xc0 ; /* 0xfffffe2000009947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*02d0*/ LOP3.LUT R10, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff030a7812 */
/* 0x000fe200078ec0ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*02f0*/ FSETP.GEU.AND P3, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f6e200 */
/*0300*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0330*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0350*/ LOP3.LUT R25, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003197812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*0370*/ BSSY B1, 0x860 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f46070 */
/*03a0*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*03b0*/ @!P3 LOP3.LUT R17, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d11b812 */
/* 0x000fe200078ec0ff */
/*03c0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12b224 */
/* 0x000fe200078e00ff */
/*03d0*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e220000001800 */
/*03e0*/ SEL R3, R23, 0x63400000, !P2 ; /* 0x6340000017037807 */
/* 0x000fe40005000000 */
/*03f0*/ @!P3 ISETP.GE.U32.AND P4, PT, R22, R17, PT ; /* 0x000000111600b20c */
/* 0x000fe40003f86070 */
/*0400*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80f */
/*0410*/ @!P3 SEL R19, R23, 0x63400000, !P4 ; /* 0x634000001713b807 */
/* 0x000fe40006000000 */
/*0420*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fc400078ec0ff */
/*0430*/ @!P3 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313b812 */
/* 0x000fe400078ef80f */
/*0440*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ @!P3 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313b812 */
/* 0x000fe200078efcff */
/*0460*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e0a000000080a */
/*0470*/ @!P3 DFMA R2, R2, 2, -R18 ; /* 0x400000000202b82b */
/* 0x000fc80000000812 */
/*0480*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0490*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*04a0*/ @!P3 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318b812 */
/* 0x000fc800078ec0ff */
/*04b0*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*04e0*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*04f0*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0500*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0520*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*0570*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*0580*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*0590*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*05a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*05b0*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*05c0*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*0640*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0670*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*06a0*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*07a0*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff77002007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} | .file "tmpxft_0004c0bf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6squarePiPyPdPiPyPd
.type _Z29__device_stub__Z6squarePiPyPdPiPyPd, @function
_Z29__device_stub__Z6squarePiPyPdPiPyPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6squarePiPyPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6squarePiPyPdPiPyPd, .-_Z29__device_stub__Z6squarePiPyPdPiPyPd
.globl _Z6squarePiPyPd
.type _Z6squarePiPyPd, @function
_Z6squarePiPyPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6squarePiPyPdPiPyPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6squarePiPyPd, .-_Z6squarePiPyPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePiPyPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiPyPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiPyPd
.globl _Z6squarePiPyPd
.p2align 8
.type _Z6squarePiPyPd,@function
_Z6squarePiPyPd:
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x24
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[3:4], v0, s[6:7]
v_add_co_u32 v5, s1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s7, 0, s1
s_add_u32 s0, s4, -8
s_addc_u32 s1, s5, -1
s_and_b32 s4, s3, 0xffff
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f64_i32_e32 v[10:11], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[8:9], v8
v_cvt_f64_u32_e32 v[12:13], v7
v_ldexp_f64 v[7:8], v[8:9], 32
v_mul_f64 v[9:10], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[12:13]
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s3, vcc_lo, s3
v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[7:8]
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
global_store_b64 v[5:6], v[3:4], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiPyPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiPyPd, .Lfunc_end0-_Z6squarePiPyPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiPyPd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6squarePiPyPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square( int *d_num_steps, unsigned long long *d_fact, double *d_out){
int idx = threadIdx.x;
int num_steps = *d_num_steps;
for(int k=idx+1; k< num_steps; k+=blockDim.x){
d_out[idx] += (double) k*0.5/ (double) d_fact[k-1];
}
} | .text
.file "square.hip"
.globl _Z21__device_stub__squarePiPyPd # -- Begin function _Z21__device_stub__squarePiPyPd
.p2align 4, 0x90
.type _Z21__device_stub__squarePiPyPd,@function
_Z21__device_stub__squarePiPyPd: # @_Z21__device_stub__squarePiPyPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePiPyPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiPyPd, .Lfunc_end0-_Z21__device_stub__squarePiPyPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiPyPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiPyPd,@object # @_Z6squarePiPyPd
.section .rodata,"a",@progbits
.globl _Z6squarePiPyPd
.p2align 3, 0x0
_Z6squarePiPyPd:
.quad _Z21__device_stub__squarePiPyPd
.size _Z6squarePiPyPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6squarePiPyPd"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiPyPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiPyPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePiPyPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff147624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff157624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0000a8000c1e1900 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0060*/ IADD3 R21, R6, 0x1, RZ ; /* 0x0000000106157810 */
/* 0x001fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R21, R20, PT ; /* 0x000000141500720c */
/* 0x004fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000164000c1e1b00 */
/*00c0*/ IADD3 R4, R21, -0x1, RZ ; /* 0xffffffff15047810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x004ea2000c1e1b00 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0110*/ I2F.F64 R14, R21 ; /* 0x00000015000e7312 */
/* 0x0022e20000201c00 */
/*0120*/ BSSY B0, 0x270 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0130*/ IADD3 R21, R21, c[0x0][0x0], RZ ; /* 0x0000000015157a10 */
/* 0x002fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P1, PT, R21, R20, PT ; /* 0x000000141500720c */
/* 0x000fe20003f26270 */
/*0150*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x008e540000000000 */
/*0160*/ FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x002fe20003f4e200 */
/*0170*/ I2F.F64.U64 R2, R2 ; /* 0x0000000200027312 */
/* 0x004e700000301800 */
/*0180*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x002e640000001800 */
/*0190*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x002e4c000000010a */
/*01a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x002e4c000000000c */
/*01b0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002e4c000000000a */
/*01c0*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x002e4c000000010c */
/*01d0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x002e4c000000000c */
/*01e0*/ DMUL R4, R14, R10 ; /* 0x0000000a0e047228 */
/* 0x002e4c0000000000 */
/*01f0*/ DFMA R12, -R2, R4, R14 ; /* 0x00000004020c722b */
/* 0x002e4c000000010e */
/*0200*/ DFMA R4, R10, R12, R4 ; /* 0x0000000c0a04722b */
/* 0x002e540000000004 */
/*0210*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x002fca0000000005 */
/*0220*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0230*/ @P0 BRA P2, 0x260 ; /* 0x0000002000000947 */
/* 0x000fea0001000000 */
/*0240*/ MOV R0, 0x260 ; /* 0x0000026000007802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x2b0 ; /* 0x0000005000007944 */
/* 0x021fea0003c00000 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ DADD R8, R4, R8 ; /* 0x0000000004087229 */
/* 0x020e8e0000000008 */
/*0280*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0045e2000c101b04 */
/*0290*/ @!P1 BRA 0xc0 ; /* 0xfffffe2000009947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*02d0*/ LOP3.LUT R10, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff030a7812 */
/* 0x000fe200078ec0ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*02f0*/ FSETP.GEU.AND P3, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f6e200 */
/*0300*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0330*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0350*/ LOP3.LUT R25, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003197812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*0370*/ BSSY B1, 0x860 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f46070 */
/*03a0*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*03b0*/ @!P3 LOP3.LUT R17, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d11b812 */
/* 0x000fe200078ec0ff */
/*03c0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12b224 */
/* 0x000fe200078e00ff */
/*03d0*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e220000001800 */
/*03e0*/ SEL R3, R23, 0x63400000, !P2 ; /* 0x6340000017037807 */
/* 0x000fe40005000000 */
/*03f0*/ @!P3 ISETP.GE.U32.AND P4, PT, R22, R17, PT ; /* 0x000000111600b20c */
/* 0x000fe40003f86070 */
/*0400*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80f */
/*0410*/ @!P3 SEL R19, R23, 0x63400000, !P4 ; /* 0x634000001713b807 */
/* 0x000fe40006000000 */
/*0420*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fc400078ec0ff */
/*0430*/ @!P3 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313b812 */
/* 0x000fe400078ef80f */
/*0440*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ @!P3 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313b812 */
/* 0x000fe200078efcff */
/*0460*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e0a000000080a */
/*0470*/ @!P3 DFMA R2, R2, 2, -R18 ; /* 0x400000000202b82b */
/* 0x000fc80000000812 */
/*0480*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0490*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*04a0*/ @!P3 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318b812 */
/* 0x000fc800078ec0ff */
/*04b0*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*04e0*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*04f0*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0500*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0520*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0530*/ @P0 BRA 0x700 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*0570*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*0580*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*0590*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*05a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*05b0*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*05c0*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*05d0*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*05e0*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*05f0*/ @P0 BRA 0x850 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0600*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0620*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0630*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*0640*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*0650*/ @!P0 BRA 0x850 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0670*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0690*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*06a0*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*06b0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06d0*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*06e0*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*06f0*/ BRA 0x850 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0700*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0710*/ @P0 BRA 0x830 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0730*/ @P0 BRA 0x800 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0770*/ @!P0 BRA 0x850 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*0790*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*07a0*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*07b0*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff77002007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiPyPd
.globl _Z6squarePiPyPd
.p2align 8
.type _Z6squarePiPyPd,@function
_Z6squarePiPyPd:
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x24
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[3:4], v0, s[6:7]
v_add_co_u32 v5, s1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s7, 0, s1
s_add_u32 s0, s4, -8
s_addc_u32 s1, s5, -1
s_and_b32 s4, s3, 0xffff
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f64_i32_e32 v[10:11], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[8:9], v8
v_cvt_f64_u32_e32 v[12:13], v7
v_ldexp_f64 v[7:8], v[8:9], 32
v_mul_f64 v[9:10], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[12:13]
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s3, vcc_lo, s3
v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[7:8]
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
global_store_b64 v[5:6], v[3:4], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiPyPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiPyPd, .Lfunc_end0-_Z6squarePiPyPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiPyPd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6squarePiPyPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c0bf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6squarePiPyPdPiPyPd
.type _Z29__device_stub__Z6squarePiPyPdPiPyPd, @function
_Z29__device_stub__Z6squarePiPyPdPiPyPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6squarePiPyPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6squarePiPyPdPiPyPd, .-_Z29__device_stub__Z6squarePiPyPdPiPyPd
.globl _Z6squarePiPyPd
.type _Z6squarePiPyPd, @function
_Z6squarePiPyPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6squarePiPyPdPiPyPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6squarePiPyPd, .-_Z6squarePiPyPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6squarePiPyPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiPyPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.globl _Z21__device_stub__squarePiPyPd # -- Begin function _Z21__device_stub__squarePiPyPd
.p2align 4, 0x90
.type _Z21__device_stub__squarePiPyPd,@function
_Z21__device_stub__squarePiPyPd: # @_Z21__device_stub__squarePiPyPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePiPyPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiPyPd, .Lfunc_end0-_Z21__device_stub__squarePiPyPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiPyPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiPyPd,@object # @_Z6squarePiPyPd
.section .rodata,"a",@progbits
.globl _Z6squarePiPyPd
.p2align 3, 0x0
_Z6squarePiPyPd:
.quad _Z21__device_stub__squarePiPyPd
.size _Z6squarePiPyPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6squarePiPyPd"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiPyPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiPyPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define allnorm_kernel (1.0F/26.0F)*(1.0F/10.0F)
#define norm_kernel 1.0/51076
#define ONE_THIRD_GPU 0.33333333333333333333F /* 1/3 */
#define ONE_FOURTH_GPU 0.25F /* 1/4 */
#define ONE_SIXTH_GPU 0.16666666666666666666F /* 1/6 */
__global__ void kernel_warmingup(){}
__global__ void kernel_strong_corners(int *gradxy,float *cornerness,int width,int height)
{
//printf("%d ",*atom);
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if( (hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6))/*&&(gradxy[gg*N+hh])&&(cornerness[gg*N+hh]<28744.000000)*/ )
{
if(cornerness[gg*N+hh]<0)
gradxy[gg*N+hh]=0;
}
}
__global__ void kernel_memset(int *gradxy,int width,int height)
{
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
gradxy[gg*width+hh]=0;
}
}
__global__ void kernel_imgblurg_separable_1(int *gradx2,int *result,int *grady2,int *result1,int *gradxy,int *result2,int width,int height)
{
int imageW=height;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
result[hh*imageW+gg]=1*gradx2[hh*imageW+gg-3]+12*gradx2[hh*imageW+gg-2]+55*gradx2[hh*imageW+gg-1]+90*gradx2[hh*imageW+gg]+55*gradx2[hh*imageW+gg+1]+
12*gradx2[hh*imageW+gg+2]+1*gradx2[hh*imageW+gg+3];
result1[hh*imageW+gg]=1*grady2[hh*imageW+gg-3]+12*grady2[hh*imageW+gg-2]+55*grady2[hh*imageW+gg-1]+90*grady2[hh*imageW+gg]+55*grady2[hh*imageW+gg+1]+
12*grady2[hh*imageW+gg+2]+1*grady2[hh*imageW+gg+3];
result2[hh*imageW+gg]=1*gradxy[hh*imageW+gg-3]+12*gradxy[hh*imageW+gg-2]+55*gradxy[hh*imageW+gg-1]+90*gradxy[hh*imageW+gg]+55*gradxy[hh*imageW+gg+1]+
12*gradxy[hh*imageW+gg+2]+1*gradxy[hh*imageW+gg+3];
}
}
__global__ void kernel_imgblurg_separable_2(int *gradx2,int *result,int *input,int *grady2,int *result1,int *input1,int *gradxy,int *result2,int *input2,int width,int height)
{
int imageW=width;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((gg<width)&&(hh<height))
{
if((gg>=3)&&(hh<(height-3))&&(hh>=3)&&(gg<(width-3)))
{
result[hh*imageW+gg]=norm_kernel*(1*gradx2[(hh-3)*imageW+gg]+12*gradx2[(hh-2)*imageW+gg]+55*gradx2[(hh-1)*imageW+gg]+90*gradx2[hh*imageW+gg]+55*gradx2[(hh+1)*imageW+gg]+
12*gradx2[(hh+2)*imageW+gg]+1*gradx2[(hh+3)*imageW+gg]);
result1[hh*imageW+gg]=norm_kernel*(1*grady2[(hh-3)*imageW+gg]+12*grady2[(hh-2)*imageW+gg]+55*grady2[(hh-1)*imageW+gg]+90*grady2[hh*imageW+gg]+55*grady2[(hh+1)*imageW+gg]+
12*grady2[(hh+2)*imageW+gg]+1*grady2[(hh+3)*imageW+gg]);
result2[hh*imageW+gg]=norm_kernel*(1*gradxy[(hh-3)*imageW+gg]+12*gradxy[(hh-2)*imageW+gg]+55*gradxy[(hh-1)*imageW+gg]+90*gradxy[hh*imageW+gg]+55*gradxy[(hh+1)*imageW+gg]+
12*gradxy[(hh+2)*imageW+gg]+1*gradxy[(hh+3)*imageW+gg]);
}
else{
result[hh*imageW+gg]= input[hh*imageW+gg];
result1[hh*imageW+gg]= input1[hh*imageW+gg];
result2[hh*imageW+gg]= input2[hh*imageW+gg];
}
}
}
__global__ void kernel_find_max(float *array, float *max, int *mutex, unsigned int n)
{
unsigned int index = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = gridDim.x*blockDim.x;
unsigned int offset = 0;
__shared__ float cache[256];
float temp = -1.0;
while(index + offset < n){
temp = fmaxf(temp, array[index + offset]);
offset += stride;
}
cache[threadIdx.x] = temp;
__syncthreads();
// reduction
unsigned int i = blockDim.x/2;
while(i != 0){
if(threadIdx.x < i){
cache[threadIdx.x] = fmaxf(cache[threadIdx.x], cache[threadIdx.x + i]);
}
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0){
while(atomicCAS(mutex,0,1) != 0); //lock
*max = fmaxf(*max, cache[0]);
atomicExch(mutex, 0); //unlock
}
}
__global__ void kernel_selcornerness(float *cornerness,float *selcornerness,int width, int height,int *gradxy,float *maximum,int *seirial,float RELMINTHR)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float d;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
d=cornerness[gg*N+hh];
if(d>=((*maximum)*RELMINTHR))
{
if ( (d>cornerness[(gg)*N+(hh+1)]) &&(d>=cornerness[(gg)*N+(hh-1)])&&(d>=cornerness[(gg+1)*N+(hh+1)])
&&(d>=cornerness[(gg+1)*N+(hh-1)])&&(d>cornerness[(gg-1)*N+(hh+1)] ) && (d>cornerness[(gg-1)*N+(hh-1)]) &&(d>=cornerness[(gg+1)*N+(hh)]) &&(d>cornerness[(gg-1)*N+(hh)]) )
{
atomicAdd(seirial,1);
gradxy[gg*N+hh]=1;
}
}
}
}
__global__ void kernel_cornerness(int *gradx2_b,int *grady2_b,int *gradxy_b,float *cornerness,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=5)&&(hh<(width-5))&&(gg>=5)&&(gg<(height-5)))
{
int det,trace;
float r;
int gxx,gyy,gxy;
gxx=gradx2_b[gg*N+hh];
gyy=grady2_b[gg*N+hh];
gxy=gradxy_b[gg*N+hh];
det=gxx*gyy - gxy*gxy;
trace=gxx + gyy;
r=det - 0.04*trace*trace;
if(r<0.0F) r=0.0F;
cornerness[gg*N+hh]=r;
}
}
__global__ void kernel_Ix2y2xy(int *gradx,int *grady,int *gradx2,int *grady2,int *gradxy,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=0)&&(hh<width)&&(gg>=0)&&(gg<height))
{
gradx2[gg*N+hh]= gradx[gg*N+hh]* gradx[gg*N+hh];
grady2[gg*N+hh]= grady[gg*N+hh]* grady[gg*N+hh];
gradxy[gg*N+hh]= gradx[gg*N+hh]* grady[gg*N+hh];
}
}
__global__ void kernel_imgradient5_smo(unsigned char *img,int width,int height, int *gradx2,int *grady2, int *gradx, int *grady)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
if((hh>=2)&&(hh<(width-2))&&(gg>=2)&&(gg<(height-2)))
{
int N=width;
gradx[gg*N+hh]=allnorm_kernel*(36*(img[gg*N+hh+1]-img[gg*N+hh-1]) +
18*(img[(gg+1)*N+hh+1]+img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]-img[(gg+1)*N+hh-1]) +
12*(img[(gg*N+hh+2)]-img[gg*N+hh-2]) +
6*(img[(gg+1)*N+hh+2]+img[(gg-1)*N+hh+2]-img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh-2]) +
3*(img[(gg+2)*N+hh+1]+img[(gg-2)*N+hh+1]-img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh-1]) +
1*(img[(gg+2)*N+hh+2]+img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]-img[(gg+2)*N+hh-2]));
grady[gg*N+hh] = allnorm_kernel*(36*(img[(gg+1)*N+hh]-img[(gg-1)*N+hh]) +
18*(img[(gg+1)*N+hh+1]+img[(gg+1)*N+hh-1]-img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]) +
12*(img[(gg+2)*N+hh]-img[(gg-2)*N+hh]) +
6*(img[(gg+2)*N+hh+1]+img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh+1]-img[(gg-2)*N+hh-1]) +
3*(img[(gg+1)*N+hh+2]+img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh+2]-img[(gg-1)*N+hh-2]) +
1*(img[(gg+2)*N+hh+2]+img[(gg+2)*N+hh-2]-img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]));
}
}
__device__ float kati(float x)
{
float xhalf;
int i;
/* compute inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
/* compute fourth root as the inverse square root of the inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
return x;
}
__global__ void kernel_coordinates(float* cornerness, float (*corners)[2],int *gradxy,int width,int height,int *atom2)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float spp, spc, spn, scp, scc, scn, snp, snc, snn;
float Pxx, Pxy, Pyy, Px, Py, ucorr, vcorr, detf;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
if(gradxy[gg*N+hh])
{
spp=kati(cornerness[(gg-1)*N+(hh-1)]);
spc=kati(cornerness[(gg-1)*N+(hh)]);
spn=kati(cornerness[(gg-1)*N+(hh+1)]);
scp=kati(cornerness[(gg)*N+(hh-1)]);
scc=kati(cornerness[(gg)*N+(hh)]);
scn=kati(cornerness[(gg)*N+(hh+1)]);
snp=kati(cornerness[(gg+1)*N+(hh-1)]);
snc=kati(cornerness[(gg+1)*N+(hh)]);
snn=kati(cornerness[(gg+1)*N+(hh+1)]);
Pxx=(spp + scp + snp -2.0F*(spc + scc + snc) + spn + scn + snn)*ONE_THIRD_GPU;
Pxy=(spp - spn - snp + snn)*ONE_FOURTH_GPU;
Pyy= (spp + spc + spn
-2.0F*(scp + scc + scn)
+ snp + snc + snn)*ONE_THIRD_GPU;
Px=(- spp - scp - snp + spn + scn + snn)*ONE_SIXTH_GPU;
Py=(- spp - spc - spn + snp + snc + snn)*ONE_SIXTH_GPU;
detf=Pxy*Pxy - Pxx*Pyy;
if(detf>=1E-12F || detf<=-1E-12F){ // nonzero determinant
// calculate sub-pixel corrections to the corner position
ucorr=(Pyy*Px - Pxy*Py)/detf;
vcorr=(Pxx*Py - Pxy*Px)/detf;
// pull the corrections inside the pixel
// printf("a=%lf ",ucorr );
if(ucorr>0.5F) ucorr=0.5F; else if(ucorr<-0.5F) ucorr=-0.5F;
if(vcorr>0.5F) vcorr=0.5F; else if(vcorr<-0.5F) vcorr=-0.5F;
// printf("xx");
}
else
{
ucorr=vcorr=0.0F;
}
int x=atomicAdd(atom2,1);
//cornrs_big[gg*N+hh][0]=/*u0*/hh+ucorr;
//cornrs_big[gg*N+hh][1]=/*v0*/gg+vcorr;
//printf("%lf ",ucorr);
corners[x][0]=hh+ucorr;
corners[x][1]=gg+vcorr;
}
}
} | .file "tmpxft_000e1ccc_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4katif
.type _Z4katif, @function
_Z4katif:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4katif, .-_Z4katif
.globl _Z35__device_stub__Z16kernel_warmingupvv
.type _Z35__device_stub__Z16kernel_warmingupvv, @function
_Z35__device_stub__Z16kernel_warmingupvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16kernel_warmingupv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z16kernel_warmingupvv, .-_Z35__device_stub__Z16kernel_warmingupvv
.globl _Z16kernel_warmingupv
.type _Z16kernel_warmingupv, @function
_Z16kernel_warmingupv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16kernel_warmingupvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16kernel_warmingupv, .-_Z16kernel_warmingupv
.globl _Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii
.type _Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii, @function
_Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernel_strong_cornersPiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii, .-_Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii
.globl _Z21kernel_strong_cornersPiPfii
.type _Z21kernel_strong_cornersPiPfii, @function
_Z21kernel_strong_cornersPiPfii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21kernel_strong_cornersPiPfiiPiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z21kernel_strong_cornersPiPfii, .-_Z21kernel_strong_cornersPiPfii
.globl _Z35__device_stub__Z13kernel_memsetPiiiPiii
.type _Z35__device_stub__Z13kernel_memsetPiiiPiii, @function
_Z35__device_stub__Z13kernel_memsetPiiiPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_memsetPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z35__device_stub__Z13kernel_memsetPiiiPiii, .-_Z35__device_stub__Z13kernel_memsetPiiiPiii
.globl _Z13kernel_memsetPiii
.type _Z13kernel_memsetPiii, @function
_Z13kernel_memsetPiii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13kernel_memsetPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13kernel_memsetPiii, .-_Z13kernel_memsetPiii
.globl _Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2058:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.type _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii, @function
_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z59__device_stub__Z27kernel_imgblurg_separable_1PiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii, .-_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.globl _Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii
.type _Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii, @function
_Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii:
.LFB2060:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii, .-_Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii
.globl _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.type _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, @function
_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii:
.LFB2061:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z65__device_stub__Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_S_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, .-_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.globl _Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij
.type _Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij, @function
_Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij:
.LFB2062:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kernel_find_maxPfS_Pij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij, .-_Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij
.globl _Z15kernel_find_maxPfS_Pij
.type _Z15kernel_find_maxPfS_Pij, @function
_Z15kernel_find_maxPfS_Pij:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15kernel_find_maxPfS_PijPfS_Pij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z15kernel_find_maxPfS_Pij, .-_Z15kernel_find_maxPfS_Pij
.globl _Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f
.type _Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f, @function
_Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f:
.LFB2064:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 12(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20kernel_selcornernessPfS_iiPiS_S0_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f, .-_Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f
.globl _Z20kernel_selcornernessPfS_iiPiS_S0_f
.type _Z20kernel_selcornernessPfS_iiPiS_S0_f, @function
_Z20kernel_selcornernessPfS_iiPiS_S0_f:
.LFB2065:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z52__device_stub__Z20kernel_selcornernessPfS_iiPiS_S0_fPfS_iiPiS_S0_f
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z20kernel_selcornernessPfS_iiPiS_S0_f, .-_Z20kernel_selcornernessPfS_iiPiS_S0_f
.globl _Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii
.type _Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii, @function
_Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii:
.LFB2066:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17kernel_cornernessPiS_S_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii, .-_Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii
.globl _Z17kernel_cornernessPiS_S_Pfii
.type _Z17kernel_cornernessPiS_S_Pfii, @function
_Z17kernel_cornernessPiS_S_Pfii:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17kernel_cornernessPiS_S_PfiiPiS_S_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _Z17kernel_cornernessPiS_S_Pfii, .-_Z17kernel_cornernessPiS_S_Pfii
.globl _Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii
.type _Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii, @function
_Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii:
.LFB2068:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14kernel_Ix2y2xyPiS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii, .-_Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii
.globl _Z14kernel_Ix2y2xyPiS_S_S_S_ii
.type _Z14kernel_Ix2y2xyPiS_S_S_S_ii, @function
_Z14kernel_Ix2y2xyPiS_S_S_S_ii:
.LFB2069:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z14kernel_Ix2y2xyPiS_S_S_S_iiPiS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z14kernel_Ix2y2xyPiS_S_S_S_ii, .-_Z14kernel_Ix2y2xyPiS_S_S_S_ii
.globl _Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_
.type _Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_, @function
_Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_:
.LFB2070:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_, .-_Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_
.globl _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_
.type _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_, @function
_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_:
.LFB2071:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_PhiiPiS0_S0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_, .-_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_
.globl _Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_
.type _Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_, @function
_Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_:
.LFB2072:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L89
.L85:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kernel_coordinatesPfPA2_fPiiiS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L85
.L90:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size _Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_, .-_Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_
.globl _Z18kernel_coordinatesPfPA2_fPiiiS2_
.type _Z18kernel_coordinatesPfPA2_fPiiiS2_, @function
_Z18kernel_coordinatesPfPA2_fPiiiS2_:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z18kernel_coordinatesPfPA2_fPiiiS2_PfPA2_fPiiiS2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z18kernel_coordinatesPfPA2_fPiiiS2_, .-_Z18kernel_coordinatesPfPA2_fPiiiS2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_coordinatesPfPA2_fPiiiS2_"
.align 8
.LC1:
.string "_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_"
.align 8
.LC2:
.string "_Z14kernel_Ix2y2xyPiS_S_S_S_ii"
.align 8
.LC3:
.string "_Z17kernel_cornernessPiS_S_Pfii"
.align 8
.LC4:
.string "_Z20kernel_selcornernessPfS_iiPiS_S0_f"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z15kernel_find_maxPfS_Pij"
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii"
.align 8
.LC7:
.string "_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii"
.section .rodata.str1.1
.LC8:
.string "_Z13kernel_memsetPiii"
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z21kernel_strong_cornersPiPfii"
.section .rodata.str1.1
.LC10:
.string "_Z16kernel_warmingupv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2075:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_coordinatesPfPA2_fPiiiS2_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_Ix2y2xyPiS_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_cornernessPiS_S_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kernel_selcornernessPfS_iiPiS_S0_f(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_find_maxPfS_Pij(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_memsetPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernel_strong_cornersPiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_warmingupv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define allnorm_kernel (1.0F/26.0F)*(1.0F/10.0F)
#define norm_kernel 1.0/51076
#define ONE_THIRD_GPU 0.33333333333333333333F /* 1/3 */
#define ONE_FOURTH_GPU 0.25F /* 1/4 */
#define ONE_SIXTH_GPU 0.16666666666666666666F /* 1/6 */
__global__ void kernel_warmingup(){}
__global__ void kernel_strong_corners(int *gradxy,float *cornerness,int width,int height)
{
//printf("%d ",*atom);
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if( (hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6))/*&&(gradxy[gg*N+hh])&&(cornerness[gg*N+hh]<28744.000000)*/ )
{
if(cornerness[gg*N+hh]<0)
gradxy[gg*N+hh]=0;
}
}
__global__ void kernel_memset(int *gradxy,int width,int height)
{
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
gradxy[gg*width+hh]=0;
}
}
__global__ void kernel_imgblurg_separable_1(int *gradx2,int *result,int *grady2,int *result1,int *gradxy,int *result2,int width,int height)
{
int imageW=height;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
result[hh*imageW+gg]=1*gradx2[hh*imageW+gg-3]+12*gradx2[hh*imageW+gg-2]+55*gradx2[hh*imageW+gg-1]+90*gradx2[hh*imageW+gg]+55*gradx2[hh*imageW+gg+1]+
12*gradx2[hh*imageW+gg+2]+1*gradx2[hh*imageW+gg+3];
result1[hh*imageW+gg]=1*grady2[hh*imageW+gg-3]+12*grady2[hh*imageW+gg-2]+55*grady2[hh*imageW+gg-1]+90*grady2[hh*imageW+gg]+55*grady2[hh*imageW+gg+1]+
12*grady2[hh*imageW+gg+2]+1*grady2[hh*imageW+gg+3];
result2[hh*imageW+gg]=1*gradxy[hh*imageW+gg-3]+12*gradxy[hh*imageW+gg-2]+55*gradxy[hh*imageW+gg-1]+90*gradxy[hh*imageW+gg]+55*gradxy[hh*imageW+gg+1]+
12*gradxy[hh*imageW+gg+2]+1*gradxy[hh*imageW+gg+3];
}
}
__global__ void kernel_imgblurg_separable_2(int *gradx2,int *result,int *input,int *grady2,int *result1,int *input1,int *gradxy,int *result2,int *input2,int width,int height)
{
int imageW=width;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((gg<width)&&(hh<height))
{
if((gg>=3)&&(hh<(height-3))&&(hh>=3)&&(gg<(width-3)))
{
result[hh*imageW+gg]=norm_kernel*(1*gradx2[(hh-3)*imageW+gg]+12*gradx2[(hh-2)*imageW+gg]+55*gradx2[(hh-1)*imageW+gg]+90*gradx2[hh*imageW+gg]+55*gradx2[(hh+1)*imageW+gg]+
12*gradx2[(hh+2)*imageW+gg]+1*gradx2[(hh+3)*imageW+gg]);
result1[hh*imageW+gg]=norm_kernel*(1*grady2[(hh-3)*imageW+gg]+12*grady2[(hh-2)*imageW+gg]+55*grady2[(hh-1)*imageW+gg]+90*grady2[hh*imageW+gg]+55*grady2[(hh+1)*imageW+gg]+
12*grady2[(hh+2)*imageW+gg]+1*grady2[(hh+3)*imageW+gg]);
result2[hh*imageW+gg]=norm_kernel*(1*gradxy[(hh-3)*imageW+gg]+12*gradxy[(hh-2)*imageW+gg]+55*gradxy[(hh-1)*imageW+gg]+90*gradxy[hh*imageW+gg]+55*gradxy[(hh+1)*imageW+gg]+
12*gradxy[(hh+2)*imageW+gg]+1*gradxy[(hh+3)*imageW+gg]);
}
else{
result[hh*imageW+gg]= input[hh*imageW+gg];
result1[hh*imageW+gg]= input1[hh*imageW+gg];
result2[hh*imageW+gg]= input2[hh*imageW+gg];
}
}
}
__global__ void kernel_find_max(float *array, float *max, int *mutex, unsigned int n)
{
unsigned int index = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = gridDim.x*blockDim.x;
unsigned int offset = 0;
__shared__ float cache[256];
float temp = -1.0;
while(index + offset < n){
temp = fmaxf(temp, array[index + offset]);
offset += stride;
}
cache[threadIdx.x] = temp;
__syncthreads();
// reduction
unsigned int i = blockDim.x/2;
while(i != 0){
if(threadIdx.x < i){
cache[threadIdx.x] = fmaxf(cache[threadIdx.x], cache[threadIdx.x + i]);
}
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0){
while(atomicCAS(mutex,0,1) != 0); //lock
*max = fmaxf(*max, cache[0]);
atomicExch(mutex, 0); //unlock
}
}
__global__ void kernel_selcornerness(float *cornerness,float *selcornerness,int width, int height,int *gradxy,float *maximum,int *seirial,float RELMINTHR)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float d;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
d=cornerness[gg*N+hh];
if(d>=((*maximum)*RELMINTHR))
{
if ( (d>cornerness[(gg)*N+(hh+1)]) &&(d>=cornerness[(gg)*N+(hh-1)])&&(d>=cornerness[(gg+1)*N+(hh+1)])
&&(d>=cornerness[(gg+1)*N+(hh-1)])&&(d>cornerness[(gg-1)*N+(hh+1)] ) && (d>cornerness[(gg-1)*N+(hh-1)]) &&(d>=cornerness[(gg+1)*N+(hh)]) &&(d>cornerness[(gg-1)*N+(hh)]) )
{
atomicAdd(seirial,1);
gradxy[gg*N+hh]=1;
}
}
}
}
__global__ void kernel_cornerness(int *gradx2_b,int *grady2_b,int *gradxy_b,float *cornerness,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=5)&&(hh<(width-5))&&(gg>=5)&&(gg<(height-5)))
{
int det,trace;
float r;
int gxx,gyy,gxy;
gxx=gradx2_b[gg*N+hh];
gyy=grady2_b[gg*N+hh];
gxy=gradxy_b[gg*N+hh];
det=gxx*gyy - gxy*gxy;
trace=gxx + gyy;
r=det - 0.04*trace*trace;
if(r<0.0F) r=0.0F;
cornerness[gg*N+hh]=r;
}
}
__global__ void kernel_Ix2y2xy(int *gradx,int *grady,int *gradx2,int *grady2,int *gradxy,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=0)&&(hh<width)&&(gg>=0)&&(gg<height))
{
gradx2[gg*N+hh]= gradx[gg*N+hh]* gradx[gg*N+hh];
grady2[gg*N+hh]= grady[gg*N+hh]* grady[gg*N+hh];
gradxy[gg*N+hh]= gradx[gg*N+hh]* grady[gg*N+hh];
}
}
__global__ void kernel_imgradient5_smo(unsigned char *img,int width,int height, int *gradx2,int *grady2, int *gradx, int *grady)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
if((hh>=2)&&(hh<(width-2))&&(gg>=2)&&(gg<(height-2)))
{
int N=width;
gradx[gg*N+hh]=allnorm_kernel*(36*(img[gg*N+hh+1]-img[gg*N+hh-1]) +
18*(img[(gg+1)*N+hh+1]+img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]-img[(gg+1)*N+hh-1]) +
12*(img[(gg*N+hh+2)]-img[gg*N+hh-2]) +
6*(img[(gg+1)*N+hh+2]+img[(gg-1)*N+hh+2]-img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh-2]) +
3*(img[(gg+2)*N+hh+1]+img[(gg-2)*N+hh+1]-img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh-1]) +
1*(img[(gg+2)*N+hh+2]+img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]-img[(gg+2)*N+hh-2]));
grady[gg*N+hh] = allnorm_kernel*(36*(img[(gg+1)*N+hh]-img[(gg-1)*N+hh]) +
18*(img[(gg+1)*N+hh+1]+img[(gg+1)*N+hh-1]-img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]) +
12*(img[(gg+2)*N+hh]-img[(gg-2)*N+hh]) +
6*(img[(gg+2)*N+hh+1]+img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh+1]-img[(gg-2)*N+hh-1]) +
3*(img[(gg+1)*N+hh+2]+img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh+2]-img[(gg-1)*N+hh-2]) +
1*(img[(gg+2)*N+hh+2]+img[(gg+2)*N+hh-2]-img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]));
}
}
__device__ float kati(float x)
{
float xhalf;
int i;
/* compute inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
/* compute fourth root as the inverse square root of the inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
return x;
}
__global__ void kernel_coordinates(float* cornerness, float (*corners)[2],int *gradxy,int width,int height,int *atom2)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float spp, spc, spn, scp, scc, scn, snp, snc, snn;
float Pxx, Pxy, Pyy, Px, Py, ucorr, vcorr, detf;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
if(gradxy[gg*N+hh])
{
spp=kati(cornerness[(gg-1)*N+(hh-1)]);
spc=kati(cornerness[(gg-1)*N+(hh)]);
spn=kati(cornerness[(gg-1)*N+(hh+1)]);
scp=kati(cornerness[(gg)*N+(hh-1)]);
scc=kati(cornerness[(gg)*N+(hh)]);
scn=kati(cornerness[(gg)*N+(hh+1)]);
snp=kati(cornerness[(gg+1)*N+(hh-1)]);
snc=kati(cornerness[(gg+1)*N+(hh)]);
snn=kati(cornerness[(gg+1)*N+(hh+1)]);
Pxx=(spp + scp + snp -2.0F*(spc + scc + snc) + spn + scn + snn)*ONE_THIRD_GPU;
Pxy=(spp - spn - snp + snn)*ONE_FOURTH_GPU;
Pyy= (spp + spc + spn
-2.0F*(scp + scc + scn)
+ snp + snc + snn)*ONE_THIRD_GPU;
Px=(- spp - scp - snp + spn + scn + snn)*ONE_SIXTH_GPU;
Py=(- spp - spc - spn + snp + snc + snn)*ONE_SIXTH_GPU;
detf=Pxy*Pxy - Pxx*Pyy;
if(detf>=1E-12F || detf<=-1E-12F){ // nonzero determinant
// calculate sub-pixel corrections to the corner position
ucorr=(Pyy*Px - Pxy*Py)/detf;
vcorr=(Pxx*Py - Pxy*Px)/detf;
// pull the corrections inside the pixel
// printf("a=%lf ",ucorr );
if(ucorr>0.5F) ucorr=0.5F; else if(ucorr<-0.5F) ucorr=-0.5F;
if(vcorr>0.5F) vcorr=0.5F; else if(vcorr<-0.5F) vcorr=-0.5F;
// printf("xx");
}
else
{
ucorr=vcorr=0.0F;
}
int x=atomicAdd(atom2,1);
//cornrs_big[gg*N+hh][0]=/*u0*/hh+ucorr;
//cornrs_big[gg*N+hh][1]=/*v0*/gg+vcorr;
//printf("%lf ",ucorr);
corners[x][0]=hh+ucorr;
corners[x][1]=gg+vcorr;
}
}
} | #include <hip/hip_runtime.h>
#define allnorm_kernel (1.0F/26.0F)*(1.0F/10.0F)
#define norm_kernel 1.0/51076
#define ONE_THIRD_GPU 0.33333333333333333333F /* 1/3 */
#define ONE_FOURTH_GPU 0.25F /* 1/4 */
#define ONE_SIXTH_GPU 0.16666666666666666666F /* 1/6 */
__global__ void kernel_warmingup(){}
__global__ void kernel_strong_corners(int *gradxy,float *cornerness,int width,int height)
{
//printf("%d ",*atom);
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if( (hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6))/*&&(gradxy[gg*N+hh])&&(cornerness[gg*N+hh]<28744.000000)*/ )
{
if(cornerness[gg*N+hh]<0)
gradxy[gg*N+hh]=0;
}
}
__global__ void kernel_memset(int *gradxy,int width,int height)
{
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
gradxy[gg*width+hh]=0;
}
}
__global__ void kernel_imgblurg_separable_1(int *gradx2,int *result,int *grady2,int *result1,int *gradxy,int *result2,int width,int height)
{
int imageW=height;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
result[hh*imageW+gg]=1*gradx2[hh*imageW+gg-3]+12*gradx2[hh*imageW+gg-2]+55*gradx2[hh*imageW+gg-1]+90*gradx2[hh*imageW+gg]+55*gradx2[hh*imageW+gg+1]+
12*gradx2[hh*imageW+gg+2]+1*gradx2[hh*imageW+gg+3];
result1[hh*imageW+gg]=1*grady2[hh*imageW+gg-3]+12*grady2[hh*imageW+gg-2]+55*grady2[hh*imageW+gg-1]+90*grady2[hh*imageW+gg]+55*grady2[hh*imageW+gg+1]+
12*grady2[hh*imageW+gg+2]+1*grady2[hh*imageW+gg+3];
result2[hh*imageW+gg]=1*gradxy[hh*imageW+gg-3]+12*gradxy[hh*imageW+gg-2]+55*gradxy[hh*imageW+gg-1]+90*gradxy[hh*imageW+gg]+55*gradxy[hh*imageW+gg+1]+
12*gradxy[hh*imageW+gg+2]+1*gradxy[hh*imageW+gg+3];
}
}
__global__ void kernel_imgblurg_separable_2(int *gradx2,int *result,int *input,int *grady2,int *result1,int *input1,int *gradxy,int *result2,int *input2,int width,int height)
{
int imageW=width;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((gg<width)&&(hh<height))
{
if((gg>=3)&&(hh<(height-3))&&(hh>=3)&&(gg<(width-3)))
{
result[hh*imageW+gg]=norm_kernel*(1*gradx2[(hh-3)*imageW+gg]+12*gradx2[(hh-2)*imageW+gg]+55*gradx2[(hh-1)*imageW+gg]+90*gradx2[hh*imageW+gg]+55*gradx2[(hh+1)*imageW+gg]+
12*gradx2[(hh+2)*imageW+gg]+1*gradx2[(hh+3)*imageW+gg]);
result1[hh*imageW+gg]=norm_kernel*(1*grady2[(hh-3)*imageW+gg]+12*grady2[(hh-2)*imageW+gg]+55*grady2[(hh-1)*imageW+gg]+90*grady2[hh*imageW+gg]+55*grady2[(hh+1)*imageW+gg]+
12*grady2[(hh+2)*imageW+gg]+1*grady2[(hh+3)*imageW+gg]);
result2[hh*imageW+gg]=norm_kernel*(1*gradxy[(hh-3)*imageW+gg]+12*gradxy[(hh-2)*imageW+gg]+55*gradxy[(hh-1)*imageW+gg]+90*gradxy[hh*imageW+gg]+55*gradxy[(hh+1)*imageW+gg]+
12*gradxy[(hh+2)*imageW+gg]+1*gradxy[(hh+3)*imageW+gg]);
}
else{
result[hh*imageW+gg]= input[hh*imageW+gg];
result1[hh*imageW+gg]= input1[hh*imageW+gg];
result2[hh*imageW+gg]= input2[hh*imageW+gg];
}
}
}
__global__ void kernel_find_max(float *array, float *max, int *mutex, unsigned int n)
{
unsigned int index = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = gridDim.x*blockDim.x;
unsigned int offset = 0;
__shared__ float cache[256];
float temp = -1.0;
while(index + offset < n){
temp = fmaxf(temp, array[index + offset]);
offset += stride;
}
cache[threadIdx.x] = temp;
__syncthreads();
// reduction
unsigned int i = blockDim.x/2;
while(i != 0){
if(threadIdx.x < i){
cache[threadIdx.x] = fmaxf(cache[threadIdx.x], cache[threadIdx.x + i]);
}
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0){
while(atomicCAS(mutex,0,1) != 0); //lock
*max = fmaxf(*max, cache[0]);
atomicExch(mutex, 0); //unlock
}
}
__global__ void kernel_selcornerness(float *cornerness,float *selcornerness,int width, int height,int *gradxy,float *maximum,int *seirial,float RELMINTHR)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float d;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
d=cornerness[gg*N+hh];
if(d>=((*maximum)*RELMINTHR))
{
if ( (d>cornerness[(gg)*N+(hh+1)]) &&(d>=cornerness[(gg)*N+(hh-1)])&&(d>=cornerness[(gg+1)*N+(hh+1)])
&&(d>=cornerness[(gg+1)*N+(hh-1)])&&(d>cornerness[(gg-1)*N+(hh+1)] ) && (d>cornerness[(gg-1)*N+(hh-1)]) &&(d>=cornerness[(gg+1)*N+(hh)]) &&(d>cornerness[(gg-1)*N+(hh)]) )
{
atomicAdd(seirial,1);
gradxy[gg*N+hh]=1;
}
}
}
}
__global__ void kernel_cornerness(int *gradx2_b,int *grady2_b,int *gradxy_b,float *cornerness,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=5)&&(hh<(width-5))&&(gg>=5)&&(gg<(height-5)))
{
int det,trace;
float r;
int gxx,gyy,gxy;
gxx=gradx2_b[gg*N+hh];
gyy=grady2_b[gg*N+hh];
gxy=gradxy_b[gg*N+hh];
det=gxx*gyy - gxy*gxy;
trace=gxx + gyy;
r=det - 0.04*trace*trace;
if(r<0.0F) r=0.0F;
cornerness[gg*N+hh]=r;
}
}
__global__ void kernel_Ix2y2xy(int *gradx,int *grady,int *gradx2,int *grady2,int *gradxy,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=0)&&(hh<width)&&(gg>=0)&&(gg<height))
{
gradx2[gg*N+hh]= gradx[gg*N+hh]* gradx[gg*N+hh];
grady2[gg*N+hh]= grady[gg*N+hh]* grady[gg*N+hh];
gradxy[gg*N+hh]= gradx[gg*N+hh]* grady[gg*N+hh];
}
}
__global__ void kernel_imgradient5_smo(unsigned char *img,int width,int height, int *gradx2,int *grady2, int *gradx, int *grady)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
if((hh>=2)&&(hh<(width-2))&&(gg>=2)&&(gg<(height-2)))
{
int N=width;
gradx[gg*N+hh]=allnorm_kernel*(36*(img[gg*N+hh+1]-img[gg*N+hh-1]) +
18*(img[(gg+1)*N+hh+1]+img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]-img[(gg+1)*N+hh-1]) +
12*(img[(gg*N+hh+2)]-img[gg*N+hh-2]) +
6*(img[(gg+1)*N+hh+2]+img[(gg-1)*N+hh+2]-img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh-2]) +
3*(img[(gg+2)*N+hh+1]+img[(gg-2)*N+hh+1]-img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh-1]) +
1*(img[(gg+2)*N+hh+2]+img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]-img[(gg+2)*N+hh-2]));
grady[gg*N+hh] = allnorm_kernel*(36*(img[(gg+1)*N+hh]-img[(gg-1)*N+hh]) +
18*(img[(gg+1)*N+hh+1]+img[(gg+1)*N+hh-1]-img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]) +
12*(img[(gg+2)*N+hh]-img[(gg-2)*N+hh]) +
6*(img[(gg+2)*N+hh+1]+img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh+1]-img[(gg-2)*N+hh-1]) +
3*(img[(gg+1)*N+hh+2]+img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh+2]-img[(gg-1)*N+hh-2]) +
1*(img[(gg+2)*N+hh+2]+img[(gg+2)*N+hh-2]-img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]));
}
}
__device__ float kati(float x)
{
float xhalf;
int i;
/* compute inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
/* compute fourth root as the inverse square root of the inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
return x;
}
__global__ void kernel_coordinates(float* cornerness, float (*corners)[2],int *gradxy,int width,int height,int *atom2)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float spp, spc, spn, scp, scc, scn, snp, snc, snn;
float Pxx, Pxy, Pyy, Px, Py, ucorr, vcorr, detf;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
if(gradxy[gg*N+hh])
{
spp=kati(cornerness[(gg-1)*N+(hh-1)]);
spc=kati(cornerness[(gg-1)*N+(hh)]);
spn=kati(cornerness[(gg-1)*N+(hh+1)]);
scp=kati(cornerness[(gg)*N+(hh-1)]);
scc=kati(cornerness[(gg)*N+(hh)]);
scn=kati(cornerness[(gg)*N+(hh+1)]);
snp=kati(cornerness[(gg+1)*N+(hh-1)]);
snc=kati(cornerness[(gg+1)*N+(hh)]);
snn=kati(cornerness[(gg+1)*N+(hh+1)]);
Pxx=(spp + scp + snp -2.0F*(spc + scc + snc) + spn + scn + snn)*ONE_THIRD_GPU;
Pxy=(spp - spn - snp + snn)*ONE_FOURTH_GPU;
Pyy= (spp + spc + spn
-2.0F*(scp + scc + scn)
+ snp + snc + snn)*ONE_THIRD_GPU;
Px=(- spp - scp - snp + spn + scn + snn)*ONE_SIXTH_GPU;
Py=(- spp - spc - spn + snp + snc + snn)*ONE_SIXTH_GPU;
detf=Pxy*Pxy - Pxx*Pyy;
if(detf>=1E-12F || detf<=-1E-12F){ // nonzero determinant
// calculate sub-pixel corrections to the corner position
ucorr=(Pyy*Px - Pxy*Py)/detf;
vcorr=(Pxx*Py - Pxy*Px)/detf;
// pull the corrections inside the pixel
// printf("a=%lf ",ucorr );
if(ucorr>0.5F) ucorr=0.5F; else if(ucorr<-0.5F) ucorr=-0.5F;
if(vcorr>0.5F) vcorr=0.5F; else if(vcorr<-0.5F) vcorr=-0.5F;
// printf("xx");
}
else
{
ucorr=vcorr=0.0F;
}
int x=atomicAdd(atom2,1);
//cornrs_big[gg*N+hh][0]=/*u0*/hh+ucorr;
//cornrs_big[gg*N+hh][1]=/*v0*/gg+vcorr;
//printf("%lf ",ucorr);
corners[x][0]=hh+ucorr;
corners[x][1]=gg+vcorr;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define allnorm_kernel (1.0F/26.0F)*(1.0F/10.0F)
#define norm_kernel 1.0/51076
#define ONE_THIRD_GPU 0.33333333333333333333F /* 1/3 */
#define ONE_FOURTH_GPU 0.25F /* 1/4 */
#define ONE_SIXTH_GPU 0.16666666666666666666F /* 1/6 */
__global__ void kernel_warmingup(){}
__global__ void kernel_strong_corners(int *gradxy,float *cornerness,int width,int height)
{
//printf("%d ",*atom);
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if( (hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6))/*&&(gradxy[gg*N+hh])&&(cornerness[gg*N+hh]<28744.000000)*/ )
{
if(cornerness[gg*N+hh]<0)
gradxy[gg*N+hh]=0;
}
}
__global__ void kernel_memset(int *gradxy,int width,int height)
{
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
gradxy[gg*width+hh]=0;
}
}
__global__ void kernel_imgblurg_separable_1(int *gradx2,int *result,int *grady2,int *result1,int *gradxy,int *result2,int width,int height)
{
int imageW=height;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((hh<width)&&(gg<height))
{
result[hh*imageW+gg]=1*gradx2[hh*imageW+gg-3]+12*gradx2[hh*imageW+gg-2]+55*gradx2[hh*imageW+gg-1]+90*gradx2[hh*imageW+gg]+55*gradx2[hh*imageW+gg+1]+
12*gradx2[hh*imageW+gg+2]+1*gradx2[hh*imageW+gg+3];
result1[hh*imageW+gg]=1*grady2[hh*imageW+gg-3]+12*grady2[hh*imageW+gg-2]+55*grady2[hh*imageW+gg-1]+90*grady2[hh*imageW+gg]+55*grady2[hh*imageW+gg+1]+
12*grady2[hh*imageW+gg+2]+1*grady2[hh*imageW+gg+3];
result2[hh*imageW+gg]=1*gradxy[hh*imageW+gg-3]+12*gradxy[hh*imageW+gg-2]+55*gradxy[hh*imageW+gg-1]+90*gradxy[hh*imageW+gg]+55*gradxy[hh*imageW+gg+1]+
12*gradxy[hh*imageW+gg+2]+1*gradxy[hh*imageW+gg+3];
}
}
__global__ void kernel_imgblurg_separable_2(int *gradx2,int *result,int *input,int *grady2,int *result1,int *input1,int *gradxy,int *result2,int *input2,int width,int height)
{
int imageW=width;
int gg=threadIdx.x+blockIdx.x*blockDim.x;
int hh=threadIdx.y+blockIdx.y*blockDim.y;
if((gg<width)&&(hh<height))
{
if((gg>=3)&&(hh<(height-3))&&(hh>=3)&&(gg<(width-3)))
{
result[hh*imageW+gg]=norm_kernel*(1*gradx2[(hh-3)*imageW+gg]+12*gradx2[(hh-2)*imageW+gg]+55*gradx2[(hh-1)*imageW+gg]+90*gradx2[hh*imageW+gg]+55*gradx2[(hh+1)*imageW+gg]+
12*gradx2[(hh+2)*imageW+gg]+1*gradx2[(hh+3)*imageW+gg]);
result1[hh*imageW+gg]=norm_kernel*(1*grady2[(hh-3)*imageW+gg]+12*grady2[(hh-2)*imageW+gg]+55*grady2[(hh-1)*imageW+gg]+90*grady2[hh*imageW+gg]+55*grady2[(hh+1)*imageW+gg]+
12*grady2[(hh+2)*imageW+gg]+1*grady2[(hh+3)*imageW+gg]);
result2[hh*imageW+gg]=norm_kernel*(1*gradxy[(hh-3)*imageW+gg]+12*gradxy[(hh-2)*imageW+gg]+55*gradxy[(hh-1)*imageW+gg]+90*gradxy[hh*imageW+gg]+55*gradxy[(hh+1)*imageW+gg]+
12*gradxy[(hh+2)*imageW+gg]+1*gradxy[(hh+3)*imageW+gg]);
}
else{
result[hh*imageW+gg]= input[hh*imageW+gg];
result1[hh*imageW+gg]= input1[hh*imageW+gg];
result2[hh*imageW+gg]= input2[hh*imageW+gg];
}
}
}
__global__ void kernel_find_max(float *array, float *max, int *mutex, unsigned int n)
{
unsigned int index = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = gridDim.x*blockDim.x;
unsigned int offset = 0;
__shared__ float cache[256];
float temp = -1.0;
while(index + offset < n){
temp = fmaxf(temp, array[index + offset]);
offset += stride;
}
cache[threadIdx.x] = temp;
__syncthreads();
// reduction
unsigned int i = blockDim.x/2;
while(i != 0){
if(threadIdx.x < i){
cache[threadIdx.x] = fmaxf(cache[threadIdx.x], cache[threadIdx.x + i]);
}
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0){
while(atomicCAS(mutex,0,1) != 0); //lock
*max = fmaxf(*max, cache[0]);
atomicExch(mutex, 0); //unlock
}
}
__global__ void kernel_selcornerness(float *cornerness,float *selcornerness,int width, int height,int *gradxy,float *maximum,int *seirial,float RELMINTHR)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float d;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
d=cornerness[gg*N+hh];
if(d>=((*maximum)*RELMINTHR))
{
if ( (d>cornerness[(gg)*N+(hh+1)]) &&(d>=cornerness[(gg)*N+(hh-1)])&&(d>=cornerness[(gg+1)*N+(hh+1)])
&&(d>=cornerness[(gg+1)*N+(hh-1)])&&(d>cornerness[(gg-1)*N+(hh+1)] ) && (d>cornerness[(gg-1)*N+(hh-1)]) &&(d>=cornerness[(gg+1)*N+(hh)]) &&(d>cornerness[(gg-1)*N+(hh)]) )
{
atomicAdd(seirial,1);
gradxy[gg*N+hh]=1;
}
}
}
}
__global__ void kernel_cornerness(int *gradx2_b,int *grady2_b,int *gradxy_b,float *cornerness,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=5)&&(hh<(width-5))&&(gg>=5)&&(gg<(height-5)))
{
int det,trace;
float r;
int gxx,gyy,gxy;
gxx=gradx2_b[gg*N+hh];
gyy=grady2_b[gg*N+hh];
gxy=gradxy_b[gg*N+hh];
det=gxx*gyy - gxy*gxy;
trace=gxx + gyy;
r=det - 0.04*trace*trace;
if(r<0.0F) r=0.0F;
cornerness[gg*N+hh]=r;
}
}
__global__ void kernel_Ix2y2xy(int *gradx,int *grady,int *gradx2,int *grady2,int *gradxy,int width,int height)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
if((hh>=0)&&(hh<width)&&(gg>=0)&&(gg<height))
{
gradx2[gg*N+hh]= gradx[gg*N+hh]* gradx[gg*N+hh];
grady2[gg*N+hh]= grady[gg*N+hh]* grady[gg*N+hh];
gradxy[gg*N+hh]= gradx[gg*N+hh]* grady[gg*N+hh];
}
}
__global__ void kernel_imgradient5_smo(unsigned char *img,int width,int height, int *gradx2,int *grady2, int *gradx, int *grady)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
if((hh>=2)&&(hh<(width-2))&&(gg>=2)&&(gg<(height-2)))
{
int N=width;
gradx[gg*N+hh]=allnorm_kernel*(36*(img[gg*N+hh+1]-img[gg*N+hh-1]) +
18*(img[(gg+1)*N+hh+1]+img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]-img[(gg+1)*N+hh-1]) +
12*(img[(gg*N+hh+2)]-img[gg*N+hh-2]) +
6*(img[(gg+1)*N+hh+2]+img[(gg-1)*N+hh+2]-img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh-2]) +
3*(img[(gg+2)*N+hh+1]+img[(gg-2)*N+hh+1]-img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh-1]) +
1*(img[(gg+2)*N+hh+2]+img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]-img[(gg+2)*N+hh-2]));
grady[gg*N+hh] = allnorm_kernel*(36*(img[(gg+1)*N+hh]-img[(gg-1)*N+hh]) +
18*(img[(gg+1)*N+hh+1]+img[(gg+1)*N+hh-1]-img[(gg-1)*N+hh+1]-img[(gg-1)*N+hh-1]) +
12*(img[(gg+2)*N+hh]-img[(gg-2)*N+hh]) +
6*(img[(gg+2)*N+hh+1]+img[(gg+2)*N+hh-1]-img[(gg-2)*N+hh+1]-img[(gg-2)*N+hh-1]) +
3*(img[(gg+1)*N+hh+2]+img[(gg+1)*N+hh-2]-img[(gg-1)*N+hh+2]-img[(gg-1)*N+hh-2]) +
1*(img[(gg+2)*N+hh+2]+img[(gg+2)*N+hh-2]-img[(gg-2)*N+hh+2]-img[(gg-2)*N+hh-2]));
}
}
__device__ float kati(float x)
{
float xhalf;
int i;
/* compute inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
/* compute fourth root as the inverse square root of the inverse square root */
xhalf=0.5f*x;
i=*(int*)&x;
i=0x5f375a86 - (i>>1); // hidden initial guess, fast - LOMONT
x=*(float*)&i;
x=x*(1.5f-xhalf*x*x);
x=x*(1.5f-xhalf*x*x); // add this in for added precision, or many more...
return x;
}
__global__ void kernel_coordinates(float* cornerness, float (*corners)[2],int *gradxy,int width,int height,int *atom2)
{
int hh=threadIdx.x+blockIdx.x*blockDim.x;
int gg=threadIdx.y+blockIdx.y*blockDim.y;
int N=width;
float spp, spc, spn, scp, scc, scn, snp, snc, snn;
float Pxx, Pxy, Pyy, Px, Py, ucorr, vcorr, detf;
if((hh>=6)&&(hh<(width-6))&&(gg>=6)&&(gg<(height-6)))
{
if(gradxy[gg*N+hh])
{
spp=kati(cornerness[(gg-1)*N+(hh-1)]);
spc=kati(cornerness[(gg-1)*N+(hh)]);
spn=kati(cornerness[(gg-1)*N+(hh+1)]);
scp=kati(cornerness[(gg)*N+(hh-1)]);
scc=kati(cornerness[(gg)*N+(hh)]);
scn=kati(cornerness[(gg)*N+(hh+1)]);
snp=kati(cornerness[(gg+1)*N+(hh-1)]);
snc=kati(cornerness[(gg+1)*N+(hh)]);
snn=kati(cornerness[(gg+1)*N+(hh+1)]);
Pxx=(spp + scp + snp -2.0F*(spc + scc + snc) + spn + scn + snn)*ONE_THIRD_GPU;
Pxy=(spp - spn - snp + snn)*ONE_FOURTH_GPU;
Pyy= (spp + spc + spn
-2.0F*(scp + scc + scn)
+ snp + snc + snn)*ONE_THIRD_GPU;
Px=(- spp - scp - snp + spn + scn + snn)*ONE_SIXTH_GPU;
Py=(- spp - spc - spn + snp + snc + snn)*ONE_SIXTH_GPU;
detf=Pxy*Pxy - Pxx*Pyy;
if(detf>=1E-12F || detf<=-1E-12F){ // nonzero determinant
// calculate sub-pixel corrections to the corner position
ucorr=(Pyy*Px - Pxy*Py)/detf;
vcorr=(Pxx*Py - Pxy*Px)/detf;
// pull the corrections inside the pixel
// printf("a=%lf ",ucorr );
if(ucorr>0.5F) ucorr=0.5F; else if(ucorr<-0.5F) ucorr=-0.5F;
if(vcorr>0.5F) vcorr=0.5F; else if(vcorr<-0.5F) vcorr=-0.5F;
// printf("xx");
}
else
{
ucorr=vcorr=0.0F;
}
int x=atomicAdd(atom2,1);
//cornrs_big[gg*N+hh][0]=/*u0*/hh+ucorr;
//cornrs_big[gg*N+hh][1]=/*v0*/gg+vcorr;
//printf("%lf ",ucorr);
corners[x][0]=hh+ucorr;
corners[x][1]=gg+vcorr;
}
}
} | .text
.file "kernels.hip"
.globl _Z31__device_stub__kernel_warmingupv # -- Begin function _Z31__device_stub__kernel_warmingupv
.p2align 4, 0x90
.type _Z31__device_stub__kernel_warmingupv,@function
_Z31__device_stub__kernel_warmingupv: # @_Z31__device_stub__kernel_warmingupv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16kernel_warmingupv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z31__device_stub__kernel_warmingupv, .Lfunc_end0-_Z31__device_stub__kernel_warmingupv
.cfi_endproc
# -- End function
.globl _Z36__device_stub__kernel_strong_cornersPiPfii # -- Begin function _Z36__device_stub__kernel_strong_cornersPiPfii
.p2align 4, 0x90
.type _Z36__device_stub__kernel_strong_cornersPiPfii,@function
_Z36__device_stub__kernel_strong_cornersPiPfii: # @_Z36__device_stub__kernel_strong_cornersPiPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernel_strong_cornersPiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z36__device_stub__kernel_strong_cornersPiPfii, .Lfunc_end1-_Z36__device_stub__kernel_strong_cornersPiPfii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_memsetPiii # -- Begin function _Z28__device_stub__kernel_memsetPiii
.p2align 4, 0x90
.type _Z28__device_stub__kernel_memsetPiii,@function
_Z28__device_stub__kernel_memsetPiii: # @_Z28__device_stub__kernel_memsetPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_memsetPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_memsetPiii, .Lfunc_end2-_Z28__device_stub__kernel_memsetPiii
.cfi_endproc
# -- End function
.globl _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii # -- Begin function _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii,@function
_Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii: # @_Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii, .Lfunc_end3-_Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii # -- Begin function _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.p2align 4, 0x90
.type _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii,@function
_Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii: # @_Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end4:
.size _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, .Lfunc_end4-_Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernel_find_maxPfS_Pij # -- Begin function _Z30__device_stub__kernel_find_maxPfS_Pij
.p2align 4, 0x90
.type _Z30__device_stub__kernel_find_maxPfS_Pij,@function
_Z30__device_stub__kernel_find_maxPfS_Pij: # @_Z30__device_stub__kernel_find_maxPfS_Pij
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kernel_find_maxPfS_Pij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z30__device_stub__kernel_find_maxPfS_Pij, .Lfunc_end5-_Z30__device_stub__kernel_find_maxPfS_Pij
.cfi_endproc
# -- End function
.globl _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f # -- Begin function _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f
.p2align 4, 0x90
.type _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f,@function
_Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f: # @_Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20kernel_selcornernessPfS_iiPiS_S0_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end6:
.size _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f, .Lfunc_end6-_Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f
.cfi_endproc
# -- End function
.globl _Z32__device_stub__kernel_cornernessPiS_S_Pfii # -- Begin function _Z32__device_stub__kernel_cornernessPiS_S_Pfii
.p2align 4, 0x90
.type _Z32__device_stub__kernel_cornernessPiS_S_Pfii,@function
_Z32__device_stub__kernel_cornernessPiS_S_Pfii: # @_Z32__device_stub__kernel_cornernessPiS_S_Pfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17kernel_cornernessPiS_S_Pfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end7:
.size _Z32__device_stub__kernel_cornernessPiS_S_Pfii, .Lfunc_end7-_Z32__device_stub__kernel_cornernessPiS_S_Pfii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii # -- Begin function _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii,@function
_Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii: # @_Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14kernel_Ix2y2xyPiS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end8:
.size _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii, .Lfunc_end8-_Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_ # -- Begin function _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_
.p2align 4, 0x90
.type _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_,@function
_Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_: # @_Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_, .Lfunc_end9-_Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_ # -- Begin function _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_
.p2align 4, 0x90
.type _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_,@function
_Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_: # @_Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernel_coordinatesPfPA2_fPiiiS2_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end10:
.size _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_, .Lfunc_end10-_Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_warmingupv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernel_strong_cornersPiPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_memsetPiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_find_maxPfS_Pij, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kernel_selcornernessPfS_iiPiS_S0_f, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_cornernessPiS_S_Pfii, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_Ix2y2xyPiS_S_S_S_ii, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_coordinatesPfPA2_fPiiiS2_, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kernel_warmingupv,@object # @_Z16kernel_warmingupv
.section .rodata,"a",@progbits
.globl _Z16kernel_warmingupv
.p2align 3, 0x0
_Z16kernel_warmingupv:
.quad _Z31__device_stub__kernel_warmingupv
.size _Z16kernel_warmingupv, 8
.type _Z21kernel_strong_cornersPiPfii,@object # @_Z21kernel_strong_cornersPiPfii
.globl _Z21kernel_strong_cornersPiPfii
.p2align 3, 0x0
_Z21kernel_strong_cornersPiPfii:
.quad _Z36__device_stub__kernel_strong_cornersPiPfii
.size _Z21kernel_strong_cornersPiPfii, 8
.type _Z13kernel_memsetPiii,@object # @_Z13kernel_memsetPiii
.globl _Z13kernel_memsetPiii
.p2align 3, 0x0
_Z13kernel_memsetPiii:
.quad _Z28__device_stub__kernel_memsetPiii
.size _Z13kernel_memsetPiii, 8
.type _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii,@object # @_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.globl _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.p2align 3, 0x0
_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii:
.quad _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.size _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii, 8
.type _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii,@object # @_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.globl _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.p2align 3, 0x0
_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii:
.quad _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.size _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii, 8
.type _Z15kernel_find_maxPfS_Pij,@object # @_Z15kernel_find_maxPfS_Pij
.globl _Z15kernel_find_maxPfS_Pij
.p2align 3, 0x0
_Z15kernel_find_maxPfS_Pij:
.quad _Z30__device_stub__kernel_find_maxPfS_Pij
.size _Z15kernel_find_maxPfS_Pij, 8
.type _Z20kernel_selcornernessPfS_iiPiS_S0_f,@object # @_Z20kernel_selcornernessPfS_iiPiS_S0_f
.globl _Z20kernel_selcornernessPfS_iiPiS_S0_f
.p2align 3, 0x0
_Z20kernel_selcornernessPfS_iiPiS_S0_f:
.quad _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f
.size _Z20kernel_selcornernessPfS_iiPiS_S0_f, 8
.type _Z17kernel_cornernessPiS_S_Pfii,@object # @_Z17kernel_cornernessPiS_S_Pfii
.globl _Z17kernel_cornernessPiS_S_Pfii
.p2align 3, 0x0
_Z17kernel_cornernessPiS_S_Pfii:
.quad _Z32__device_stub__kernel_cornernessPiS_S_Pfii
.size _Z17kernel_cornernessPiS_S_Pfii, 8
.type _Z14kernel_Ix2y2xyPiS_S_S_S_ii,@object # @_Z14kernel_Ix2y2xyPiS_S_S_S_ii
.globl _Z14kernel_Ix2y2xyPiS_S_S_S_ii
.p2align 3, 0x0
_Z14kernel_Ix2y2xyPiS_S_S_S_ii:
.quad _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii
.size _Z14kernel_Ix2y2xyPiS_S_S_S_ii, 8
.type _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_,@object # @_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_
.globl _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_
.p2align 3, 0x0
_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_:
.quad _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_
.size _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_, 8
.type _Z18kernel_coordinatesPfPA2_fPiiiS2_,@object # @_Z18kernel_coordinatesPfPA2_fPiiiS2_
.globl _Z18kernel_coordinatesPfPA2_fPiiiS2_
.p2align 3, 0x0
_Z18kernel_coordinatesPfPA2_fPiiiS2_:
.quad _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_
.size _Z18kernel_coordinatesPfPA2_fPiiiS2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16kernel_warmingupv"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21kernel_strong_cornersPiPfii"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13kernel_memsetPiii"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii"
.size .L__unnamed_4, 46
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii"
.size .L__unnamed_5, 52
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z15kernel_find_maxPfS_Pij"
.size .L__unnamed_6, 27
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z20kernel_selcornernessPfS_iiPiS_S0_f"
.size .L__unnamed_7, 39
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z17kernel_cornernessPiS_S_Pfii"
.size .L__unnamed_8, 32
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z14kernel_Ix2y2xyPiS_S_S_S_ii"
.size .L__unnamed_9, 31
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_"
.size .L__unnamed_10, 42
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z18kernel_coordinatesPfPA2_fPiiiS2_"
.size .L__unnamed_11, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernel_warmingupv
.addrsig_sym _Z36__device_stub__kernel_strong_cornersPiPfii
.addrsig_sym _Z28__device_stub__kernel_memsetPiii
.addrsig_sym _Z42__device_stub__kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.addrsig_sym _Z42__device_stub__kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.addrsig_sym _Z30__device_stub__kernel_find_maxPfS_Pij
.addrsig_sym _Z35__device_stub__kernel_selcornernessPfS_iiPiS_S0_f
.addrsig_sym _Z32__device_stub__kernel_cornernessPiS_S_Pfii
.addrsig_sym _Z29__device_stub__kernel_Ix2y2xyPiS_S_S_S_ii
.addrsig_sym _Z37__device_stub__kernel_imgradient5_smoPhiiPiS0_S0_S0_
.addrsig_sym _Z33__device_stub__kernel_coordinatesPfPA2_fPiiiS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernel_warmingupv
.addrsig_sym _Z21kernel_strong_cornersPiPfii
.addrsig_sym _Z13kernel_memsetPiii
.addrsig_sym _Z27kernel_imgblurg_separable_1PiS_S_S_S_S_ii
.addrsig_sym _Z27kernel_imgblurg_separable_2PiS_S_S_S_S_S_S_S_ii
.addrsig_sym _Z15kernel_find_maxPfS_Pij
.addrsig_sym _Z20kernel_selcornernessPfS_iiPiS_S0_f
.addrsig_sym _Z17kernel_cornernessPiS_S_Pfii
.addrsig_sym _Z14kernel_Ix2y2xyPiS_S_S_S_ii
.addrsig_sym _Z22kernel_imgradient5_smoPhiiPiS0_S0_S0_
.addrsig_sym _Z18kernel_coordinatesPfPA2_fPiiiS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&dev_newA, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
cudaMemcpy( new_a, dev_newA, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} | code for sm_80
Function : _Z6vecIncPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x3e7, PT ; /* 0x000003e70600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMNMX R3, R6.reuse, 0x2e8, !PT ; /* 0x000002e806037817 */
/* 0x040fe20007800200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BSSY B0, 0x220 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*0070*/ IADD3 R3, -R6, 0xff, R3 ; /* 0x000000ff06037810 */
/* 0x000fc80007ffe103 */
/*0080*/ LEA.HI R0, R3.reuse, 0x1, RZ, 0x18 ; /* 0x0000000103007811 */
/* 0x040fe400078fc0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, 0x300, PT ; /* 0x000003000300780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fda000782c0ff */
/*00b0*/ @!P1 BRA 0x210 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0004 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0150*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0160*/ IADD3 R4, P3, R4, 0x400, RZ ; /* 0x0000040004047810 */
/* 0x000fe40007f7e0ff */
/*0170*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0180*/ IADD3 R6, R6, 0x100, RZ ; /* 0x0000010006067810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0009 */
/*01b0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x004fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*01d0*/ IADD3 R8, P2, R8, 0x400, RZ ; /* 0x0000040008087810 */
/* 0x000fc80007f5e0ff */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*01f0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0200*/ @P1 BRA 0x120 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R0, R6, -0x400, RZ ; /* 0xfffffc0006007810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe200078e00ff */
/*0250*/ BSSY B0, 0x6c0 ; /* 0x0000046000007945 */
/* 0x000fe40003800000 */
/*0260*/ IADD3 R5, -R0, -0x18, RZ ; /* 0xffffffe800057810 */
/* 0x000fe20007ffe1ff */
/*0270*/ IMAD.WIDE R2, R6, R3, c[0x2][0x0] ; /* 0x0080000006027625 */
/* 0x000fc600078e0203 */
/*0280*/ ISETP.GT.AND P1, PT, R5, 0xc00, PT ; /* 0x00000c000500780c */
/* 0x000fe40003f24270 */
/*0290*/ IADD3 R4, P0, R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f1e0ff */
/*02a0*/ IADD3 R2, P2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3.X R5, R3.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x040fe400007fe4ff */
/*02c0*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe400017fe4ff */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*02e0*/ @!P1 BRA 0x6b0 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0e170 */
/*0300*/ LDG.E R6, [R4.64+-0x800] ; /* 0xfff8000404067981 */
/* 0x000ea4000c1e1900 */
/*0310*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x004fca0007ffe0ff */
/*0320*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R6, [R4.64+-0x400] ; /* 0xfffc000404067981 */
/* 0x000ea4000c1e1900 */
/*0340*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x004fca0007ffe0ff */
/*0350*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x0003e8000c101904 */
/*0360*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0370*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0380*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0390*/ LDG.E R6, [R4.64+0x400] ; /* 0x0004000404067981 */
/* 0x000ee4000c1e1900 */
/*03a0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*03b0*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x0007e8000c101904 */
/*03c0*/ LDG.E R6, [R4.64+0x800] ; /* 0x0008000404067981 */
/* 0x000e24000c1e1900 */
/*03d0*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*03e0*/ STG.E [R2.64+0x800], R7 ; /* 0x0008000702007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R6, [R4.64+0xc00] ; /* 0x000c000404067981 */
/* 0x000e64000c1e1900 */
/*0400*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0410*/ STG.E [R2.64+0xc00], R9 ; /* 0x000c000902007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R6, [R4.64+0x1000] ; /* 0x0010000404067981 */
/* 0x000ea4000c1e1900 */
/*0430*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R2.64+0x1000], R11 ; /* 0x0010000b02007986 */
/* 0x0005e8000c101904 */
/*0450*/ LDG.E R6, [R4.64+0x1400] ; /* 0x0014000404067981 */
/* 0x000ee4000c1e1900 */
/*0460*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*0470*/ STG.E [R2.64+0x1400], R13 ; /* 0x0014000d02007986 */
/* 0x0007e8000c101904 */
/*0480*/ LDG.E R6, [R4.64+0x1800] ; /* 0x0018000404067981 */
/* 0x000e24000c1e1900 */
/*0490*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*04a0*/ STG.E [R2.64+0x1800], R7 ; /* 0x0018000702007986 */
/* 0x0001e8000c101904 */
/*04b0*/ LDG.E R6, [R4.64+0x1c00] ; /* 0x001c000404067981 */
/* 0x000e64000c1e1900 */
/*04c0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*04d0*/ STG.E [R2.64+0x1c00], R9 ; /* 0x001c000902007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R6, [R4.64+0x2000] ; /* 0x0020000404067981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0500*/ STG.E [R2.64+0x2000], R11 ; /* 0x0020000b02007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R6, [R4.64+0x2400] ; /* 0x0024000404067981 */
/* 0x000ee4000c1e1900 */
/*0520*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*0530*/ STG.E [R2.64+0x2400], R13 ; /* 0x0024000d02007986 */
/* 0x000fe8000c101904 */
/*0540*/ LDG.E R6, [R4.64+0x2800] ; /* 0x0028000404067981 */
/* 0x000e24000c1e1900 */
/*0550*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*0560*/ STG.E [R2.64+0x2800], R7 ; /* 0x0028000702007986 */
/* 0x000fe8000c101904 */
/*0570*/ LDG.E R6, [R4.64+0x2c00] ; /* 0x002c000404067981 */
/* 0x000e64000c1e1900 */
/*0580*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0590*/ STG.E [R2.64+0x2c00], R9 ; /* 0x002c000902007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R6, [R4.64+0x3000] ; /* 0x0030000404067981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R0, R0, 0x1000, RZ ; /* 0x0000100000007810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*05d0*/ STG.E [R2.64+0x3000], R11 ; /* 0x0030000b02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ LDG.E R6, [R4.64+0x3400] ; /* 0x0034000404067981 */
/* 0x0002a2000c1e1900 */
/*05f0*/ ISETP.GE.AND P1, PT, R0, -0xc18, PT ; /* 0xfffff3e80000780c */
/* 0x000fe40003f26270 */
/*0600*/ IADD3 R8, P2, R4, 0x4000, RZ ; /* 0x0000400004087810 */
/* 0x000fca0007f5e0ff */
/*0610*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x001fe400010e0605 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0640*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x004fe40007ffe0ff */
/*0650*/ IADD3 R6, P3, R2, 0x4000, RZ ; /* 0x0000400002067810 */
/* 0x000fc60007f7e0ff */
/*0660*/ STG.E [R2.64+0x3400], R13 ; /* 0x0034000d02007986 */
/* 0x0001e4000c101904 */
/*0670*/ IMAD.X R7, RZ, RZ, R3, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0603 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0690*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*06a0*/ @!P1 BRA 0x300 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R6, -R0, -0x18, RZ ; /* 0xffffffe800067810 */
/* 0x000fe20007ffe1ff */
/*06d0*/ BSSY B0, 0x930 ; /* 0x0000025000007945 */
/* 0x000fe60003800000 */
/*06e0*/ ISETP.GT.AND P1, PT, R6, 0x400, PT ; /* 0x000004000600780c */
/* 0x000fda0003f24270 */
/*06f0*/ @!P1 BRA 0x920 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R6, [R4.64+-0x800] ; /* 0xfff8000404067981 */
/* 0x000ea4000c1e1900 */
/*0710*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x004fca0007ffe0ff */
/*0720*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x0001e8000c101904 */
/*0730*/ LDG.E R6, [R4.64+-0x400] ; /* 0xfffc000404067981 */
/* 0x000ea4000c1e1900 */
/*0740*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x004fca0007ffe0ff */
/*0750*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x0003e8000c101904 */
/*0760*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0770*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0780*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0790*/ LDG.E R6, [R4.64+0x400] ; /* 0x0004000404067981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*07b0*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x0007e8000c101904 */
/*07c0*/ LDG.E R6, [R4.64+0x800] ; /* 0x0008000404067981 */
/* 0x000e24000c1e1900 */
/*07d0*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*07e0*/ STG.E [R2.64+0x800], R7 ; /* 0x0008000702007986 */
/* 0x0001e8000c101904 */
/*07f0*/ LDG.E R6, [R4.64+0xc00] ; /* 0x000c000404067981 */
/* 0x000e64000c1e1900 */
/*0800*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0810*/ STG.E [R2.64+0xc00], R9 ; /* 0x000c000902007986 */
/* 0x000fe8000c101904 */
/*0820*/ LDG.E R6, [R4.64+0x1000] ; /* 0x0010000404067981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0840*/ STG.E [R2.64+0x1000], R11 ; /* 0x0010000b02007986 */
/* 0x000fe8000c101904 */
/*0850*/ LDG.E R6, [R4.64+0x1400] ; /* 0x0014000404067981 */
/* 0x0002e2000c1e1900 */
/*0860*/ IADD3 R8, P1, R4, 0x2000, RZ ; /* 0x0000200004087810 */
/* 0x000fe40007f3e0ff */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0880*/ IADD3 R0, R0, 0x800, RZ ; /* 0x0000080000007810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.X R15, RZ, RZ, R5, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fc400008e0605 */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000f */
/*08c0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fe40007ffe0ff */
/*08d0*/ IADD3 R6, P2, R2, 0x2000, RZ ; /* 0x0000200002067810 */
/* 0x000fc60007f5e0ff */
/*08e0*/ STG.E [R2.64+0x1400], R13 ; /* 0x0014000d02007986 */
/* 0x0003e4000c101904 */
/*08f0*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0603 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x002fe400078e0006 */
/*0910*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.LT.OR P0, PT, R0, -0x18, P0 ; /* 0xffffffe80000780c */
/* 0x000fda0000701670 */
/*0940*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R0, [R4.64+-0x800] ; /* 0xfff8000404007981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x004fca0007ffe0ff */
/*0970*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x000fe8000c101904 */
/*0980*/ LDG.E R0, [R4.64+-0x400] ; /* 0xfffc000404007981 */
/* 0x000ea4000c1e1900 */
/*0990*/ IADD3 R9, R0, 0x1, RZ ; /* 0x0000000100097810 */
/* 0x004fca0007ffe0ff */
/*09a0*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x000fe8000c101904 */
/*09b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ IADD3 R11, R0, 0x1, RZ ; /* 0x00000001000b7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*09e0*/ LDG.E R0, [R4.64+0x400] ; /* 0x0004000404007981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x004fca0007ffe0ff */
/*0a00*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&dev_newA, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
cudaMemcpy( new_a, dev_newA, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} | .file "tmpxft_00126f21_00000000-6_vecInc2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6vecIncPiS_PiS_
.type _Z27__device_stub__Z6vecIncPiS_PiS_, @function
_Z27__device_stub__Z6vecIncPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vecIncPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6vecIncPiS_PiS_, .-_Z27__device_stub__Z6vecIncPiS_PiS_
.globl _Z6vecIncPiS_
.type _Z6vecIncPiS_, @function
_Z6vecIncPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6vecIncPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecIncPiS_, .-_Z6vecIncPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Original A array\n"
.LC1:
.string "%d "
.LC2:
.string "\nNew A array \n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $3968, %rsp
.cfi_def_cfa_offset 8096
movq %fs:40, %rax
movq %rax, 8056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 4048(%rsp), %r12
leaq .LC1(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 4048(%rsp), %rbx
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8048(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8056(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $8064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6vecIncPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6vecIncPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecIncPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA, size);
cudaMalloc( (void**)&dev_newA, size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
cudaMemcpy( new_a, dev_newA, size, cudaMemcpyDeviceToHost);
cudaFree( devA);
cudaFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&dev_newA, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
hipMemcpy( new_a, dev_newA, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&dev_newA, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
hipMemcpy( new_a, dev_newA, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecIncPiS_
.globl _Z6vecIncPiS_
.p2align 8
.type _Z6vecIncPiS_,@function
_Z6vecIncPiS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_add_nc_u32_e32 v4, 0xffffff00, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
global_load_b32 v5, v[0:1], off
v_add_nc_u32_e32 v4, 0x100, v4
v_add_co_u32 v0, vcc_lo, v0, 0x400
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 0x2e7, v4
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 1, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, 0x400
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecIncPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecIncPiS_, .Lfunc_end0-_Z6vecIncPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecIncPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6vecIncPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1000
#define T 256
__global__ void vecInc(int *A,int *newA){
int i;
for (i = threadIdx.x;i < N;i = i + T){
newA[i] = A[i] + 1;
}
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof ( int);
int a[N], new_a[N], *devA, *dev_newA;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = rand() % 100;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA, size);
hipMalloc( (void**)&dev_newA, size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecInc<<<1, T>>>(devA, dev_newA);
hipMemcpy( new_a, dev_newA, size, hipMemcpyDeviceToHost);
hipFree( devA);
hipFree( dev_newA);
printf("\nNew A array \n");
for (i= 0; i < N; i++){
printf("%d ",new_a[i]);
}
printf("\n");
} | .text
.file "vecInc2.hip"
.globl _Z21__device_stub__vecIncPiS_ # -- Begin function _Z21__device_stub__vecIncPiS_
.p2align 4, 0x90
.type _Z21__device_stub__vecIncPiS_,@function
_Z21__device_stub__vecIncPiS_: # @_Z21__device_stub__vecIncPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vecIncPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vecIncPiS_, .Lfunc_end0-_Z21__device_stub__vecIncPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $8080, %rsp # imm = 0x1F90
.cfi_def_cfa_offset 8096
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1374389535, %rsi, %rax # imm = 0x51EB851F
movq %rax, %rcx
shrq $63, %rcx
sarq $37, %rax
addl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %esi
movl %esi, 4080(%rsp,%rbx,4)
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1000, %rbx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4080(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecIncPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1000, %rbx # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $8080, %rsp # imm = 0x1F90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecIncPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecIncPiS_,@object # @_Z6vecIncPiS_
.section .rodata,"a",@progbits
.globl _Z6vecIncPiS_
.p2align 3, 0x0
_Z6vecIncPiS_:
.quad _Z21__device_stub__vecIncPiS_
.size _Z6vecIncPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecIncPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original A array"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nNew A array "
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecIncPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecIncPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecIncPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x3e7, PT ; /* 0x000003e70600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMNMX R3, R6.reuse, 0x2e8, !PT ; /* 0x000002e806037817 */
/* 0x040fe20007800200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BSSY B0, 0x220 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*0070*/ IADD3 R3, -R6, 0xff, R3 ; /* 0x000000ff06037810 */
/* 0x000fc80007ffe103 */
/*0080*/ LEA.HI R0, R3.reuse, 0x1, RZ, 0x18 ; /* 0x0000000103007811 */
/* 0x040fe400078fc0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, 0x300, PT ; /* 0x000003000300780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fda000782c0ff */
/*00b0*/ @!P1 BRA 0x210 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0004 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0150*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0160*/ IADD3 R4, P3, R4, 0x400, RZ ; /* 0x0000040004047810 */
/* 0x000fe40007f7e0ff */
/*0170*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0180*/ IADD3 R6, R6, 0x100, RZ ; /* 0x0000010006067810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0009 */
/*01b0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x004fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*01d0*/ IADD3 R8, P2, R8, 0x400, RZ ; /* 0x0000040008087810 */
/* 0x000fc80007f5e0ff */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*01f0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0200*/ @P1 BRA 0x120 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R0, R6, -0x400, RZ ; /* 0xfffffc0006007810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe200078e00ff */
/*0250*/ BSSY B0, 0x6c0 ; /* 0x0000046000007945 */
/* 0x000fe40003800000 */
/*0260*/ IADD3 R5, -R0, -0x18, RZ ; /* 0xffffffe800057810 */
/* 0x000fe20007ffe1ff */
/*0270*/ IMAD.WIDE R2, R6, R3, c[0x2][0x0] ; /* 0x0080000006027625 */
/* 0x000fc600078e0203 */
/*0280*/ ISETP.GT.AND P1, PT, R5, 0xc00, PT ; /* 0x00000c000500780c */
/* 0x000fe40003f24270 */
/*0290*/ IADD3 R4, P0, R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f1e0ff */
/*02a0*/ IADD3 R2, P2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3.X R5, R3.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x040fe400007fe4ff */
/*02c0*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe400017fe4ff */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*02e0*/ @!P1 BRA 0x6b0 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0e170 */
/*0300*/ LDG.E R6, [R4.64+-0x800] ; /* 0xfff8000404067981 */
/* 0x000ea4000c1e1900 */
/*0310*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x004fca0007ffe0ff */
/*0320*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R6, [R4.64+-0x400] ; /* 0xfffc000404067981 */
/* 0x000ea4000c1e1900 */
/*0340*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x004fca0007ffe0ff */
/*0350*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x0003e8000c101904 */
/*0360*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0370*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0380*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0390*/ LDG.E R6, [R4.64+0x400] ; /* 0x0004000404067981 */
/* 0x000ee4000c1e1900 */
/*03a0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*03b0*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x0007e8000c101904 */
/*03c0*/ LDG.E R6, [R4.64+0x800] ; /* 0x0008000404067981 */
/* 0x000e24000c1e1900 */
/*03d0*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*03e0*/ STG.E [R2.64+0x800], R7 ; /* 0x0008000702007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R6, [R4.64+0xc00] ; /* 0x000c000404067981 */
/* 0x000e64000c1e1900 */
/*0400*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0410*/ STG.E [R2.64+0xc00], R9 ; /* 0x000c000902007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R6, [R4.64+0x1000] ; /* 0x0010000404067981 */
/* 0x000ea4000c1e1900 */
/*0430*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R2.64+0x1000], R11 ; /* 0x0010000b02007986 */
/* 0x0005e8000c101904 */
/*0450*/ LDG.E R6, [R4.64+0x1400] ; /* 0x0014000404067981 */
/* 0x000ee4000c1e1900 */
/*0460*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*0470*/ STG.E [R2.64+0x1400], R13 ; /* 0x0014000d02007986 */
/* 0x0007e8000c101904 */
/*0480*/ LDG.E R6, [R4.64+0x1800] ; /* 0x0018000404067981 */
/* 0x000e24000c1e1900 */
/*0490*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*04a0*/ STG.E [R2.64+0x1800], R7 ; /* 0x0018000702007986 */
/* 0x0001e8000c101904 */
/*04b0*/ LDG.E R6, [R4.64+0x1c00] ; /* 0x001c000404067981 */
/* 0x000e64000c1e1900 */
/*04c0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*04d0*/ STG.E [R2.64+0x1c00], R9 ; /* 0x001c000902007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R6, [R4.64+0x2000] ; /* 0x0020000404067981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0500*/ STG.E [R2.64+0x2000], R11 ; /* 0x0020000b02007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R6, [R4.64+0x2400] ; /* 0x0024000404067981 */
/* 0x000ee4000c1e1900 */
/*0520*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*0530*/ STG.E [R2.64+0x2400], R13 ; /* 0x0024000d02007986 */
/* 0x000fe8000c101904 */
/*0540*/ LDG.E R6, [R4.64+0x2800] ; /* 0x0028000404067981 */
/* 0x000e24000c1e1900 */
/*0550*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*0560*/ STG.E [R2.64+0x2800], R7 ; /* 0x0028000702007986 */
/* 0x000fe8000c101904 */
/*0570*/ LDG.E R6, [R4.64+0x2c00] ; /* 0x002c000404067981 */
/* 0x000e64000c1e1900 */
/*0580*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0590*/ STG.E [R2.64+0x2c00], R9 ; /* 0x002c000902007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R6, [R4.64+0x3000] ; /* 0x0030000404067981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R0, R0, 0x1000, RZ ; /* 0x0000100000007810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*05d0*/ STG.E [R2.64+0x3000], R11 ; /* 0x0030000b02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ LDG.E R6, [R4.64+0x3400] ; /* 0x0034000404067981 */
/* 0x0002a2000c1e1900 */
/*05f0*/ ISETP.GE.AND P1, PT, R0, -0xc18, PT ; /* 0xfffff3e80000780c */
/* 0x000fe40003f26270 */
/*0600*/ IADD3 R8, P2, R4, 0x4000, RZ ; /* 0x0000400004087810 */
/* 0x000fca0007f5e0ff */
/*0610*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x001fe400010e0605 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0640*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x004fe40007ffe0ff */
/*0650*/ IADD3 R6, P3, R2, 0x4000, RZ ; /* 0x0000400002067810 */
/* 0x000fc60007f7e0ff */
/*0660*/ STG.E [R2.64+0x3400], R13 ; /* 0x0034000d02007986 */
/* 0x0001e4000c101904 */
/*0670*/ IMAD.X R7, RZ, RZ, R3, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0603 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0690*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*06a0*/ @!P1 BRA 0x300 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R6, -R0, -0x18, RZ ; /* 0xffffffe800067810 */
/* 0x000fe20007ffe1ff */
/*06d0*/ BSSY B0, 0x930 ; /* 0x0000025000007945 */
/* 0x000fe60003800000 */
/*06e0*/ ISETP.GT.AND P1, PT, R6, 0x400, PT ; /* 0x000004000600780c */
/* 0x000fda0003f24270 */
/*06f0*/ @!P1 BRA 0x920 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R6, [R4.64+-0x800] ; /* 0xfff8000404067981 */
/* 0x000ea4000c1e1900 */
/*0710*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x004fca0007ffe0ff */
/*0720*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x0001e8000c101904 */
/*0730*/ LDG.E R6, [R4.64+-0x400] ; /* 0xfffc000404067981 */
/* 0x000ea4000c1e1900 */
/*0740*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x004fca0007ffe0ff */
/*0750*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x0003e8000c101904 */
/*0760*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0770*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0780*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0790*/ LDG.E R6, [R4.64+0x400] ; /* 0x0004000404067981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fca0007ffe0ff */
/*07b0*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x0007e8000c101904 */
/*07c0*/ LDG.E R6, [R4.64+0x800] ; /* 0x0008000404067981 */
/* 0x000e24000c1e1900 */
/*07d0*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fca0007ffe0ff */
/*07e0*/ STG.E [R2.64+0x800], R7 ; /* 0x0008000702007986 */
/* 0x0001e8000c101904 */
/*07f0*/ LDG.E R6, [R4.64+0xc00] ; /* 0x000c000404067981 */
/* 0x000e64000c1e1900 */
/*0800*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x002fca0007ffe0ff */
/*0810*/ STG.E [R2.64+0xc00], R9 ; /* 0x000c000902007986 */
/* 0x000fe8000c101904 */
/*0820*/ LDG.E R6, [R4.64+0x1000] ; /* 0x0010000404067981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IADD3 R11, R6, 0x1, RZ ; /* 0x00000001060b7810 */
/* 0x004fca0007ffe0ff */
/*0840*/ STG.E [R2.64+0x1000], R11 ; /* 0x0010000b02007986 */
/* 0x000fe8000c101904 */
/*0850*/ LDG.E R6, [R4.64+0x1400] ; /* 0x0014000404067981 */
/* 0x0002e2000c1e1900 */
/*0860*/ IADD3 R8, P1, R4, 0x2000, RZ ; /* 0x0000200004087810 */
/* 0x000fe40007f3e0ff */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0880*/ IADD3 R0, R0, 0x800, RZ ; /* 0x0000080000007810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.X R15, RZ, RZ, R5, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fc400008e0605 */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000f */
/*08c0*/ IADD3 R13, R6, 0x1, RZ ; /* 0x00000001060d7810 */
/* 0x008fe40007ffe0ff */
/*08d0*/ IADD3 R6, P2, R2, 0x2000, RZ ; /* 0x0000200002067810 */
/* 0x000fc60007f5e0ff */
/*08e0*/ STG.E [R2.64+0x1400], R13 ; /* 0x0014000d02007986 */
/* 0x0003e4000c101904 */
/*08f0*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0603 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x002fe400078e0006 */
/*0910*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.LT.OR P0, PT, R0, -0x18, P0 ; /* 0xffffffe80000780c */
/* 0x000fda0000701670 */
/*0940*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R0, [R4.64+-0x800] ; /* 0xfff8000404007981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x004fca0007ffe0ff */
/*0970*/ STG.E [R2.64+-0x800], R7 ; /* 0xfff8000702007986 */
/* 0x000fe8000c101904 */
/*0980*/ LDG.E R0, [R4.64+-0x400] ; /* 0xfffc000404007981 */
/* 0x000ea4000c1e1900 */
/*0990*/ IADD3 R9, R0, 0x1, RZ ; /* 0x0000000100097810 */
/* 0x004fca0007ffe0ff */
/*09a0*/ STG.E [R2.64+-0x400], R9 ; /* 0xfffc000902007986 */
/* 0x000fe8000c101904 */
/*09b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ IADD3 R11, R0, 0x1, RZ ; /* 0x00000001000b7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*09e0*/ LDG.E R0, [R4.64+0x400] ; /* 0x0004000404007981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x004fca0007ffe0ff */
/*0a00*/ STG.E [R2.64+0x400], R13 ; /* 0x0004000d02007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecIncPiS_
.globl _Z6vecIncPiS_
.p2align 8
.type _Z6vecIncPiS_,@function
_Z6vecIncPiS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_add_nc_u32_e32 v4, 0xffffff00, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v2
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
global_load_b32 v5, v[0:1], off
v_add_nc_u32_e32 v4, 0x100, v4
v_add_co_u32 v0, vcc_lo, v0, 0x400
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 0x2e7, v4
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 1, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, 0x400
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecIncPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecIncPiS_, .Lfunc_end0-_Z6vecIncPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecIncPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6vecIncPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00126f21_00000000-6_vecInc2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6vecIncPiS_PiS_
.type _Z27__device_stub__Z6vecIncPiS_PiS_, @function
_Z27__device_stub__Z6vecIncPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vecIncPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6vecIncPiS_PiS_, .-_Z27__device_stub__Z6vecIncPiS_PiS_
.globl _Z6vecIncPiS_
.type _Z6vecIncPiS_, @function
_Z6vecIncPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6vecIncPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecIncPiS_, .-_Z6vecIncPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Original A array\n"
.LC1:
.string "%d "
.LC2:
.string "\nNew A array \n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $3968, %rsp
.cfi_def_cfa_offset 8096
movq %fs:40, %rax
movq %rax, 8056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 4048(%rsp), %r12
leaq .LC1(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 4048(%rsp), %rbx
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8048(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8056(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $8064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6vecIncPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6vecIncPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecIncPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecInc2.hip"
.globl _Z21__device_stub__vecIncPiS_ # -- Begin function _Z21__device_stub__vecIncPiS_
.p2align 4, 0x90
.type _Z21__device_stub__vecIncPiS_,@function
_Z21__device_stub__vecIncPiS_: # @_Z21__device_stub__vecIncPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vecIncPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vecIncPiS_, .Lfunc_end0-_Z21__device_stub__vecIncPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $8080, %rsp # imm = 0x1F90
.cfi_def_cfa_offset 8096
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1374389535, %rsi, %rax # imm = 0x51EB851F
movq %rax, %rcx
shrq $63, %rcx
sarq $37, %rax
addl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %esi
movl %esi, 4080(%rsp,%rbx,4)
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1000, %rbx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4080(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecIncPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1000, %rbx # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $8080, %rsp # imm = 0x1F90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecIncPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecIncPiS_,@object # @_Z6vecIncPiS_
.section .rodata,"a",@progbits
.globl _Z6vecIncPiS_
.p2align 3, 0x0
_Z6vecIncPiS_:
.quad _Z21__device_stub__vecIncPiS_
.size _Z6vecIncPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecIncPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original A array"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nNew A array "
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecIncPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecIncPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} | code for sm_80
Function : _Z19applyGaussianFilterPhS_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe4000001ff00 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x180], RZ, 0x1 ; /* 0x0000600000007a11 */
/* 0x000fe200078f08ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e260000002100 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011400 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0090*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fe400078e0202 */
/*00d0*/ IMAD R2, R4, c[0x0][0x4], R5 ; /* 0x0000010004027a24 */
/* 0x002fd400078e0205 */
/*00e0*/ @!P0 BRA 0x800 ; /* 0x0000071000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe20007ffe1ff */
/*0100*/ IMAD.SHL.U32 R22, R0, 0x2, RZ ; /* 0x0000000200167824 */
/* 0x000fe200078e00ff */
/*0110*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.IADD R5, R3.reuse, 0x1, -R0 ; /* 0x0000000103057824 */
/* 0x040fe400078e0a00 */
/*0130*/ IMAD.IADD R8, R3, 0x1, R4 ; /* 0x0000000103087824 */
/* 0x000fe200078e0204 */
/*0140*/ IADD3 R6, R22, 0x1, RZ ; /* 0x0000000116067810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe40003f46270 */
/*0160*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fc40007ffe0ff */
/*0170*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe40003f06270 */
/*0180*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*0190*/ ISETP.GE.AND P1, PT, R9.reuse, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x040fe40003f26270 */
/*01a0*/ ISETP.LT.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000701670 */
/*01b0*/ ISETP.NE.AND P4, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f85270 */
/*01c0*/ ISETP.LT.OR P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fc40000f21670 */
/*01d0*/ ISETP.LT.OR P2, PT, R5, RZ, P2 ; /* 0x000000ff0500720c */
/* 0x000fe40001741670 */
/*01e0*/ IADD3 R6, -R0, 0x3, RZ ; /* 0x0000000300067810 */
/* 0x000fe40007ffe1ff */
/*01f0*/ IADD3 R8, R3, 0x3, RZ ; /* 0x0000000303087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IMAD.IADD R18, R2, 0x1, R7 ; /* 0x0000000102127824 */
/* 0x000fc800078e0207 */
/*0210*/ IMAD R9, R18.reuse, c[0x0][0x17c], R5 ; /* 0x00005f0012097a24 */
/* 0x040fe200078e0205 */
/*0220*/ ISETP.GE.AND P3, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fc80003f66270 */
/*0230*/ ISETP.LT.OR P3, PT, R18, RZ, P3 ; /* 0x000000ff1200720c */
/* 0x000fe40001f61670 */
/*0240*/ IADD3 R10, P5, R9.reuse, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x040fe40007fbe0ff */
/*0250*/ PLOP3.LUT P6, PT, P2, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400017c7570 */
/*0260*/ LEA.HI.X.SX32 R11, R9, c[0x0][0x164], 0x1, P5 ; /* 0x00005900090b7a11 */
/* 0x000fe200028f0eff */
/*0270*/ IMAD.IADD R9, R0, 0x1, R7 ; /* 0x0000000100097824 */
/* 0x000fe400078e0207 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fd000078e00ff */
/*0290*/ @!P6 LDG.E.U8 R19, [R10.64] ; /* 0x000000040a13e981 */
/* 0x000ea2000c1e1100 */
/*02a0*/ IMAD R9, R9, c[0x0][0x180], RZ ; /* 0x0000600009097a24 */
/* 0x000fc800078e02ff */
/*02b0*/ IMAD.WIDE R14, R9, R14, c[0x0][0x170] ; /* 0x00005c00090e7625 */
/* 0x000fca00078e020e */
/*02c0*/ @!P6 LDG.E R16, [R14.64] ; /* 0x000000040e10e981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ ISETP.GE.U32.AND P5, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003fa6070 */
/*02e0*/ @!P6 I2F.U16 R19, R19 ; /* 0x000000130013e306 */
/* 0x004ee40000101000 */
/*02f0*/ @!P6 FMUL R16, R19, R16 ; /* 0x000000101310e220 */
/* 0x008fcc0000400000 */
/*0300*/ @!P6 F2F.F64.F32 R16, R16 ; /* 0x000000100010e310 */
/* 0x000e240000201800 */
/*0310*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0010640000000010 */
/*0320*/ IMAD.MOV.U32 R17, RZ, RZ, R4 ; /* 0x000000ffff117224 */
/* 0x001fe200078e0004 */
/*0330*/ @!P4 BRA 0x430 ; /* 0x000000f00000c947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P6, PT, P0, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x002fda00007c7570 */
/*0350*/ @!P6 LDG.E.U8 R19, [R10.64+0x1] ; /* 0x000001040a13e981 */
/* 0x000ea8000c1e1100 */
/*0360*/ @!P6 LDG.E R16, [R14.64+0x4] ; /* 0x000004040e10e981 */
/* 0x000ee2000c1e1900 */
/*0370*/ @!P6 I2F.U16 R19, R19 ; /* 0x000000130013e306 */
/* 0x004ee40000101000 */
/*0380*/ @!P6 FMUL R20, R19, R16 ; /* 0x000000101314e220 */
/* 0x008fcc0000400000 */
/*0390*/ @!P6 F2F.F64.F32 R16, R20 ; /* 0x000000140010e310 */
/* 0x000e240000201800 */
/*03a0*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0010620000000010 */
/*03b0*/ PLOP3.LUT P6, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000fc7570 */
/*03c0*/ @!P6 LDG.E.U8 R21, [R10.64+0x2] ; /* 0x000002040a15e981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ @!P6 LDG.E R16, [R14.64+0x8] ; /* 0x000008040e10e981 */
/* 0x001ee2000c1e1900 */
/*03e0*/ @!P6 I2F.U16 R21, R21 ; /* 0x000000150015e306 */
/* 0x004ee40000101000 */
/*03f0*/ @!P6 FMUL R16, R21, R16 ; /* 0x000000101510e220 */
/* 0x008fcc0000400000 */
/*0400*/ @!P6 F2F.F64.F32 R16, R16 ; /* 0x000000100010e310 */
/* 0x000e640000201800 */
/*0410*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0020640000000010 */
/*0420*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x001fc800078e0006 */
/*0430*/ ISETP.GE.AND P6, PT, R7.reuse, R0, PT ; /* 0x000000000700720c */
/* 0x042fe40003fc6270 */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0450*/ @!P5 BRA 0x7f0 ; /* 0x000003900000d947 */
/* 0x000ff40003800000 */
/*0460*/ IMAD.IADD R11, R3, 0x1, R17.reuse ; /* 0x00000001030b7824 */
/* 0x100fe200078e0211 */
/*0470*/ IADD3 R9, R9, R0, R17.reuse ; /* 0x0000000009097210 */
/* 0x100fe20007ffe011 */
/*0480*/ IMAD.IADD R20, R8, 0x1, R17 ; /* 0x0000000108147824 */
/* 0x000fe200078e0211 */
/*0490*/ IADD3 R21, R17, -0x1, RZ ; /* 0xffffffff11157810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD R18, R18, c[0x0][0x17c], R11 ; /* 0x00005f0012127a24 */
/* 0x000fc400078e020b */
/*04b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R14, P5, R18, c[0x0][0x160], RZ ; /* 0x00005800120e7a10 */
/* 0x000fc80007fbe0ff */
/*04e0*/ LEA.HI.X.SX32 R15, R18, c[0x0][0x164], 0x1, P5 ; /* 0x00005900120f7a11 */
/* 0x000fe400028f0eff */
/*04f0*/ IADD3 R16, R20, -0x3, RZ ; /* 0xfffffffd14107810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GE.AND P5, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fc80003fa6270 */
/*0510*/ ISETP.LT.OR P5, PT, R16, RZ, P5 ; /* 0x000000ff1000720c */
/* 0x000fc80002fa1670 */
/*0520*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20002fa7570 */
/*0530*/ IMAD.WIDE R16, R9, 0x4, R10 ; /* 0x0000000409107825 */
/* 0x000fd800078e020a */
/*0540*/ @!P5 LDG.E.U8 R23, [R14.64] ; /* 0x000000040e17d981 */
/* 0x000ea8000c1e1100 */
/*0550*/ @!P5 LDG.E R18, [R16.64] ; /* 0x000000041012d981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R25, R20, -0x2, RZ ; /* 0xfffffffe14197810 */
/* 0x000fe20007ffe0ff */
/*0570*/ @!P5 I2F.U16 R23, R23 ; /* 0x000000170017d306 */
/* 0x004ee40000101000 */
/*0580*/ @!P5 FMUL R24, R23, R18 ; /* 0x000000121718d220 */
/* 0x008fcc0000400000 */
/*0590*/ @!P5 F2F.F64.F32 R18, R24 ; /* 0x000000180012d310 */
/* 0x000e240000201800 */
/*05a0*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0010620000000012 */
/*05b0*/ ISETP.GE.AND P5, PT, R25, c[0x0][0x17c], PT ; /* 0x00005f0019007a0c */
/* 0x000fc80003fa6270 */
/*05c0*/ ISETP.LT.OR P5, PT, R25, RZ, P5 ; /* 0x000000ff1900720c */
/* 0x000fc80002fa1670 */
/*05d0*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*05e0*/ @!P5 LDG.E.U8 R25, [R14.64+0x1] ; /* 0x000001040e19d981 */
/* 0x000ea8000c1e1100 */
/*05f0*/ @!P5 LDG.E R18, [R16.64+0x4] ; /* 0x000004041012d981 */
/* 0x001ee2000c1e1900 */
/*0600*/ IADD3 R24, R20, -0x1, RZ ; /* 0xffffffff14187810 */
/* 0x000fe20007ffe0ff */
/*0610*/ @!P5 I2F.U16 R25, R25 ; /* 0x000000190019d306 */
/* 0x004ee40000101000 */
/*0620*/ @!P5 FMUL R23, R25, R18 ; /* 0x000000121917d220 */
/* 0x008fcc0000400000 */
/*0630*/ @!P5 F2F.F64.F32 R18, R23 ; /* 0x000000170012d310 */
/* 0x000e640000201800 */
/*0640*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*0650*/ ISETP.GE.AND P5, PT, R24, c[0x0][0x17c], PT ; /* 0x00005f0018007a0c */
/* 0x000fc80003fa6270 */
/*0660*/ ISETP.LT.OR P5, PT, R24, RZ, P5 ; /* 0x000000ff1800720c */
/* 0x000fc80002fa1670 */
/*0670*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*0680*/ @!P5 LDG.E.U8 R24, [R14.64+0x2] ; /* 0x000002040e18d981 */
/* 0x000ea8000c1e1100 */
/*0690*/ @!P5 LDG.E R19, [R16.64+0x8] ; /* 0x000008041013d981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ @!P5 I2F.U16 R24, R24 ; /* 0x000000180018d306 */
/* 0x004ee40000101000 */
/*06b0*/ @!P5 FMUL R25, R24, R19 ; /* 0x000000131819d220 */
/* 0x008fcc0000400000 */
/*06c0*/ @!P5 F2F.F64.F32 R18, R25 ; /* 0x000000190012d310 */
/* 0x000e640000201800 */
/*06d0*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*06e0*/ ISETP.GE.AND P5, PT, R20, c[0x0][0x17c], PT ; /* 0x00005f0014007a0c */
/* 0x000fc80003fa6270 */
/*06f0*/ ISETP.LT.OR P5, PT, R20, RZ, P5 ; /* 0x000000ff1400720c */
/* 0x000fc80002fa1670 */
/*0700*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*0710*/ @!P5 LDG.E.U8 R23, [R14.64+0x3] ; /* 0x000003040e17d981 */
/* 0x000ea8000c1e1100 */
/*0720*/ @!P5 LDG.E R18, [R16.64+0xc] ; /* 0x00000c041012d981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P5 I2F.U16 R23, R23 ; /* 0x000000170017d306 */
/* 0x004ee40000101000 */
/*0760*/ @!P5 FMUL R18, R23, R18 ; /* 0x000000121712d220 */
/* 0x008fcc0000400000 */
/*0770*/ @!P5 F2F.F64.F32 R18, R18 ; /* 0x000000120012d310 */
/* 0x000e640000201800 */
/*0780*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*0790*/ IADD3 R14, P5, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fca0007fbe0ff */
/*07a0*/ IMAD.X R15, RZ, RZ, R15, P5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200028e060f */
/*07b0*/ IADD3 R10, P5, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fca0007fbe0ff */
/*07c0*/ IMAD.X R11, RZ, RZ, R11, P5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200028e060b */
/*07d0*/ ISETP.GE.AND P5, PT, R21, R0, PT ; /* 0x000000001500720c */
/* 0x000fda0003fa6270 */
/*07e0*/ @!P5 BRA 0x4f0 ; /* 0xfffffd000000d947 */
/* 0x003fea000383ffff */
/*07f0*/ @!P6 BRA 0x200 ; /* 0xfffffa000000e947 */
/* 0x000fea000383ffff */
/*0800*/ DSETP.GT.AND P0, PT, R12, 255, PT ; /* 0x406fe0000c00742a */
/* 0x000e220003f04000 */
/*0810*/ IMAD R3, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002037a24 */
/* 0x000fca00078e0203 */
/*0820*/ FSEL R5, R13, 3.748046875, !P0 ; /* 0x406fe0000d057808 */
/* 0x001fe40004000000 */
/*0830*/ FSEL R4, R12, RZ, !P0 ; /* 0x000000ff0c047208 */
/* 0x000fe40004000000 */
/*0840*/ IADD3 R2, P0, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x040fe40007f1e0ff */
/*0850*/ F2I.U32.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x000e24000030d000 */
/*0860*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0003037a11 */
/* 0x000fca00000f0eff */
/*0870*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0880*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} | .file "tmpxft_000a8f1b_00000000-6_applyGaussianFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
.type _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii, @function
_Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19applyGaussianFilterPhS_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii, .-_Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
.globl _Z19applyGaussianFilterPhS_Pfiii
.type _Z19applyGaussianFilterPhS_Pfiii, @function
_Z19applyGaussianFilterPhS_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19applyGaussianFilterPhS_Pfiii, .-_Z19applyGaussianFilterPhS_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19applyGaussianFilterPhS_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19applyGaussianFilterPhS_Pfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19applyGaussianFilterPhS_Pfiii
.globl _Z19applyGaussianFilterPhS_Pfiii
.p2align 8
.type _Z19applyGaussianFilterPhS_Pfiii,@function
_Z19applyGaussianFilterPhS_Pfiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, s15, v3
v_mov_b32_e32 v1, 0
s_cmp_lt_i32 s5, -1
s_mul_i32 s14, s14, s2
s_cbranch_scc1 .LBB0_8
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x18
s_lshr_b32 s2, s5, 31
v_add_nc_u32_e32 v5, s14, v2
s_add_i32 s2, s5, s2
s_mov_b32 s12, 0
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v0, s2, v3
s_abs_i32 s13, s2
s_sub_i32 s16, 0, s2
s_add_i32 s15, s2, s13
v_mul_lo_u32 v4, s4, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_subrev_nc_u32_e32 v5, s2, v5
s_add_i32 s15, s15, 1
.LBB0_2:
v_add_nc_u32_e32 v6, s16, v3
s_mov_b32 s10, s12
s_mov_b32 s18, s15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s3, v6
v_cmp_gt_i32_e64 s2, 0, v6
v_mov_b32_e32 v6, v5
s_or_b32 s17, vcc_lo, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s18, s18, -1
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s18, 0
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s4, v6
v_cmp_gt_i32_e64 s2, 0, v6
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s17
s_xor_b32 s11, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v7, v4, v6
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[20:21], s[10:11], 2
s_add_u32 s20, s8, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v7, vcc_lo, s6, v7
s_addc_u32 s21, s9, s21
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_load_b32 s11, s[20:21], 0x0
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v7, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s11, v7
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[7:8]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s4, v4
s_add_i32 s2, s16, 1
s_add_i32 s12, s12, s5
s_cmp_eq_u32 s16, s13
s_cbranch_scc1 .LBB0_8
s_mov_b32 s16, s2
s_branch .LBB0_2
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x8
v_cndmask_b32_e32 v1, 0x406fe000, v1, vcc_lo
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cvt_i32_f64_e32 v4, v[0:1]
v_mul_lo_u32 v0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19applyGaussianFilterPhS_Pfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19applyGaussianFilterPhS_Pfiii, .Lfunc_end0-_Z19applyGaussianFilterPhS_Pfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19applyGaussianFilterPhS_Pfiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z19applyGaussianFilterPhS_Pfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define GAUSS_WIDTH 5
#define SOBEL_WIDTH 3
typedef struct images {
char *pType;
int width;
int height;
int maxValColor;
unsigned char *data;
} image;
/**
Reads the input file formatted as pnm. The actual implementation
supports only P5 type pnm images (grayscale).
*/
__global__ void applyGaussianFilter(unsigned char *input, unsigned char *output, float *kernel, int iHeight, int iWidth, int kWidth) {
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
double sum = 0.0;
int halvedKW = kWidth / 2;
for (int i = -halvedKW; i <= halvedKW; i++) {
for (int j = -halvedKW; j <= halvedKW; j++) {
if ((x + j) < iWidth && (x + j) >= 0 && (y + i) < iHeight && (y + i) >= 0) {
int kPosX = (j + halvedKW);
int kPosY = (i + halvedKW);
sum = sum + (float)(input[(y + i) * iWidth + (x + j)]) * kernel[kPosY * kWidth + kPosX];
}
}
}
if (sum > 255.0)
sum = 255.0;
output[y * iWidth + x] = (unsigned char)sum;
} | .text
.file "applyGaussianFilter.hip"
.globl _Z34__device_stub__applyGaussianFilterPhS_Pfiii # -- Begin function _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.p2align 4, 0x90
.type _Z34__device_stub__applyGaussianFilterPhS_Pfiii,@function
_Z34__device_stub__applyGaussianFilterPhS_Pfiii: # @_Z34__device_stub__applyGaussianFilterPhS_Pfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19applyGaussianFilterPhS_Pfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__applyGaussianFilterPhS_Pfiii, .Lfunc_end0-_Z34__device_stub__applyGaussianFilterPhS_Pfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19applyGaussianFilterPhS_Pfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19applyGaussianFilterPhS_Pfiii,@object # @_Z19applyGaussianFilterPhS_Pfiii
.section .rodata,"a",@progbits
.globl _Z19applyGaussianFilterPhS_Pfiii
.p2align 3, 0x0
_Z19applyGaussianFilterPhS_Pfiii:
.quad _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.size _Z19applyGaussianFilterPhS_Pfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19applyGaussianFilterPhS_Pfiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19applyGaussianFilterPhS_Pfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19applyGaussianFilterPhS_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe4000001ff00 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x180], RZ, 0x1 ; /* 0x0000600000007a11 */
/* 0x000fe200078f08ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e260000002100 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011400 */
/*0080*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0090*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fe400078e0202 */
/*00d0*/ IMAD R2, R4, c[0x0][0x4], R5 ; /* 0x0000010004027a24 */
/* 0x002fd400078e0205 */
/*00e0*/ @!P0 BRA 0x800 ; /* 0x0000071000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe20007ffe1ff */
/*0100*/ IMAD.SHL.U32 R22, R0, 0x2, RZ ; /* 0x0000000200167824 */
/* 0x000fe200078e00ff */
/*0110*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.IADD R5, R3.reuse, 0x1, -R0 ; /* 0x0000000103057824 */
/* 0x040fe400078e0a00 */
/*0130*/ IMAD.IADD R8, R3, 0x1, R4 ; /* 0x0000000103087824 */
/* 0x000fe200078e0204 */
/*0140*/ IADD3 R6, R22, 0x1, RZ ; /* 0x0000000116067810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe40003f46270 */
/*0160*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fc40007ffe0ff */
/*0170*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe40003f06270 */
/*0180*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*0190*/ ISETP.GE.AND P1, PT, R9.reuse, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x040fe40003f26270 */
/*01a0*/ ISETP.LT.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fe40000701670 */
/*01b0*/ ISETP.NE.AND P4, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f85270 */
/*01c0*/ ISETP.LT.OR P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fc40000f21670 */
/*01d0*/ ISETP.LT.OR P2, PT, R5, RZ, P2 ; /* 0x000000ff0500720c */
/* 0x000fe40001741670 */
/*01e0*/ IADD3 R6, -R0, 0x3, RZ ; /* 0x0000000300067810 */
/* 0x000fe40007ffe1ff */
/*01f0*/ IADD3 R8, R3, 0x3, RZ ; /* 0x0000000303087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IMAD.IADD R18, R2, 0x1, R7 ; /* 0x0000000102127824 */
/* 0x000fc800078e0207 */
/*0210*/ IMAD R9, R18.reuse, c[0x0][0x17c], R5 ; /* 0x00005f0012097a24 */
/* 0x040fe200078e0205 */
/*0220*/ ISETP.GE.AND P3, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fc80003f66270 */
/*0230*/ ISETP.LT.OR P3, PT, R18, RZ, P3 ; /* 0x000000ff1200720c */
/* 0x000fe40001f61670 */
/*0240*/ IADD3 R10, P5, R9.reuse, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x040fe40007fbe0ff */
/*0250*/ PLOP3.LUT P6, PT, P2, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400017c7570 */
/*0260*/ LEA.HI.X.SX32 R11, R9, c[0x0][0x164], 0x1, P5 ; /* 0x00005900090b7a11 */
/* 0x000fe200028f0eff */
/*0270*/ IMAD.IADD R9, R0, 0x1, R7 ; /* 0x0000000100097824 */
/* 0x000fe400078e0207 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fd000078e00ff */
/*0290*/ @!P6 LDG.E.U8 R19, [R10.64] ; /* 0x000000040a13e981 */
/* 0x000ea2000c1e1100 */
/*02a0*/ IMAD R9, R9, c[0x0][0x180], RZ ; /* 0x0000600009097a24 */
/* 0x000fc800078e02ff */
/*02b0*/ IMAD.WIDE R14, R9, R14, c[0x0][0x170] ; /* 0x00005c00090e7625 */
/* 0x000fca00078e020e */
/*02c0*/ @!P6 LDG.E R16, [R14.64] ; /* 0x000000040e10e981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ ISETP.GE.U32.AND P5, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003fa6070 */
/*02e0*/ @!P6 I2F.U16 R19, R19 ; /* 0x000000130013e306 */
/* 0x004ee40000101000 */
/*02f0*/ @!P6 FMUL R16, R19, R16 ; /* 0x000000101310e220 */
/* 0x008fcc0000400000 */
/*0300*/ @!P6 F2F.F64.F32 R16, R16 ; /* 0x000000100010e310 */
/* 0x000e240000201800 */
/*0310*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0010640000000010 */
/*0320*/ IMAD.MOV.U32 R17, RZ, RZ, R4 ; /* 0x000000ffff117224 */
/* 0x001fe200078e0004 */
/*0330*/ @!P4 BRA 0x430 ; /* 0x000000f00000c947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P6, PT, P0, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x002fda00007c7570 */
/*0350*/ @!P6 LDG.E.U8 R19, [R10.64+0x1] ; /* 0x000001040a13e981 */
/* 0x000ea8000c1e1100 */
/*0360*/ @!P6 LDG.E R16, [R14.64+0x4] ; /* 0x000004040e10e981 */
/* 0x000ee2000c1e1900 */
/*0370*/ @!P6 I2F.U16 R19, R19 ; /* 0x000000130013e306 */
/* 0x004ee40000101000 */
/*0380*/ @!P6 FMUL R20, R19, R16 ; /* 0x000000101314e220 */
/* 0x008fcc0000400000 */
/*0390*/ @!P6 F2F.F64.F32 R16, R20 ; /* 0x000000140010e310 */
/* 0x000e240000201800 */
/*03a0*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0010620000000010 */
/*03b0*/ PLOP3.LUT P6, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000fc7570 */
/*03c0*/ @!P6 LDG.E.U8 R21, [R10.64+0x2] ; /* 0x000002040a15e981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ @!P6 LDG.E R16, [R14.64+0x8] ; /* 0x000008040e10e981 */
/* 0x001ee2000c1e1900 */
/*03e0*/ @!P6 I2F.U16 R21, R21 ; /* 0x000000150015e306 */
/* 0x004ee40000101000 */
/*03f0*/ @!P6 FMUL R16, R21, R16 ; /* 0x000000101510e220 */
/* 0x008fcc0000400000 */
/*0400*/ @!P6 F2F.F64.F32 R16, R16 ; /* 0x000000100010e310 */
/* 0x000e640000201800 */
/*0410*/ @!P6 DADD R12, R12, R16 ; /* 0x000000000c0ce229 */
/* 0x0020640000000010 */
/*0420*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x001fc800078e0006 */
/*0430*/ ISETP.GE.AND P6, PT, R7.reuse, R0, PT ; /* 0x000000000700720c */
/* 0x042fe40003fc6270 */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0450*/ @!P5 BRA 0x7f0 ; /* 0x000003900000d947 */
/* 0x000ff40003800000 */
/*0460*/ IMAD.IADD R11, R3, 0x1, R17.reuse ; /* 0x00000001030b7824 */
/* 0x100fe200078e0211 */
/*0470*/ IADD3 R9, R9, R0, R17.reuse ; /* 0x0000000009097210 */
/* 0x100fe20007ffe011 */
/*0480*/ IMAD.IADD R20, R8, 0x1, R17 ; /* 0x0000000108147824 */
/* 0x000fe200078e0211 */
/*0490*/ IADD3 R21, R17, -0x1, RZ ; /* 0xffffffff11157810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD R18, R18, c[0x0][0x17c], R11 ; /* 0x00005f0012127a24 */
/* 0x000fc400078e020b */
/*04b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R14, P5, R18, c[0x0][0x160], RZ ; /* 0x00005800120e7a10 */
/* 0x000fc80007fbe0ff */
/*04e0*/ LEA.HI.X.SX32 R15, R18, c[0x0][0x164], 0x1, P5 ; /* 0x00005900120f7a11 */
/* 0x000fe400028f0eff */
/*04f0*/ IADD3 R16, R20, -0x3, RZ ; /* 0xfffffffd14107810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GE.AND P5, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fc80003fa6270 */
/*0510*/ ISETP.LT.OR P5, PT, R16, RZ, P5 ; /* 0x000000ff1000720c */
/* 0x000fc80002fa1670 */
/*0520*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20002fa7570 */
/*0530*/ IMAD.WIDE R16, R9, 0x4, R10 ; /* 0x0000000409107825 */
/* 0x000fd800078e020a */
/*0540*/ @!P5 LDG.E.U8 R23, [R14.64] ; /* 0x000000040e17d981 */
/* 0x000ea8000c1e1100 */
/*0550*/ @!P5 LDG.E R18, [R16.64] ; /* 0x000000041012d981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R25, R20, -0x2, RZ ; /* 0xfffffffe14197810 */
/* 0x000fe20007ffe0ff */
/*0570*/ @!P5 I2F.U16 R23, R23 ; /* 0x000000170017d306 */
/* 0x004ee40000101000 */
/*0580*/ @!P5 FMUL R24, R23, R18 ; /* 0x000000121718d220 */
/* 0x008fcc0000400000 */
/*0590*/ @!P5 F2F.F64.F32 R18, R24 ; /* 0x000000180012d310 */
/* 0x000e240000201800 */
/*05a0*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0010620000000012 */
/*05b0*/ ISETP.GE.AND P5, PT, R25, c[0x0][0x17c], PT ; /* 0x00005f0019007a0c */
/* 0x000fc80003fa6270 */
/*05c0*/ ISETP.LT.OR P5, PT, R25, RZ, P5 ; /* 0x000000ff1900720c */
/* 0x000fc80002fa1670 */
/*05d0*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*05e0*/ @!P5 LDG.E.U8 R25, [R14.64+0x1] ; /* 0x000001040e19d981 */
/* 0x000ea8000c1e1100 */
/*05f0*/ @!P5 LDG.E R18, [R16.64+0x4] ; /* 0x000004041012d981 */
/* 0x001ee2000c1e1900 */
/*0600*/ IADD3 R24, R20, -0x1, RZ ; /* 0xffffffff14187810 */
/* 0x000fe20007ffe0ff */
/*0610*/ @!P5 I2F.U16 R25, R25 ; /* 0x000000190019d306 */
/* 0x004ee40000101000 */
/*0620*/ @!P5 FMUL R23, R25, R18 ; /* 0x000000121917d220 */
/* 0x008fcc0000400000 */
/*0630*/ @!P5 F2F.F64.F32 R18, R23 ; /* 0x000000170012d310 */
/* 0x000e640000201800 */
/*0640*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*0650*/ ISETP.GE.AND P5, PT, R24, c[0x0][0x17c], PT ; /* 0x00005f0018007a0c */
/* 0x000fc80003fa6270 */
/*0660*/ ISETP.LT.OR P5, PT, R24, RZ, P5 ; /* 0x000000ff1800720c */
/* 0x000fc80002fa1670 */
/*0670*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*0680*/ @!P5 LDG.E.U8 R24, [R14.64+0x2] ; /* 0x000002040e18d981 */
/* 0x000ea8000c1e1100 */
/*0690*/ @!P5 LDG.E R19, [R16.64+0x8] ; /* 0x000008041013d981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ @!P5 I2F.U16 R24, R24 ; /* 0x000000180018d306 */
/* 0x004ee40000101000 */
/*06b0*/ @!P5 FMUL R25, R24, R19 ; /* 0x000000131819d220 */
/* 0x008fcc0000400000 */
/*06c0*/ @!P5 F2F.F64.F32 R18, R25 ; /* 0x000000190012d310 */
/* 0x000e640000201800 */
/*06d0*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*06e0*/ ISETP.GE.AND P5, PT, R20, c[0x0][0x17c], PT ; /* 0x00005f0014007a0c */
/* 0x000fc80003fa6270 */
/*06f0*/ ISETP.LT.OR P5, PT, R20, RZ, P5 ; /* 0x000000ff1400720c */
/* 0x000fc80002fa1670 */
/*0700*/ PLOP3.LUT P5, PT, P5, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fa7570 */
/*0710*/ @!P5 LDG.E.U8 R23, [R14.64+0x3] ; /* 0x000003040e17d981 */
/* 0x000ea8000c1e1100 */
/*0720*/ @!P5 LDG.E R18, [R16.64+0xc] ; /* 0x00000c041012d981 */
/* 0x001ee2000c1e1900 */
/*0730*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P5 I2F.U16 R23, R23 ; /* 0x000000170017d306 */
/* 0x004ee40000101000 */
/*0760*/ @!P5 FMUL R18, R23, R18 ; /* 0x000000121712d220 */
/* 0x008fcc0000400000 */
/*0770*/ @!P5 F2F.F64.F32 R18, R18 ; /* 0x000000120012d310 */
/* 0x000e640000201800 */
/*0780*/ @!P5 DADD R12, R12, R18 ; /* 0x000000000c0cd229 */
/* 0x0020620000000012 */
/*0790*/ IADD3 R14, P5, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fca0007fbe0ff */
/*07a0*/ IMAD.X R15, RZ, RZ, R15, P5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200028e060f */
/*07b0*/ IADD3 R10, P5, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fca0007fbe0ff */
/*07c0*/ IMAD.X R11, RZ, RZ, R11, P5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200028e060b */
/*07d0*/ ISETP.GE.AND P5, PT, R21, R0, PT ; /* 0x000000001500720c */
/* 0x000fda0003fa6270 */
/*07e0*/ @!P5 BRA 0x4f0 ; /* 0xfffffd000000d947 */
/* 0x003fea000383ffff */
/*07f0*/ @!P6 BRA 0x200 ; /* 0xfffffa000000e947 */
/* 0x000fea000383ffff */
/*0800*/ DSETP.GT.AND P0, PT, R12, 255, PT ; /* 0x406fe0000c00742a */
/* 0x000e220003f04000 */
/*0810*/ IMAD R3, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002037a24 */
/* 0x000fca00078e0203 */
/*0820*/ FSEL R5, R13, 3.748046875, !P0 ; /* 0x406fe0000d057808 */
/* 0x001fe40004000000 */
/*0830*/ FSEL R4, R12, RZ, !P0 ; /* 0x000000ff0c047208 */
/* 0x000fe40004000000 */
/*0840*/ IADD3 R2, P0, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x040fe40007f1e0ff */
/*0850*/ F2I.U32.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x000e24000030d000 */
/*0860*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0003037a11 */
/* 0x000fca00000f0eff */
/*0870*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0880*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19applyGaussianFilterPhS_Pfiii
.globl _Z19applyGaussianFilterPhS_Pfiii
.p2align 8
.type _Z19applyGaussianFilterPhS_Pfiii,@function
_Z19applyGaussianFilterPhS_Pfiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, s15, v3
v_mov_b32_e32 v1, 0
s_cmp_lt_i32 s5, -1
s_mul_i32 s14, s14, s2
s_cbranch_scc1 .LBB0_8
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x18
s_lshr_b32 s2, s5, 31
v_add_nc_u32_e32 v5, s14, v2
s_add_i32 s2, s5, s2
s_mov_b32 s12, 0
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v0, s2, v3
s_abs_i32 s13, s2
s_sub_i32 s16, 0, s2
s_add_i32 s15, s2, s13
v_mul_lo_u32 v4, s4, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_subrev_nc_u32_e32 v5, s2, v5
s_add_i32 s15, s15, 1
.LBB0_2:
v_add_nc_u32_e32 v6, s16, v3
s_mov_b32 s10, s12
s_mov_b32 s18, s15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s3, v6
v_cmp_gt_i32_e64 s2, 0, v6
v_mov_b32_e32 v6, v5
s_or_b32 s17, vcc_lo, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s18, s18, -1
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s18, 0
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s4, v6
v_cmp_gt_i32_e64 s2, 0, v6
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s17
s_xor_b32 s11, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v7, v4, v6
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[20:21], s[10:11], 2
s_add_u32 s20, s8, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v7, vcc_lo, s6, v7
s_addc_u32 s21, s9, s21
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_load_b32 s11, s[20:21], 0x0
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v7, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s11, v7
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[7:8]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s4, v4
s_add_i32 s2, s16, 1
s_add_i32 s12, s12, s5
s_cmp_eq_u32 s16, s13
s_cbranch_scc1 .LBB0_8
s_mov_b32 s16, s2
s_branch .LBB0_2
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x8
v_cndmask_b32_e32 v1, 0x406fe000, v1, vcc_lo
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cvt_i32_f64_e32 v4, v[0:1]
v_mul_lo_u32 v0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19applyGaussianFilterPhS_Pfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19applyGaussianFilterPhS_Pfiii, .Lfunc_end0-_Z19applyGaussianFilterPhS_Pfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19applyGaussianFilterPhS_Pfiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z19applyGaussianFilterPhS_Pfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8f1b_00000000-6_applyGaussianFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
.type _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii, @function
_Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19applyGaussianFilterPhS_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii, .-_Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
.globl _Z19applyGaussianFilterPhS_Pfiii
.type _Z19applyGaussianFilterPhS_Pfiii, @function
_Z19applyGaussianFilterPhS_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19applyGaussianFilterPhS_PfiiiPhS_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19applyGaussianFilterPhS_Pfiii, .-_Z19applyGaussianFilterPhS_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19applyGaussianFilterPhS_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19applyGaussianFilterPhS_Pfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "applyGaussianFilter.hip"
.globl _Z34__device_stub__applyGaussianFilterPhS_Pfiii # -- Begin function _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.p2align 4, 0x90
.type _Z34__device_stub__applyGaussianFilterPhS_Pfiii,@function
_Z34__device_stub__applyGaussianFilterPhS_Pfiii: # @_Z34__device_stub__applyGaussianFilterPhS_Pfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19applyGaussianFilterPhS_Pfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__applyGaussianFilterPhS_Pfiii, .Lfunc_end0-_Z34__device_stub__applyGaussianFilterPhS_Pfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19applyGaussianFilterPhS_Pfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19applyGaussianFilterPhS_Pfiii,@object # @_Z19applyGaussianFilterPhS_Pfiii
.section .rodata,"a",@progbits
.globl _Z19applyGaussianFilterPhS_Pfiii
.p2align 3, 0x0
_Z19applyGaussianFilterPhS_Pfiii:
.quad _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.size _Z19applyGaussianFilterPhS_Pfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19applyGaussianFilterPhS_Pfiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__applyGaussianFilterPhS_Pfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19applyGaussianFilterPhS_Pfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#include <cuda_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess){
fprintf(stderr, "Cuda Error : %s\n", cudaGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
cudaMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
cudaMemcpy(dev_x_prev, host_x, size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), cudaMemcpyDeviceToDevice);
checkGPUOperation();
cudaMemcpy(dev_B, host_B, size * size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_g, host_g, size * sizeof(float), cudaMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
cudaDeviceSynchronize();
}
//get result
cudaMemcpy(host_x, dev_x_next, size * sizeof(float), cudaMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
cudaFree(dev_B);
cudaFree(dev_g);
cudaFree(dev_x_prev);
cudaFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} | code for sm_80
Function : _Z6jacobiPfS_S_jS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, 0x400, PT ; /* 0x000004000200780c */
/* 0x000fe20003f04070 */
/*0060*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fd800078e0203 */
/*0070*/ @P0 BRA 0xc00 ; /* 0x00000b8000000947 */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fce0003f45070 */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*00e0*/ IADD3 R9, RZ, -R7, RZ ; /* 0x80000007ff097210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0110*/ IMAD.HI.U32 R7, R7, 0x400, RZ ; /* 0x0000040007077827 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R9, -R7, RZ, RZ ; /* 0x000000ff07097210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R8, R2, R9, 0x400 ; /* 0x0000040002087424 */
/* 0x000fca00078e0209 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R8, R8, -c[0x0][0x0], RZ ; /* 0x8000000008080a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fe20003f26070 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd800078e00ff */
/*0190*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff07aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IMNMX.U32 R7, R7, 0x1, !PT ; /* 0x0000000107077817 */
/* 0x000fc80007800000 */
/*01c0*/ IADD3 R5, R7.reuse, -0x1, RZ ; /* 0xffffffff07057810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe400078ec0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 BRA 0xb30 ; /* 0x0000093000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R9, R7, -R6, RZ ; /* 0x8000000607097210 */
/* 0x000fe20007ffe0ff */
/*0210*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0220*/ IMAD.SHL.U32 R29, R3, 0x4, RZ ; /* 0x00000004031d7824 */
/* 0x000fe400078e00ff */
/*0230*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fd800078e0003 */
/*0250*/ @!P0 BRA 0x9d0 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0280*/ @!P1 BRA 0x730 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fd400000001ff */
/*02b0*/ IMAD.WIDE R18, R7, R16, c[0x0][0x170] ; /* 0x00005c0007127625 */
/* 0x002fca00078e0210 */
/*02c0*/ LDG.E R10, [R18.64] ; /* 0x00000006120a7981 */
/* 0x0000a2000c1e1900 */
/*02d0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fca00078e0212 */
/*02e0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x0002e4000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R2, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x002fca00078e020e */
/*0300*/ LDG.E R21, [R14.64] ; /* 0x000000060e157981 */
/* 0x000322000c1e1900 */
/*0310*/ IMAD R5, R2.reuse, 0x4, R7 ; /* 0x0000000402057824 */
/* 0x040fe400078e0207 */
/*0320*/ IMAD.WIDE R22, R2, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x000fc800078e020e */
/*0330*/ IMAD.WIDE R12, R5, R16, c[0x0][0x170] ; /* 0x00005c00050c7625 */
/* 0x000fe400078e0210 */
/*0340*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000b22000c1e1900 */
/*0350*/ LEA R5, R2, R5, 0x2 ; /* 0x0000000502057211 */
/* 0x000fc600078e10ff */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fe400078e020c */
/*0370*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000324000c1e1900 */
/*0380*/ IMAD.WIDE R26, R5, R16, c[0x0][0x170] ; /* 0x00005c00051a7625 */
/* 0x000fc800078e0210 */
/*0390*/ IMAD R5, R2.reuse, 0x4, R5 ; /* 0x0000000402057824 */
/* 0x040fe400078e0205 */
/*03a0*/ IMAD.WIDE R18, R2.reuse, 0x4, R24 ; /* 0x0000000402127825 */
/* 0x041fe400078e0218 */
/*03b0*/ LDG.E R25, [R24.64] ; /* 0x0000000618197981 */
/* 0x000124000c1e1900 */
/*03c0*/ IMAD.WIDE R16, R5, R16, c[0x0][0x170] ; /* 0x00005c0005107625 */
/* 0x000fe400078e0210 */
/*03d0*/ LDG.E R7, [R18.64] ; /* 0x0000000612077981 */
/* 0x000b24000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R2, 0x4, R26 ; /* 0x00000004020e7825 */
/* 0x002fc400078e021a */
/*03f0*/ LDG.E R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000328000c1e1900 */
/*0400*/ LDG.E R24, [R14.64] ; /* 0x000000060e187981 */
/* 0x001122000c1e1900 */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R18 ; /* 0x0000000402127825 */
/* 0x020fc600078e0212 */
/*0420*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000b22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x002fc800078e0210 */
/*0440*/ IMAD.WIDE R14, R2.reuse, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x041fe200078e020e */
/*0450*/ LDG.E R12, [R16.64] ; /* 0x00000006100c7981 */
/* 0x000128000c1e1900 */
/*0460*/ LDG.E R27, [R18.64] ; /* 0x00000006121b7981 */
/* 0x020368000c1e1900 */
/*0470*/ LDG.E R22, [R14.64] ; /* 0x000000060e167981 */
/* 0x000162000c1e1900 */
/*0480*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc800078e0210 */
/*0490*/ IMAD.WIDE R14, R2.reuse, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x041fe200078e020e */
/*04a0*/ LDG.E R28, [R18.64] ; /* 0x00000006121c7981 */
/* 0x00016a000c1e1900 */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000362000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R2, 0x4, R18 ; /* 0x0000000402127825 */
/* 0x001fcc00078e0212 */
/*04d0*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000162000c1e1900 */
/*04e0*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0500*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*0510*/ STS [R29], R10 ; /* 0x0000000a1d007388 */
/* 0x0045e40000000800 */
/*0520*/ LEA R29, R2, R29, 0x2 ; /* 0x0000001d021d7211 */
/* 0x004fca00078e10ff */
/*0530*/ IMAD R10, R2.reuse, 0x4, R29 ; /* 0x00000004020a7824 */
/* 0x040fe200078e021d */
/*0540*/ STS [R29], R11 ; /* 0x0000000b1d007388 */
/* 0x0085e80000000800 */
/*0550*/ LEA R11, R2.reuse, R10, 0x2 ; /* 0x0000000a020b7211 */
/* 0x044fe200078e10ff */
/*0560*/ STS [R10], R21 ; /* 0x000000150a007388 */
/* 0x0105e80000000800 */
/*0570*/ IMAD R19, R2, 0x4, R11 ; /* 0x0000000402137824 */
/* 0x001fca00078e020b */
/*0580*/ LEA R21, R2, R19, 0x2 ; /* 0x0000001302157211 */
/* 0x004fca00078e10ff */
/*0590*/ IMAD R15, R2, 0x4, R21 ; /* 0x00000004020f7824 */
/* 0x002fca00078e0215 */
/*05a0*/ LEA R16, R2.reuse, R15, 0x2 ; /* 0x0000000f02107211 */
/* 0x040fe200078e10ff */
/*05b0*/ STS [R11], R23 ; /* 0x000000170b007388 */
/* 0x000fe80000000800 */
/*05c0*/ IMAD R17, R2.reuse, 0x4, R16 ; /* 0x0000000402117824 */
/* 0x040fe200078e0210 */
/*05d0*/ STS [R19], R13 ; /* 0x0000000d13007388 */
/* 0x0001e80000000800 */
/*05e0*/ LEA R13, R2, R17, 0x2 ; /* 0x00000011020d7211 */
/* 0x001fca00078e10ff */
/*05f0*/ IMAD R29, R2, 0x4, R13 ; /* 0x00000004021d7824 */
/* 0x000fca00078e020d */
/*0600*/ LEA R11, R2.reuse, R29, 0x2 ; /* 0x0000001d020b7211 */
/* 0x040fe200078e10ff */
/*0610*/ STS [R21], R25 ; /* 0x0000001915007388 */
/* 0x000fe80000000800 */
/*0620*/ IMAD R10, R2.reuse, 0x4, R11 ; /* 0x00000004020a7824 */
/* 0x040fe200078e020b */
/*0630*/ STS [R15], R7 ; /* 0x000000070f007388 */
/* 0x0001e80000000800 */
/*0640*/ LEA R15, R2.reuse, R10, 0x2 ; /* 0x0000000a020f7211 */
/* 0x041fe200078e10ff */
/*0650*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x020fe80000000800 */
/*0660*/ IMAD R23, R2.reuse, 0x4, R15 ; /* 0x0000000402177824 */
/* 0x040fe200078e020f */
/*0670*/ STS [R17], R26 ; /* 0x0000001a11007388 */
/* 0x000fe80000000800 */
/*0680*/ STS [R13], R24 ; /* 0x000000180d007388 */
/* 0x000fe20000000800 */
/*0690*/ LEA R19, R2, R23, 0x2 ; /* 0x0000001702137211 */
/* 0x000fc600078e10ff */
/*06a0*/ STS [R29], R22 ; /* 0x000000161d007388 */
/* 0x0001e80000000800 */
/*06b0*/ STS [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0003e80000000800 */
/*06c0*/ STS [R10], R20 ; /* 0x000000140a007388 */
/* 0x0003e80000000800 */
/*06d0*/ STS [R15], R12 ; /* 0x0000000c0f007388 */
/* 0x0003e80000000800 */
/*06e0*/ STS [R23], R28 ; /* 0x0000001c17007388 */
/* 0x0003e80000000800 */
/*06f0*/ STS [R19], R18 ; /* 0x0000001213007388 */
/* 0x0003e20000000800 */
/*0700*/ IMAD R7, R2.reuse, 0x4, R5 ; /* 0x0000000402077824 */
/* 0x040fe200078e0205 */
/*0710*/ LEA R29, R2, R19, 0x2 ; /* 0x00000013021d7211 */
/* 0x001fe200078e10ff */
/*0720*/ @P1 BRA 0x2a0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0740*/ @!P1 BRA 0x9b0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x002fe200078e00ff */
/*0760*/ LEA R5, R2, R7, 0x2 ; /* 0x0000000702057211 */
/* 0x000fc600078e10ff */
/*0770*/ IMAD.WIDE R22, R7, R10, c[0x0][0x170] ; /* 0x00005c0007167625 */
/* 0x000fc800078e020a */
/*0780*/ IMAD.WIDE R10, R5, R10, c[0x0][0x170] ; /* 0x00005c00050a7625 */
/* 0x000fc800078e020a */
/*0790*/ IMAD.WIDE R12, R2.reuse, 0x4, R22 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0216 */
/*07a0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x0000a4000c1e1900 */
/*07b0*/ IMAD.WIDE R14, R2.reuse, 0x4, R10 ; /* 0x00000004020e7825 */
/* 0x040fe400078e020a */
/*07c0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x0002e4000c1e1900 */
/*07d0*/ IMAD.WIDE R16, R2.reuse, 0x4, R12 ; /* 0x0000000402107825 */
/* 0x040fe400078e020c */
/*07e0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000964000c1e1900 */
/*07f0*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fc400078e020e */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD.WIDE R20, R2.reuse, 0x4, R16 ; /* 0x0000000402147825 */
/* 0x040fe400078e0210 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x0000e4000c1e1900 */
/*0830*/ IMAD.WIDE R24, R2.reuse, 0x4, R18 ; /* 0x0000000402187825 */
/* 0x040fe400078e0212 */
/*0840*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ee8000c1e1900 */
/*0850*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ee2000c1e1900 */
/*0870*/ IMAD R7, R2, 0x4, R29 ; /* 0x0000000402077824 */
/* 0x000fca00078e021d */
/*0880*/ LEA R27, R2, R7, 0x2 ; /* 0x00000007021b7211 */
/* 0x000fca00078e10ff */
/*0890*/ IMAD R23, R2, 0x4, R27 ; /* 0x0000000402177824 */
/* 0x001fca00078e021b */
/*08a0*/ LEA R13, R2, R23, 0x2 ; /* 0x00000017020d7211 */
/* 0x010fca00078e10ff */
/*08b0*/ IMAD R17, R2, 0x4, R13 ; /* 0x0000000402117824 */
/* 0x000fca00078e020d */
/*08c0*/ LEA R26, R2, R17, 0x2 ; /* 0x00000011021a7211 */
/* 0x000fca00078e10ff */
/*08d0*/ IMAD R11, R2, 0x4, R26 ; /* 0x00000004020b7824 */
/* 0x002fe200078e021a */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0910*/ STS [R29], R22 ; /* 0x000000161d007388 */
/* 0x004fe80000000800 */
/*0920*/ STS [R7], R12 ; /* 0x0000000c07007388 */
/* 0x0201e80000000800 */
/*0930*/ STS [R27], R16 ; /* 0x000000101b007388 */
/* 0x0083e80000000800 */
/*0940*/ STS [R23], R20 ; /* 0x0000001417007388 */
/* 0x0003e80000000800 */
/*0950*/ STS [R13], R10 ; /* 0x0000000a0d007388 */
/* 0x0003e80000000800 */
/*0960*/ STS [R17], R14 ; /* 0x0000000e11007388 */
/* 0x0003e80000000800 */
/*0970*/ STS [R26], R18 ; /* 0x000000121a007388 */
/* 0x0003e80000000800 */
/*0980*/ STS [R11], R24 ; /* 0x000000180b007388 */
/* 0x0003e20000000800 */
/*0990*/ LEA R7, R2.reuse, R5, 0x2 ; /* 0x0000000502077211 */
/* 0x041fe200078e10ff */
/*09a0*/ IMAD R29, R2, 0x4, R11 ; /* 0x00000004021d7824 */
/* 0x000fc400078e020b */
/*09b0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*09c0*/ @!P0 BRA 0xb30 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*09d0*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x002fca0000000f00 */
/*09e0*/ IMAD.WIDE R14, R7, R14, c[0x0][0x170] ; /* 0x00005c00070e7625 */
/* 0x000fcc00078e020e */
/*09f0*/ IMAD.WIDE R16, R2.reuse, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x040fe400078e020e */
/*0a00*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee8000c1e1900 */
/*0a30*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc400078e020c */
/*0a40*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f62000c1e1900 */
/*0a60*/ IMAD R5, R2, 0x4, R29 ; /* 0x0000000402057824 */
/* 0x000fca00078e021d */
/*0a70*/ LEA R19, R2, R5, 0x2 ; /* 0x0000000502137211 */
/* 0x000fca00078e10ff */
/*0a80*/ IMAD R21, R2, 0x4, R19 ; /* 0x0000000402157824 */
/* 0x000fe200078e0213 */
/*0a90*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc80007ffe0ff */
/*0aa0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0ab0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ LEA R7, R2.reuse, R7, 0x2 ; /* 0x0000000702077211 */
/* 0x040fe200078e10ff */
/*0ad0*/ STS [R29], R14 ; /* 0x0000000e1d007388 */
/* 0x0041e80000000800 */
/*0ae0*/ STS [R5], R16 ; /* 0x0000001005007388 */
/* 0x0083e80000000800 */
/*0af0*/ STS [R19], R12 ; /* 0x0000000c13007388 */
/* 0x0103e80000000800 */
/*0b00*/ STS [R21], R10 ; /* 0x0000000a15007388 */
/* 0x0203e20000000800 */
/*0b10*/ IMAD R29, R2, 0x4, R21 ; /* 0x00000004021d7824 */
/* 0x001fe200078e0215 */
/*0b20*/ @P0 BRA 0x9d0 ; /* 0xfffffea000000947 */
/* 0x002fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc00 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD R5, R8, c[0x0][0x0], R3 ; /* 0x0000000008057a24 */
/* 0x000fca00078e0203 */
/*0b60*/ SHF.L.U32 R7, R5, 0x2, RZ ; /* 0x0000000205077819 */
/* 0x000fe400000006ff */
/*0b70*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0b80*/ IMAD.WIDE R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fcc00078e0208 */
/*0b90*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0bb0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0bd0*/ STS [R7], R8 ; /* 0x0000000807007388 */
/* 0x0041e40000000800 */
/*0be0*/ LEA R7, R2, R7, 0x2 ; /* 0x0000000702077211 */
/* 0x001fd400078e10ff */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c10*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0c20*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0c30*/ @!P0 BRA 0xf90 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x002fe20000000f00 */
/*0c50*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fc600000001ff */
/*0c60*/ IADD3 R5, R13.reuse, -0x1, RZ ; /* 0xffffffff0d057810 */
/* 0x040fe40007ffe0ff */
/*0c70*/ LOP3.LUT R2, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d027812 */
/* 0x000fe400078ec0ff */
/*0c80*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0c90*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0ca0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f25270 */
/*0cb0*/ @!P0 BRA 0xec0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ IADD3 R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a10 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ IMAD R12, R13.reuse, 0x3, R4 ; /* 0x000000030d0c7824 */
/* 0x040fe200078e0204 */
/*0ce0*/ LEA R16, R13, R4.reuse, 0x1 ; /* 0x000000040d107211 */
/* 0x080fe200078e08ff */
/*0cf0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0d00*/ IADD3 R20, R2, -c[0x0][0x178], RZ ; /* 0x80005e0002147a10 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fe200078e0203 */
/*0d20*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0d30*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0d40*/ MOV R18, R4 ; /* 0x0000000400127202 */
/* 0x000fe40000000f00 */
/*0d50*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0d60*/ LDS.128 R8, [UR4] ; /* 0x00000004ff087984 */
/* 0x000e260008000c00 */
/*0d70*/ IMAD.WIDE.U32 R24, R18, R15, c[0x0][0x160] ; /* 0x0000580012187625 */
/* 0x000fc800078e000f */
/*0d80*/ IMAD.WIDE.U32 R22, R0, R15.reuse, c[0x0][0x160] ; /* 0x0000580000167625 */
/* 0x080fe400078e000f */
/*0d90*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000e24000c1e1900 */
/*0da0*/ IMAD.WIDE.U32 R6, R16, R15.reuse, c[0x0][0x160] ; /* 0x0000580010067625 */
/* 0x080fe400078e000f */
/*0db0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea4000c1e1900 */
/*0dc0*/ IMAD.WIDE.U32 R14, R12, R15, c[0x0][0x160] ; /* 0x000058000c0e7625 */
/* 0x000fe400078e000f */
/*0dd0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee8000c1e1900 */
/*0de0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f22000c1e1900 */
/*0df0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007ffe0ff */
/*0e00*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0e10*/ LEA R0, R13.reuse, R0, 0x2 ; /* 0x000000000d007211 */
/* 0x040fe200078e10ff */
/*0e20*/ IMAD R16, R13, 0x4, R16 ; /* 0x000000040d107824 */
/* 0x000fe200078e0210 */
/*0e30*/ IADD3 R3, R20, R17, RZ ; /* 0x0000001114037210 */
/* 0x000fc40007ffe0ff */
/*0e40*/ LEA R18, R13, R18, 0x2 ; /* 0x000000120d127211 */
/* 0x000fe400078e10ff */
/*0e50*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0e60*/ LEA R12, R13, R12, 0x2 ; /* 0x0000000c0d0c7211 */
/* 0x000fe200078e10ff */
/*0e70*/ FFMA R8, R8, R24, R5 ; /* 0x0000001808087223 */
/* 0x001fc80000000005 */
/*0e80*/ FFMA R9, R22, R9, R8 ; /* 0x0000000916097223 */
/* 0x004fc80000000008 */
/*0e90*/ FFMA R10, R6, R10, R9 ; /* 0x0000000a060a7223 */
/* 0x008fc80000000009 */
/*0ea0*/ FFMA R5, R14, R11, R10 ; /* 0x0000000b0e057223 */
/* 0x010fe2000000000a */
/*0eb0*/ @P0 BRA 0xd50 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0ec0*/ @!P1 BRA 0xf90 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0ed0*/ IMAD.SHL.U32 R0, R17.reuse, 0x4, RZ ; /* 0x0000000411007824 */
/* 0x040fe400078e00ff */
/*0ee0*/ IMAD R17, R17, c[0x0][0x178], R4 ; /* 0x00005e0011117a24 */
/* 0x000fe400078e0204 */
/*0ef0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0f00*/ LDS R8, [R0] ; /* 0x0000000000087984 */
/* 0x0000680000000800 */
/*0f10*/ IMAD.WIDE.U32 R6, R17, R6, c[0x0][0x160] ; /* 0x0000580011067625 */
/* 0x000fcc00078e0006 */
/*0f20*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000e62000c1e1900 */
/*0f30*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0f40*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe40007ffe0ff */
/*0f50*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0f60*/ IADD3 R17, R17, c[0x0][0x178], RZ ; /* 0x00005e0011117a10 */
/* 0x000fe20007ffe0ff */
/*0f70*/ FFMA R5, R8, R6, R5 ; /* 0x0000000608057223 */
/* 0x002fd40000000005 */
/*0f80*/ @P0 BRA 0xef0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0f90*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0fa0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0207 */
/*0fb0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0fc0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x180] ; /* 0x0000600004067625 */
/* 0x000fc800078e0207 */
/*0fd0*/ FADD R5, R2, R5 ; /* 0x0000000502057221 */
/* 0x004fca0000000000 */
/*0fe0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101906 */
/*0ff0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#include <cuda_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess){
fprintf(stderr, "Cuda Error : %s\n", cudaGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
cudaMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
cudaMemcpy(dev_x_prev, host_x, size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), cudaMemcpyDeviceToDevice);
checkGPUOperation();
cudaMemcpy(dev_B, host_B, size * size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_g, host_g, size * sizeof(float), cudaMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
cudaDeviceSynchronize();
}
//get result
cudaMemcpy(host_x, dev_x_next, size * sizeof(float), cudaMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
cudaFree(dev_B);
cudaFree(dev_g);
cudaFree(dev_x_prev);
cudaFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} | .file "tmpxft_000c0d47_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2441:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2441:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "getMatrix doesn't get matrix\n"
.text
.globl _Z9getMatrixPfj
.type _Z9getMatrixPfj, @function
_Z9getMatrixPfj:
.LFB2431:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
testq %rdi, %rdi
je .L4
movq %rdi, %r13
movl %esi, %r12d
movl $0, %r14d
testl %esi, %esi
je .L3
.L5:
movl %r14d, %ebp
movl $0, %ebx
.L7:
call rand@PLT
movl %eax, %edx
movl %ebp, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movl %ebx, %eax
addl $1, %ebx
addl %r12d, %ebp
cmpl %ebx, %r12d
jne .L7
leal 1(%r14), %edx
cmpl %eax, %r14d
je .L8
movl %edx, %r14d
jmp .L5
.L4:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
leal 2(%rax), %edi
movl $0, %ecx
movl $0, %edx
movss .LC4(%rip), %xmm1
.L9:
movl %ecx, %esi
leaq 0(%r13,%rsi,4), %rsi
movaps %xmm1, %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rsi)
movl %edx, %esi
addl $1, %edx
addl %edi, %ecx
cmpl %esi, %eax
jne .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2431:
.size _Z9getMatrixPfj, .-_Z9getMatrixPfj
.globl _Z5get_fPfj
.type _Z5get_fPfj, @function
_Z5get_fPfj:
.LFB2432:
.cfi_startproc
endbr64
testl %esi, %esi
je .L20
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,4), %rbp
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2432:
.size _Z5get_fPfj, .-_Z5get_fPfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "computeBMatrix doesn't get matrix\n"
.section .rodata.str1.1
.LC8:
.string "error on allocate memory\n"
.text
.globl _Z14computeBMatrixPfj
.type _Z14computeBMatrixPfj, @function
_Z14computeBMatrixPfj:
.LFB2433:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testq %rdi, %rdi
je .L40
movq %rdi, %rbx
movl %esi, %ebp
movl %esi, %r12d
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %rdi
testq %rax, %rax
je .L25
testl %ebp, %ebp
je .L27
leal 1(%rbp), %esi
leaq (%rax,%r12,4), %r8
movl $0, %edx
movss .LC5(%rip), %xmm1
.L28:
movl %edx, %ecx
movaps %xmm1, %xmm0
divss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%rax)
addl %esi, %edx
addq $4, %rax
cmpq %r8, %rax
jne .L28
movl $0, %esi
.L29:
movl %esi, %edx
movq %rdi, %rax
.L30:
movl %edx, %ecx
leaq (%rbx,%rcx,4), %rcx
movss (%rcx), %xmm0
mulss (%rax), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addl %ebp, %edx
cmpq %r8, %rax
jne .L30
leal 1(%rsi), %r9d
cmpl %r9d, %ebp
je .L34
movl %r9d, %esi
jmp .L29
.L40:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %edx, %ecx
leaq (%rbx,%rcx,4), %rcx
subss (%rcx), %xmm0
movss %xmm0, (%rcx)
leal 1(%rax), %ecx
addl %r9d, %edx
cmpl %eax, %esi
je .L41
movl %ecx, %eax
.L33:
movaps %xmm1, %xmm0
cmpl %eax, %r8d
jne .L32
movaps %xmm2, %xmm0
jmp .L32
.L41:
leal 1(%r8), %eax
cmpl %r8d, %esi
je .L27
movl %eax, %r8d
.L31:
movl %r8d, %edx
movl %r10d, %eax
jmp .L33
.L34:
movl $0, %r8d
movl $0, %r10d
pxor %xmm1, %xmm1
movss .LC5(%rip), %xmm2
jmp .L31
.L27:
call free@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2433:
.size _Z14computeBMatrixPfj, .-_Z14computeBMatrixPfj
.section .rodata.str1.8
.align 8
.LC9:
.string "compute_g get invalud arguments\n"
.text
.globl _Z9compute_gPfS_j
.type _Z9compute_gPfS_j, @function
_Z9compute_gPfS_j:
.LFB2434:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L43
testq %rsi, %rsi
je .L43
testl %edx, %edx
je .L50
leal 1(%rdx), %r8d
movq %rsi, %rax
movl %edx, %edx
leaq (%rsi,%rdx,4), %rsi
movl $0, %edx
movss .LC5(%rip), %xmm1
.L46:
movl %edx, %ecx
movaps %xmm1, %xmm0
divss (%rdi,%rcx,4), %xmm0
mulss (%rax), %xmm0
movss %xmm0, (%rax)
addl %r8d, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L46
ret
.L50:
ret
.L43:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2434:
.size _Z9compute_gPfS_j, .-_Z9compute_gPfS_j
.section .rodata.str1.8
.align 8
.LC10:
.string "precision get invalid parametr\n"
.text
.globl _Z9precisionPfS_S_j
.type _Z9precisionPfS_S_j, @function
_Z9precisionPfS_S_j:
.LFB2435:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %r11
testq %rsi, %rsi
sete %al
testq %rdx, %rdx
sete %dl
orb %dl, %al
jne .L52
movl %ecx, %r10d
testq %rdi, %rdi
je .L52
testl %ecx, %ecx
je .L58
movq %rsi, %r8
movl %ecx, %eax
leaq (%rsi,%rax,4), %rbx
movl %ecx, %esi
movl $0, %r9d
pxor %xmm2, %xmm2
movss .LC11(%rip), %xmm3
.L54:
movq %r11, %rdx
movl %r9d, %eax
pxor %xmm1, %xmm1
.L55:
movl %eax, %ecx
movss (%rdi,%rcx,4), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addl $1, %eax
addq $4, %rdx
cmpl %esi, %eax
jne .L55
movss (%r8), %xmm0
subss %xmm1, %xmm0
andps %xmm3, %xmm0
maxss %xmm2, %xmm0
movaps %xmm0, %xmm2
addq $4, %r8
addl %r10d, %r9d
addl %r10d, %esi
cmpq %rbx, %r8
jne .L54
.L51:
movaps %xmm2, %xmm0
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
pxor %xmm2, %xmm2
jmp .L51
.cfi_endproc
.LFE2435:
.size _Z9precisionPfS_S_j, .-_Z9precisionPfS_S_j
.globl _Z9transposePfj
.type _Z9transposePfj, @function
_Z9transposePfj:
.LFB2436:
.cfi_startproc
endbr64
testl %esi, %esi
je .L70
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leal 1(%rsi), %ebx
movl $0, %r9d
movl $0, %r10d
movl $0, %r11d
jmp .L64
.L67:
movl %r11d, %eax
movl %r10d, %edx
.L65:
movl %edx, %ecx
leaq (%rdi,%rcx,4), %r8
movss (%r8), %xmm0
movl %eax, %ecx
leaq (%rdi,%rcx,4), %rcx
movss (%rcx), %xmm1
movss %xmm1, (%r8)
movss %xmm0, (%rcx)
addl %esi, %edx
addl $1, %eax
cmpl %r9d, %eax
jne .L65
.L64:
addl $1, %r10d
addl %esi, %r11d
addl %ebx, %r9d
cmpl %r10d, %esi
je .L62
testl %r10d, %r10d
jne .L67
jmp .L64
.L62:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore 3
ret
.cfi_endproc
.LFE2436:
.size _Z9transposePfj, .-_Z9transposePfj
.section .rodata.str1.1
.LC12:
.string "Cuda Error : %s\n"
.text
.globl _Z17checkGPUOperationv
.type _Z17checkGPUOperationv, @function
_Z17checkGPUOperationv:
.LFB2437:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L76
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2437:
.size _Z17checkGPUOperationv, .-_Z17checkGPUOperationv
.globl _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
.type _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_, @function
_Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_:
.LFB2463:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6jacobiPfS_S_jS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2463:
.size _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_, .-_Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
.globl _Z6jacobiPfS_S_jS_
.type _Z6jacobiPfS_S_jS_, @function
_Z6jacobiPfS_S_jS_:
.LFB2464:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2464:
.size _Z6jacobiPfS_S_jS_, .-_Z6jacobiPfS_S_jS_
.section .rodata.str1.1
.LC13:
.string "precision : %f \n"
.LC15:
.string "success\n"
.text
.globl main
.type main, @function
main:
.LFB2438:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $4, %esi
movl $1024, %edi
call calloc@PLT
testq %r13, %r13
je .L86
movq %rax, %rbp
testq %r15, %r15
je .L86
testq %r12, %r12
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L86
testq %rbp, %rbp
je .L86
movl $1024, %esi
movq %r13, %rdi
call _Z9getMatrixPfj
movl $1024, %esi
movq %r12, %rdi
call _Z5get_fPfj
movl $4194304, %edx
movq %r13, %rsi
movq %r15, %rdi
call memcpy@PLT
movl $512, %ecx
movq 8(%rsp), %rdi
movq %r12, %rsi
rep movsq
movl $1024, %edx
movq 8(%rsp), %rbx
movq %rbx, %rsi
movq %r13, %rdi
call _Z9compute_gPfS_j
movl $1024, %esi
movq %r15, %rdi
call _Z14computeBMatrixPfj
movl $1024, %esi
movq %r15, %rdi
call _Z9transposePfj
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $3, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq .LC13(%rip), %r14
jmp .L94
.L86:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L85
.L90:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L100
.L91:
movq 40(%rsp), %rax
movq 32(%rsp), %rdx
movq %rdx, 40(%rsp)
movq %rax, 32(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L90
movq 40(%rsp), %r8
movl $1024, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
jmp .L90
.L100:
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1024, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z9precisionPfS_S_j
movss %xmm0, (%rsp)
cvtss2sd %xmm0, %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%rsp), %xmm1
comiss .LC14(%rip), %xmm1
jbe .L92
movss 4(%rsp), %xmm2
comiss %xmm1, %xmm2
jbe .L92
movss (%rsp), %xmm3
movss %xmm3, 4(%rsp)
.L94:
movl $512, %ebx
jmp .L91
.L92:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L85:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L101
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2438:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6jacobiPfS_S_jS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2466:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6jacobiPfS_S_jS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2466:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC2:
.long 1056964608
.align 4
.LC3:
.long 1092616192
.align 4
.LC4:
.long 1148846080
.align 4
.LC5:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC14:
.long 869711765
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#include <cuda_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess){
fprintf(stderr, "Cuda Error : %s\n", cudaGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
cudaMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
cudaMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
cudaMemcpy(dev_x_prev, host_x, size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), cudaMemcpyDeviceToDevice);
checkGPUOperation();
cudaMemcpy(dev_B, host_B, size * size * sizeof(float), cudaMemcpyHostToDevice);
checkGPUOperation();
cudaMemcpy(dev_g, host_g, size * sizeof(float), cudaMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
cudaDeviceSynchronize();
}
//get result
cudaMemcpy(host_x, dev_x_next, size * sizeof(float), cudaMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
cudaFree(dev_B);
cudaFree(dev_g);
cudaFree(dev_x_prev);
cudaFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess){
fprintf(stderr, "Cuda Error : %s\n", hipGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
hipMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
hipMemcpy(dev_x_prev, host_x, size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), hipMemcpyDeviceToDevice);
checkGPUOperation();
hipMemcpy(dev_B, host_B, size * size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_g, host_g, size * sizeof(float), hipMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
hipDeviceSynchronize();
}
//get result
hipMemcpy(host_x, dev_x_next, size * sizeof(float), hipMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
hipFree(dev_B);
hipFree(dev_g);
hipFree(dev_x_prev);
hipFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess){
fprintf(stderr, "Cuda Error : %s\n", hipGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
hipMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
hipMemcpy(dev_x_prev, host_x, size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), hipMemcpyDeviceToDevice);
checkGPUOperation();
hipMemcpy(dev_B, host_B, size * size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_g, host_g, size * sizeof(float), hipMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
hipDeviceSynchronize();
}
//get result
hipMemcpy(host_x, dev_x_next, size * sizeof(float), hipMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
hipFree(dev_B);
hipFree(dev_g);
hipFree(dev_x_prev);
hipFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6jacobiPfS_S_jS_
.globl _Z6jacobiPfS_S_jS_
.p2align 8
.type _Z6jacobiPfS_S_jS_,@function
_Z6jacobiPfS_S_jS_:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_gt_u32 s2, 0x400
s_cbranch_scc1 .LBB0_3
v_cvt_f32_u32_e32 v1, s2
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x44800000, v2
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v3, -v2, v1, 0x44800000
v_cvt_u32_f32_e32 v2, v2
v_cmp_ge_f32_e64 s6, |v3|, |v1|
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s7, v2
s_cmp_lg_u32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s4, s4, v3
v_add_co_ci_u32_e64 v2, null, s5, 0, s4
s_addc_u32 s5, s7, 0
s_lshl_b32 s4, s2, 2
s_and_b32 s5, s5, 0xffff
s_mov_b32 s6, s3
.LBB0_2:
global_load_b32 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s5
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
v_add_nc_u32_e32 v3, s4, v3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b32 s4, s[0:1], 0x18
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_mov_b32 s6, s4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_add_i32 s6, s6, -1
v_add_nc_u32_e32 v2, s4, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v5, s5
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s6, 0
ds_load_b32 v5, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, v4, v5
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v0, v3
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6jacobiPfS_S_jS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6jacobiPfS_S_jS_, .Lfunc_end0-_Z6jacobiPfS_S_jS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6jacobiPfS_S_jS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6jacobiPfS_S_jS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_fp16.h>
#define EPS 0.0000001f
#define SIZE 1024
#define BIG_VALUE 65536
#define BLOCK_SIZE 256
// generate random matrix
void getMatrix(float* matrix, unsigned size)
{
if (matrix == NULL){
fprintf(stderr, "getMatrix doesn't get matrix\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
matrix[i + size * j] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// add diagonal predominance
for (unsigned i = 0; i < size; i++) {
matrix[i + size * i] += 1000;
}
}
// generate random vector
void get_f(float *f, unsigned size)
{
if (get_f == NULL){
fprintf(stderr, "get_f doen't get vector\n");
exit(-1);
}
for (unsigned i = 0; i < size; i++) {
f[i] = (((float)rand() / RAND_MAX) - 0.5f) * 10;
}
}
// compute Matrix B, and return result in argument
void computeBMatrix(float *A, unsigned size)
{
if (A == NULL){
fprintf(stderr, "computeBMatrix doesn't get matrix\n");
exit(-1);
}
float *inverse_D = (float *)calloc(size, sizeof(float));
if (inverse_D == NULL){
fprintf(stderr, "error on allocate memory\n");
exit(-1);
}
//D = diag(A)
//compute D^-1
for (unsigned i = 0; i < size; i++) {
inverse_D[i] = 1.0f / A[i + size * i];
}
//compute D^-1 * A
for (unsigned i = 0; i < size; i++) { //columns
for (unsigned j = 0; j < size; j++) { //lines
A[i + size * j] = inverse_D[j] * A[i + size * j];
}
}
//compute I - D^-1 * A
for (unsigned i = 0; i < size; i++) {
for (unsigned j = 0; j < size; j++) {
float tmp = (i == j) ? 1 : 0;
A[i + size * j] = tmp - A[i + size * j];
}
}
free(inverse_D);
}
// compute vector g and return in argument
void compute_g(float *A, float* b, unsigned size)
{
if (A == NULL || b == NULL){
fprintf(stderr, "compute_g get invalud arguments\n");
exit(-1);
}
// g = diag(A) ^ -1 * b;
for (unsigned i = 0; i < size; i++) {
b[i] = (1.0f / A[i + size * i]) * b[i];
}
}
// metric is : max(|Ax_i - f_i|)
float precision(float *matrix, float *f, float* x, unsigned size)
{
if (matrix == NULL || f == NULL || x == NULL){
fprintf(stderr, "precision get invalid parametr\n");
exit(-1);
}
float max = 0;
for (unsigned i = 0; i < size; i++) {
float cur = 0;
for (unsigned j = 0; j < size; j++) {
cur += matrix[j + size * i] * x[j];
}
cur = fabs(f[i] - cur);
max = max < cur ? cur : max;
}
return max;
}
// cuda kernel
//with transpose matrix B
__global__ void jacobi(float* B, float* g, float* x, unsigned size, float* x_next)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float x_curr = 0;
__shared__ float shared_x[SIZE];
for (int i = 0; i < SIZE / blockDim.x; i++){
int loc_idx = blockDim.x * i + threadIdx.x;
shared_x[loc_idx] = x[loc_idx];
}
__syncthreads();
#pragma uroll 16
for (int i = 0; i < size; i++) {
// here loc_i is useless, becouse matrix B
x_curr += B[idx + i * size] * shared_x[i];
}
x_next[idx] = x_curr + g[idx];
}
void transpose(float* matrix, unsigned size)
{
for (unsigned i = 0; i < size; i++){
for (unsigned j = 0; j < i; j++){
//swap value
float tmp = matrix[i + j * size];
matrix[i + j * size] = matrix[j + i * size];
matrix[j + i * size] = tmp;
}
}
}
void checkGPUOperation()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess){
fprintf(stderr, "Cuda Error : %s\n", hipGetErrorString(code));
exit(-1);
}
}
int main()
{
float eps = EPS;
unsigned size = SIZE;
// alloc memory on CPU
float *host_A = (float *)malloc(size * size * sizeof(float));
float *host_B = (float *)malloc(size * size * sizeof(float));
float *host_f = (float *)malloc(size * sizeof(float));
float *host_g = (float *)malloc(size * sizeof(float));
float *host_x = (float *)calloc(size, sizeof(float)); // start with null vector
if (host_A == NULL || host_B == NULL || host_f == NULL
|| host_g == NULL || host_x == NULL){
fprintf(stderr, "error on allocate memory\n");
return -1;
}
getMatrix(host_A, size);
get_f(host_f, size);
memcpy(host_B, host_A, size * size * sizeof(float));
memcpy(host_g, host_f, size * sizeof(float));
compute_g(host_A, host_g, size);
computeBMatrix(host_B, size);
transpose(host_B, size); // transpose for optimization
// alloc memory on GPU
float *dev_B, *dev_g, *dev_x_prev, *dev_x_next;
hipMalloc((void **)&dev_B, size * size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_g, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_prev, size * sizeof(float));
checkGPUOperation();
hipMalloc((void **)&dev_x_next, size * sizeof(float));
checkGPUOperation();
//copy memory from CPU to GPU
hipMemcpy(dev_x_prev, host_x, size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_x_next, dev_x_prev, size * sizeof(float), hipMemcpyDeviceToDevice);
checkGPUOperation();
hipMemcpy(dev_B, host_B, size * size * sizeof(float), hipMemcpyHostToDevice);
checkGPUOperation();
hipMemcpy(dev_g, host_g, size * sizeof(float), hipMemcpyHostToDevice);
float p = 0; //precision
float prev_p = BIG_VALUE; //previos precision
// when precision stop decrease stop compute
do {
for (int i = 0; i < 512; i++) {
//swap vectors
float *tmp = dev_x_next;
dev_x_next = dev_x_prev;
dev_x_prev = tmp;
jacobi <<<dim3(size / BLOCK_SIZE), dim3(BLOCK_SIZE)>>> (dev_B, dev_g, dev_x_prev, size, dev_x_next);
hipDeviceSynchronize();
}
//get result
hipMemcpy(host_x, dev_x_next, size * sizeof(float), hipMemcpyDeviceToHost);
checkGPUOperation();
prev_p = p;
p = precision(host_A, host_f, host_x, size);
printf("precision : %f \n", p);
} while (p > eps && p < prev_p);
printf("success\n");
//free memory on CPU
free(host_A);
free(host_B);
free(host_f);
free(host_g);
free(host_x);
//free memory on GPU
hipFree(dev_B);
hipFree(dev_g);
hipFree(dev_x_prev);
hipFree(dev_x_next);
#ifdef _WIN32
// stop console
// only Windows needed
scanf("\n");
#endif
return 0;
} | .text
.file "jacobi.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9getMatrixPfj
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0xbf000000 # float -0.5
.LCPI0_2:
.long 0x41200000 # float 10
.LCPI0_3:
.long 0x447a0000 # float 1000
.text
.globl _Z9getMatrixPfj
.p2align 4, 0x90
.type _Z9getMatrixPfj,@function
_Z9getMatrixPfj: # @_Z9getMatrixPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testq %rdi, %rdi
je .LBB0_9
# %bb.1: # %.preheader22
movl %esi, %ebx
testl %esi, %esi
je .LBB0_8
# %bb.2: # %.preheader21.preheader
movq %rdi, %r14
movl %ebx, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %r15, %r12
movl %ebp, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movl %r13d, %eax
movss %xmm0, (%r14,%rax,4)
addl %ebx, %r13d
decq %r12
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
incl %ebp
cmpl %ebx, %ebp
jne .LBB0_3
# %bb.6: # %.lr.ph
incl %ebx
xorl %eax, %eax
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%r14,%rcx,4)
addl %ebx, %eax
decq %r15
jne .LBB0_7
.LBB0_8: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $29, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z9getMatrixPfj, .Lfunc_end0-_Z9getMatrixPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z5get_fPfj
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0xbf000000 # float -0.5
.LCPI1_2:
.long 0x41200000 # float 10
.text
.globl _Z5get_fPfj
.p2align 4, 0x90
.type _Z5get_fPfj,@function
_Z5get_fPfj: # @_Z5get_fPfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z5get_fPfj, .Lfunc_end1-_Z5get_fPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14computeBMatrixPfj
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl _Z14computeBMatrixPfj
.p2align 4, 0x90
.type _Z14computeBMatrixPfj,@function
_Z14computeBMatrixPfj: # @_Z14computeBMatrixPfj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testq %rdi, %rdi
je .LBB2_1
# %bb.3:
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
movl $4, %esi
movq %r15, %rdi
callq calloc
testq %rax, %rax
je .LBB2_18
# %bb.4: # %.preheader55
testl %ebx, %ebx
je .LBB2_17
# %bb.5: # %.lr.ph
leal 1(%rbx), %ecx
xorl %edx, %edx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl %edx, %edi
movaps %xmm0, %xmm1
divss (%r14,%rdi,4), %xmm1
movss %xmm1, (%rax,%rsi,4)
incq %rsi
addl %ecx, %edx
cmpq %rsi, %r15
jne .LBB2_6
# %bb.7: # %.preheader53.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_8: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movl %ecx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, %edi
mulss (%r14,%rdi,4), %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %rsi
addl %ebx, %edx
cmpq %rsi, %r15
jne .LBB2_9
# %bb.10: # in Loop: Header=BB2_8 Depth=1
incl %ecx
cmpl %r15d, %ecx
jne .LBB2_8
# %bb.11: # %.preheader.preheader
xorl %ecx, %ecx
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_12 Depth=1
incq %rcx
cmpq %r15, %rcx
je .LBB2_17
.LBB2_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
movl %ecx, %edx
xorl %esi, %esi
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=2
movl %edx, %edi
subss (%r14,%rdi,4), %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %rsi
addl %ebx, %edx
cmpq %rsi, %r15
je .LBB2_16
.LBB2_13: # Parent Loop BB2_12 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm1
cmpq %rsi, %rcx
je .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=2
xorps %xmm1, %xmm1
jmp .LBB2_15
.LBB2_17: # %._crit_edge
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $34, %esi
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
.LBB2_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14computeBMatrixPfj, .Lfunc_end2-_Z14computeBMatrixPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9compute_gPfS_j
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl _Z9compute_gPfS_j
.p2align 4, 0x90
.type _Z9compute_gPfS_j,@function
_Z9compute_gPfS_j: # @_Z9compute_gPfS_j
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB3_6
# %bb.1:
testq %rsi, %rsi
je .LBB3_6
# %bb.2: # %.preheader
testl %edx, %edx
je .LBB3_5
# %bb.3: # %.lr.ph
movl %edx, %eax
incl %edx
xorl %ecx, %ecx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movl %ecx, %r9d
movaps %xmm0, %xmm1
divss (%rdi,%r9,4), %xmm1
mulss (%rsi,%r8,4), %xmm1
movss %xmm1, (%rsi,%r8,4)
incq %r8
addl %edx, %ecx
cmpq %r8, %rax
jne .LBB3_4
.LBB3_5: # %._crit_edge
retq
.LBB3_6:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $32, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z9compute_gPfS_j, .Lfunc_end3-_Z9compute_gPfS_j
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z9precisionPfS_S_j
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z9precisionPfS_S_j
.p2align 4, 0x90
.type _Z9precisionPfS_S_j,@function
_Z9precisionPfS_S_j: # @_Z9precisionPfS_S_j
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB4_5
# %bb.1:
testq %rsi, %rsi
je .LBB4_5
# %bb.2:
testq %rdx, %rdx
je .LBB4_5
# %bb.3: # %.preheader33
testl %ecx, %ecx
je .LBB4_4
# %bb.6: # %.preheader.preheader
movl %ecx, %eax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
xorl %r9d, %r9d
xorps %xmm3, %xmm3
.p2align 4, 0x90
.LBB4_8: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%r9), %r10d
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%r9,4), %xmm0
addss %xmm0, %xmm3
incq %r9
cmpq %r9, %rax
jne .LBB4_8
# %bb.9: # in Loop: Header=BB4_7 Depth=1
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss %xmm3, %xmm0
andps %xmm1, %xmm0
maxss %xmm2, %xmm0
incq %r8
addq %rax, %rcx
movaps %xmm0, %xmm2
cmpq %rax, %r8
jne .LBB4_7
# %bb.10: # %._crit_edge
retq
.LBB4_4:
xorps %xmm0, %xmm0
retq
.LBB4_5:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $31, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end4:
.size _Z9precisionPfS_S_j, .Lfunc_end4-_Z9precisionPfS_S_j
.cfi_endproc
# -- End function
.globl _Z21__device_stub__jacobiPfS_S_jS_ # -- Begin function _Z21__device_stub__jacobiPfS_S_jS_
.p2align 4, 0x90
.type _Z21__device_stub__jacobiPfS_S_jS_,@function
_Z21__device_stub__jacobiPfS_S_jS_: # @_Z21__device_stub__jacobiPfS_S_jS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6jacobiPfS_S_jS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end5:
.size _Z21__device_stub__jacobiPfS_S_jS_, .Lfunc_end5-_Z21__device_stub__jacobiPfS_S_jS_
.cfi_endproc
# -- End function
.globl _Z9transposePfj # -- Begin function _Z9transposePfj
.p2align 4, 0x90
.type _Z9transposePfj,@function
_Z9transposePfj: # @_Z9transposePfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB6_6
# %bb.1: # %.preheader.preheader
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %rdx
addq %rax, %rcx
cmpq %rax, %rdx
je .LBB6_6
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testq %rdx, %rdx
je .LBB6_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
movl %edx, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, %r10d
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rcx,%r9), %r11d
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rdi,%r10,4)
movss %xmm0, (%rdi,%r11,4)
incq %r9
addl %esi, %r8d
cmpq %r9, %rdx
jne .LBB6_4
jmp .LBB6_5
.LBB6_6: # %._crit_edge26
retq
.Lfunc_end6:
.size _Z9transposePfj, .Lfunc_end6-_Z9transposePfj
.cfi_endproc
# -- End function
.globl _Z17checkGPUOperationv # -- Begin function _Z17checkGPUOperationv
.p2align 4, 0x90
.type _Z17checkGPUOperationv,@function
_Z17checkGPUOperationv: # @_Z17checkGPUOperationv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipGetLastError
testl %eax, %eax
jne .LBB7_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB7_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z17checkGPUOperationv, .Lfunc_end7-_Z17checkGPUOperationv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI8_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI8_1:
.long 0xbf000000 # float -0.5
.LCPI8_2:
.long 0x41200000 # float 10
.LCPI8_3:
.long 0x447a0000 # float 1000
.LCPI8_4:
.long 0x3f800000 # float 1
.LCPI8_6:
.long 0x33d6bf95 # float 1.00000001E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI8_5:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
movl $4, %esi
callq calloc
testq %rbp, %rbp
je .LBB8_41
# %bb.1:
testq %rbx, %rbx
je .LBB8_41
# %bb.2:
testq %r15, %r15
je .LBB8_41
# %bb.3:
testq %r14, %r14
je .LBB8_41
# %bb.4:
movq %rax, %r13
testq %rax, %rax
je .LBB8_41
# %bb.5: # %.preheader21.i.preheader
movq %r14, 56(%rsp) # 8-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq %rbp, %r14
.p2align 4, 0x90
.LBB8_6: # %.preheader21.i
# =>This Loop Header: Depth=1
# Child Loop BB8_7 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_7: # Parent Loop BB8_6 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI8_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
movss .LCPI8_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r12)
addq $4096, %r12 # imm = 0x1000
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB8_7
# %bb.8: # in Loop: Header=BB8_6 Depth=1
incl %ebx
addq $4, %r14
cmpl $1024, %ebx # imm = 0x400
jne .LBB8_6
# %bb.9: # %.preheader.i.preheader
xorl %eax, %eax
movss .LCPI8_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB8_10: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movss (%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rbp,%rax)
addq $4100, %rax # imm = 0x1004
cmpq $4198400, %rax # imm = 0x401000
jne .LBB8_10
# %bb.11: # %.lr.ph.i.preheader
xorl %ebx, %ebx
movq 64(%rsp), %r14 # 8-byte Reload
movq 56(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB8_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI8_0(%rip), %xmm0
addss .LCPI8_1(%rip), %xmm0
mulss .LCPI8_2(%rip), %xmm0
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB8_12
# %bb.13: # %_Z5get_fPfj.exit
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movq %rbp, %rsi
callq memcpy@PLT
movl $4096, %edx # imm = 0x1000
movq %r12, %rdi
movq %r15, %rsi
callq memcpy@PLT
xorl %eax, %eax
movss .LCPI8_4(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbp, %rcx
.p2align 4, 0x90
.LBB8_14: # =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm1
divss (%rcx), %xmm1
mulss (%r12,%rax,4), %xmm1
movss %xmm1, (%r12,%rax,4)
incq %rax
addq $4100, %rcx # imm = 0x1004
cmpq $1024, %rax # imm = 0x400
jne .LBB8_14
# %bb.15: # %_Z9compute_gPfS_j.exit
movq %r14, %rdi
movl $1024, %esi # imm = 0x400
callq _Z14computeBMatrixPfj
xorl %eax, %eax
movq %r14, %rcx
movq %r14, %rdx
jmp .LBB8_16
.p2align 4, 0x90
.LBB8_19: # %._crit_edge.i
# in Loop: Header=BB8_16 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4, %rcx
cmpq $1024, %rax # imm = 0x400
je .LBB8_20
.LBB8_16: # %.preheader.i89
# =>This Loop Header: Depth=1
# Child Loop BB8_18 Depth 2
testq %rax, %rax
je .LBB8_19
# %bb.17: # %.lr.ph.i91
# in Loop: Header=BB8_16 Depth=1
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_18: # Parent Loop BB8_16 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rdx,%rdi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rsi)
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq %rdi, %rax
jne .LBB8_18
jmp .LBB8_19
.LBB8_20: # %_Z9transposePfj.exit
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.21: # %_Z17checkGPUOperationv.exit
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.22: # %_Z17checkGPUOperationv.exit98
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.23: # %_Z17checkGPUOperationv.exit100
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.24: # %_Z17checkGPUOperationv.exit102
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.25: # %_Z17checkGPUOperationv.exit104
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $3, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.26: # %_Z17checkGPUOperationv.exit106
movq %rbp, 72(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.27: # %_Z17checkGPUOperationv.exit108
movabsq $4294967300, %rbp # imm = 0x100000004
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
leaq 252(%rbp), %r14
leaq 160(%rsp), %r12
.p2align 4, 0x90
.LBB8_28: # =>This Loop Header: Depth=1
# Child Loop BB8_29 Depth 2
# Child Loop BB8_34 Depth 2
# Child Loop BB8_35 Depth 3
movl $512, %ebx # imm = 0x200
jmp .LBB8_29
.p2align 4, 0x90
.LBB8_31: # in Loop: Header=BB8_29 Depth=2
callq hipDeviceSynchronize
decl %ebx
je .LBB8_32
.LBB8_29: # Parent Loop BB8_28 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_31
# %bb.30: # in Loop: Header=BB8_29 Depth=2
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $1024, 52(%rsp) # imm = 0x400
movq %rsi, 128(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z6jacobiPfS_S_jS_, %edi
movq %r12, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB8_31
.p2align 4, 0x90
.LBB8_32: # in Loop: Header=BB8_28 Depth=1
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.33: # %.preheader.i112.preheader
# in Loop: Header=BB8_28 Depth=1
xorps %xmm0, %xmm0
movq 72(%rsp), %rax # 8-byte Reload
xorl %ecx, %ecx
movaps .LCPI8_5(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB8_34: # %.preheader.i112
# Parent Loop BB8_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_35 Depth 3
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB8_35: # Parent Loop BB8_28 Depth=1
# Parent Loop BB8_34 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss (%r13,%rdx,4), %xmm2
addss %xmm2, %xmm1
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB8_35
# %bb.36: # in Loop: Header=BB8_34 Depth=2
movss (%r15,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
andps %xmm3, %xmm2
maxss %xmm0, %xmm2
incq %rcx
addq $4096, %rax # imm = 0x1000
movaps %xmm2, %xmm0
cmpq $1024, %rcx # imm = 0x400
jne .LBB8_34
# %bb.37: # %_Z9precisionPfS_S_j.exit
# in Loop: Header=BB8_28 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.6, %edi
movb $1, %al
movaps %xmm2, 208(%rsp) # 16-byte Spill
callq printf
movaps 208(%rsp), %xmm1 # 16-byte Reload
ucomiss .LCPI8_6(%rip), %xmm1
jbe .LBB8_39
# %bb.38: # %_Z9precisionPfS_S_j.exit
# in Loop: Header=BB8_28 Depth=1
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss %xmm1, 28(%rsp) # 4-byte Spill
ja .LBB8_28
.LBB8_39:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB8_40:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_41:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %eax
jmp .LBB8_40
.LBB8_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6jacobiPfS_S_jS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "getMatrix doesn't get matrix\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "computeBMatrix doesn't get matrix\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error on allocate memory\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "compute_g get invalud arguments\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "precision get invalid parametr\n"
.size .L.str.4, 32
.type _Z6jacobiPfS_S_jS_,@object # @_Z6jacobiPfS_S_jS_
.section .rodata,"a",@progbits
.globl _Z6jacobiPfS_S_jS_
.p2align 3, 0x0
_Z6jacobiPfS_S_jS_:
.quad _Z21__device_stub__jacobiPfS_S_jS_
.size _Z6jacobiPfS_S_jS_, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Cuda Error : %s\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "precision : %f \n"
.size .L.str.6, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6jacobiPfS_S_jS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "success"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__jacobiPfS_S_jS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6jacobiPfS_S_jS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6jacobiPfS_S_jS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, 0x400, PT ; /* 0x000004000200780c */
/* 0x000fe20003f04070 */
/*0060*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fd800078e0203 */
/*0070*/ @P0 BRA 0xc00 ; /* 0x00000b8000000947 */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fce0003f45070 */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*00e0*/ IADD3 R9, RZ, -R7, RZ ; /* 0x80000007ff097210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*0110*/ IMAD.HI.U32 R7, R7, 0x400, RZ ; /* 0x0000040007077827 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R9, -R7, RZ, RZ ; /* 0x000000ff07097210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R8, R2, R9, 0x400 ; /* 0x0000040002087424 */
/* 0x000fca00078e0209 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R8, R8, -c[0x0][0x0], RZ ; /* 0x8000000008080a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fe20003f26070 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd800078e00ff */
/*0190*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff07aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IMNMX.U32 R7, R7, 0x1, !PT ; /* 0x0000000107077817 */
/* 0x000fc80007800000 */
/*01c0*/ IADD3 R5, R7.reuse, -0x1, RZ ; /* 0xffffffff07057810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe400078ec0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 BRA 0xb30 ; /* 0x0000093000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R9, R7, -R6, RZ ; /* 0x8000000607097210 */
/* 0x000fe20007ffe0ff */
/*0210*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0220*/ IMAD.SHL.U32 R29, R3, 0x4, RZ ; /* 0x00000004031d7824 */
/* 0x000fe400078e00ff */
/*0230*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fd800078e0003 */
/*0250*/ @!P0 BRA 0x9d0 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0280*/ @!P1 BRA 0x730 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fd400000001ff */
/*02b0*/ IMAD.WIDE R18, R7, R16, c[0x0][0x170] ; /* 0x00005c0007127625 */
/* 0x002fca00078e0210 */
/*02c0*/ LDG.E R10, [R18.64] ; /* 0x00000006120a7981 */
/* 0x0000a2000c1e1900 */
/*02d0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fca00078e0212 */
/*02e0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x0002e4000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R2, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x002fca00078e020e */
/*0300*/ LDG.E R21, [R14.64] ; /* 0x000000060e157981 */
/* 0x000322000c1e1900 */
/*0310*/ IMAD R5, R2.reuse, 0x4, R7 ; /* 0x0000000402057824 */
/* 0x040fe400078e0207 */
/*0320*/ IMAD.WIDE R22, R2, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x000fc800078e020e */
/*0330*/ IMAD.WIDE R12, R5, R16, c[0x0][0x170] ; /* 0x00005c00050c7625 */
/* 0x000fe400078e0210 */
/*0340*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000b22000c1e1900 */
/*0350*/ LEA R5, R2, R5, 0x2 ; /* 0x0000000502057211 */
/* 0x000fc600078e10ff */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fe400078e020c */
/*0370*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000324000c1e1900 */
/*0380*/ IMAD.WIDE R26, R5, R16, c[0x0][0x170] ; /* 0x00005c00051a7625 */
/* 0x000fc800078e0210 */
/*0390*/ IMAD R5, R2.reuse, 0x4, R5 ; /* 0x0000000402057824 */
/* 0x040fe400078e0205 */
/*03a0*/ IMAD.WIDE R18, R2.reuse, 0x4, R24 ; /* 0x0000000402127825 */
/* 0x041fe400078e0218 */
/*03b0*/ LDG.E R25, [R24.64] ; /* 0x0000000618197981 */
/* 0x000124000c1e1900 */
/*03c0*/ IMAD.WIDE R16, R5, R16, c[0x0][0x170] ; /* 0x00005c0005107625 */
/* 0x000fe400078e0210 */
/*03d0*/ LDG.E R7, [R18.64] ; /* 0x0000000612077981 */
/* 0x000b24000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R2, 0x4, R26 ; /* 0x00000004020e7825 */
/* 0x002fc400078e021a */
/*03f0*/ LDG.E R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000328000c1e1900 */
/*0400*/ LDG.E R24, [R14.64] ; /* 0x000000060e187981 */
/* 0x001122000c1e1900 */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R18 ; /* 0x0000000402127825 */
/* 0x020fc600078e0212 */
/*0420*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000b22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x002fc800078e0210 */
/*0440*/ IMAD.WIDE R14, R2.reuse, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x041fe200078e020e */
/*0450*/ LDG.E R12, [R16.64] ; /* 0x00000006100c7981 */
/* 0x000128000c1e1900 */
/*0460*/ LDG.E R27, [R18.64] ; /* 0x00000006121b7981 */
/* 0x020368000c1e1900 */
/*0470*/ LDG.E R22, [R14.64] ; /* 0x000000060e167981 */
/* 0x000162000c1e1900 */
/*0480*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc800078e0210 */
/*0490*/ IMAD.WIDE R14, R2.reuse, 0x4, R14 ; /* 0x00000004020e7825 */
/* 0x041fe200078e020e */
/*04a0*/ LDG.E R28, [R18.64] ; /* 0x00000006121c7981 */
/* 0x00016a000c1e1900 */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000362000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R2, 0x4, R18 ; /* 0x0000000402127825 */
/* 0x001fcc00078e0212 */
/*04d0*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000162000c1e1900 */
/*04e0*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0500*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*0510*/ STS [R29], R10 ; /* 0x0000000a1d007388 */
/* 0x0045e40000000800 */
/*0520*/ LEA R29, R2, R29, 0x2 ; /* 0x0000001d021d7211 */
/* 0x004fca00078e10ff */
/*0530*/ IMAD R10, R2.reuse, 0x4, R29 ; /* 0x00000004020a7824 */
/* 0x040fe200078e021d */
/*0540*/ STS [R29], R11 ; /* 0x0000000b1d007388 */
/* 0x0085e80000000800 */
/*0550*/ LEA R11, R2.reuse, R10, 0x2 ; /* 0x0000000a020b7211 */
/* 0x044fe200078e10ff */
/*0560*/ STS [R10], R21 ; /* 0x000000150a007388 */
/* 0x0105e80000000800 */
/*0570*/ IMAD R19, R2, 0x4, R11 ; /* 0x0000000402137824 */
/* 0x001fca00078e020b */
/*0580*/ LEA R21, R2, R19, 0x2 ; /* 0x0000001302157211 */
/* 0x004fca00078e10ff */
/*0590*/ IMAD R15, R2, 0x4, R21 ; /* 0x00000004020f7824 */
/* 0x002fca00078e0215 */
/*05a0*/ LEA R16, R2.reuse, R15, 0x2 ; /* 0x0000000f02107211 */
/* 0x040fe200078e10ff */
/*05b0*/ STS [R11], R23 ; /* 0x000000170b007388 */
/* 0x000fe80000000800 */
/*05c0*/ IMAD R17, R2.reuse, 0x4, R16 ; /* 0x0000000402117824 */
/* 0x040fe200078e0210 */
/*05d0*/ STS [R19], R13 ; /* 0x0000000d13007388 */
/* 0x0001e80000000800 */
/*05e0*/ LEA R13, R2, R17, 0x2 ; /* 0x00000011020d7211 */
/* 0x001fca00078e10ff */
/*05f0*/ IMAD R29, R2, 0x4, R13 ; /* 0x00000004021d7824 */
/* 0x000fca00078e020d */
/*0600*/ LEA R11, R2.reuse, R29, 0x2 ; /* 0x0000001d020b7211 */
/* 0x040fe200078e10ff */
/*0610*/ STS [R21], R25 ; /* 0x0000001915007388 */
/* 0x000fe80000000800 */
/*0620*/ IMAD R10, R2.reuse, 0x4, R11 ; /* 0x00000004020a7824 */
/* 0x040fe200078e020b */
/*0630*/ STS [R15], R7 ; /* 0x000000070f007388 */
/* 0x0001e80000000800 */
/*0640*/ LEA R15, R2.reuse, R10, 0x2 ; /* 0x0000000a020f7211 */
/* 0x041fe200078e10ff */
/*0650*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x020fe80000000800 */
/*0660*/ IMAD R23, R2.reuse, 0x4, R15 ; /* 0x0000000402177824 */
/* 0x040fe200078e020f */
/*0670*/ STS [R17], R26 ; /* 0x0000001a11007388 */
/* 0x000fe80000000800 */
/*0680*/ STS [R13], R24 ; /* 0x000000180d007388 */
/* 0x000fe20000000800 */
/*0690*/ LEA R19, R2, R23, 0x2 ; /* 0x0000001702137211 */
/* 0x000fc600078e10ff */
/*06a0*/ STS [R29], R22 ; /* 0x000000161d007388 */
/* 0x0001e80000000800 */
/*06b0*/ STS [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0003e80000000800 */
/*06c0*/ STS [R10], R20 ; /* 0x000000140a007388 */
/* 0x0003e80000000800 */
/*06d0*/ STS [R15], R12 ; /* 0x0000000c0f007388 */
/* 0x0003e80000000800 */
/*06e0*/ STS [R23], R28 ; /* 0x0000001c17007388 */
/* 0x0003e80000000800 */
/*06f0*/ STS [R19], R18 ; /* 0x0000001213007388 */
/* 0x0003e20000000800 */
/*0700*/ IMAD R7, R2.reuse, 0x4, R5 ; /* 0x0000000402077824 */
/* 0x040fe200078e0205 */
/*0710*/ LEA R29, R2, R19, 0x2 ; /* 0x00000013021d7211 */
/* 0x001fe200078e10ff */
/*0720*/ @P1 BRA 0x2a0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0740*/ @!P1 BRA 0x9b0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x002fe200078e00ff */
/*0760*/ LEA R5, R2, R7, 0x2 ; /* 0x0000000702057211 */
/* 0x000fc600078e10ff */
/*0770*/ IMAD.WIDE R22, R7, R10, c[0x0][0x170] ; /* 0x00005c0007167625 */
/* 0x000fc800078e020a */
/*0780*/ IMAD.WIDE R10, R5, R10, c[0x0][0x170] ; /* 0x00005c00050a7625 */
/* 0x000fc800078e020a */
/*0790*/ IMAD.WIDE R12, R2.reuse, 0x4, R22 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0216 */
/*07a0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x0000a4000c1e1900 */
/*07b0*/ IMAD.WIDE R14, R2.reuse, 0x4, R10 ; /* 0x00000004020e7825 */
/* 0x040fe400078e020a */
/*07c0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x0002e4000c1e1900 */
/*07d0*/ IMAD.WIDE R16, R2.reuse, 0x4, R12 ; /* 0x0000000402107825 */
/* 0x040fe400078e020c */
/*07e0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000964000c1e1900 */
/*07f0*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fc400078e020e */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD.WIDE R20, R2.reuse, 0x4, R16 ; /* 0x0000000402147825 */
/* 0x040fe400078e0210 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x0000e4000c1e1900 */
/*0830*/ IMAD.WIDE R24, R2.reuse, 0x4, R18 ; /* 0x0000000402187825 */
/* 0x040fe400078e0212 */
/*0840*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ee8000c1e1900 */
/*0850*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000ee2000c1e1900 */
/*0870*/ IMAD R7, R2, 0x4, R29 ; /* 0x0000000402077824 */
/* 0x000fca00078e021d */
/*0880*/ LEA R27, R2, R7, 0x2 ; /* 0x00000007021b7211 */
/* 0x000fca00078e10ff */
/*0890*/ IMAD R23, R2, 0x4, R27 ; /* 0x0000000402177824 */
/* 0x001fca00078e021b */
/*08a0*/ LEA R13, R2, R23, 0x2 ; /* 0x00000017020d7211 */
/* 0x010fca00078e10ff */
/*08b0*/ IMAD R17, R2, 0x4, R13 ; /* 0x0000000402117824 */
/* 0x000fca00078e020d */
/*08c0*/ LEA R26, R2, R17, 0x2 ; /* 0x00000011021a7211 */
/* 0x000fca00078e10ff */
/*08d0*/ IMAD R11, R2, 0x4, R26 ; /* 0x00000004020b7824 */
/* 0x002fe200078e021a */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0910*/ STS [R29], R22 ; /* 0x000000161d007388 */
/* 0x004fe80000000800 */
/*0920*/ STS [R7], R12 ; /* 0x0000000c07007388 */
/* 0x0201e80000000800 */
/*0930*/ STS [R27], R16 ; /* 0x000000101b007388 */
/* 0x0083e80000000800 */
/*0940*/ STS [R23], R20 ; /* 0x0000001417007388 */
/* 0x0003e80000000800 */
/*0950*/ STS [R13], R10 ; /* 0x0000000a0d007388 */
/* 0x0003e80000000800 */
/*0960*/ STS [R17], R14 ; /* 0x0000000e11007388 */
/* 0x0003e80000000800 */
/*0970*/ STS [R26], R18 ; /* 0x000000121a007388 */
/* 0x0003e80000000800 */
/*0980*/ STS [R11], R24 ; /* 0x000000180b007388 */
/* 0x0003e20000000800 */
/*0990*/ LEA R7, R2.reuse, R5, 0x2 ; /* 0x0000000502077211 */
/* 0x041fe200078e10ff */
/*09a0*/ IMAD R29, R2, 0x4, R11 ; /* 0x00000004021d7824 */
/* 0x000fc400078e020b */
/*09b0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*09c0*/ @!P0 BRA 0xb30 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*09d0*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x002fca0000000f00 */
/*09e0*/ IMAD.WIDE R14, R7, R14, c[0x0][0x170] ; /* 0x00005c00070e7625 */
/* 0x000fcc00078e020e */
/*09f0*/ IMAD.WIDE R16, R2.reuse, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x040fe400078e020e */
/*0a00*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee8000c1e1900 */
/*0a30*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc400078e020c */
/*0a40*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f62000c1e1900 */
/*0a60*/ IMAD R5, R2, 0x4, R29 ; /* 0x0000000402057824 */
/* 0x000fca00078e021d */
/*0a70*/ LEA R19, R2, R5, 0x2 ; /* 0x0000000502137211 */
/* 0x000fca00078e10ff */
/*0a80*/ IMAD R21, R2, 0x4, R19 ; /* 0x0000000402157824 */
/* 0x000fe200078e0213 */
/*0a90*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc80007ffe0ff */
/*0aa0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0ab0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ LEA R7, R2.reuse, R7, 0x2 ; /* 0x0000000702077211 */
/* 0x040fe200078e10ff */
/*0ad0*/ STS [R29], R14 ; /* 0x0000000e1d007388 */
/* 0x0041e80000000800 */
/*0ae0*/ STS [R5], R16 ; /* 0x0000001005007388 */
/* 0x0083e80000000800 */
/*0af0*/ STS [R19], R12 ; /* 0x0000000c13007388 */
/* 0x0103e80000000800 */
/*0b00*/ STS [R21], R10 ; /* 0x0000000a15007388 */
/* 0x0203e20000000800 */
/*0b10*/ IMAD R29, R2, 0x4, R21 ; /* 0x00000004021d7824 */
/* 0x001fe200078e0215 */
/*0b20*/ @P0 BRA 0x9d0 ; /* 0xfffffea000000947 */
/* 0x002fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc00 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD R5, R8, c[0x0][0x0], R3 ; /* 0x0000000008057a24 */
/* 0x000fca00078e0203 */
/*0b60*/ SHF.L.U32 R7, R5, 0x2, RZ ; /* 0x0000000205077819 */
/* 0x000fe400000006ff */
/*0b70*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0b80*/ IMAD.WIDE R8, R5, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x000fcc00078e0208 */
/*0b90*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0bb0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0bd0*/ STS [R7], R8 ; /* 0x0000000807007388 */
/* 0x0041e40000000800 */
/*0be0*/ LEA R7, R2, R7, 0x2 ; /* 0x0000000702077211 */
/* 0x001fd400078e10ff */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c10*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0c20*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0c30*/ @!P0 BRA 0xf90 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x002fe20000000f00 */
/*0c50*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fc600000001ff */
/*0c60*/ IADD3 R5, R13.reuse, -0x1, RZ ; /* 0xffffffff0d057810 */
/* 0x040fe40007ffe0ff */
/*0c70*/ LOP3.LUT R2, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d027812 */
/* 0x000fe400078ec0ff */
/*0c80*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0c90*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0ca0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f25270 */
/*0cb0*/ @!P0 BRA 0xec0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ IADD3 R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a10 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ IMAD R12, R13.reuse, 0x3, R4 ; /* 0x000000030d0c7824 */
/* 0x040fe200078e0204 */
/*0ce0*/ LEA R16, R13, R4.reuse, 0x1 ; /* 0x000000040d107211 */
/* 0x080fe200078e08ff */
/*0cf0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0d00*/ IADD3 R20, R2, -c[0x0][0x178], RZ ; /* 0x80005e0002147a10 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fe200078e0203 */
/*0d20*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0d30*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0d40*/ MOV R18, R4 ; /* 0x0000000400127202 */
/* 0x000fe40000000f00 */
/*0d50*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0d60*/ LDS.128 R8, [UR4] ; /* 0x00000004ff087984 */
/* 0x000e260008000c00 */
/*0d70*/ IMAD.WIDE.U32 R24, R18, R15, c[0x0][0x160] ; /* 0x0000580012187625 */
/* 0x000fc800078e000f */
/*0d80*/ IMAD.WIDE.U32 R22, R0, R15.reuse, c[0x0][0x160] ; /* 0x0000580000167625 */
/* 0x080fe400078e000f */
/*0d90*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000e24000c1e1900 */
/*0da0*/ IMAD.WIDE.U32 R6, R16, R15.reuse, c[0x0][0x160] ; /* 0x0000580010067625 */
/* 0x080fe400078e000f */
/*0db0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ea4000c1e1900 */
/*0dc0*/ IMAD.WIDE.U32 R14, R12, R15, c[0x0][0x160] ; /* 0x000058000c0e7625 */
/* 0x000fe400078e000f */
/*0dd0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee8000c1e1900 */
/*0de0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f22000c1e1900 */
/*0df0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007ffe0ff */
/*0e00*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0e10*/ LEA R0, R13.reuse, R0, 0x2 ; /* 0x000000000d007211 */
/* 0x040fe200078e10ff */
/*0e20*/ IMAD R16, R13, 0x4, R16 ; /* 0x000000040d107824 */
/* 0x000fe200078e0210 */
/*0e30*/ IADD3 R3, R20, R17, RZ ; /* 0x0000001114037210 */
/* 0x000fc40007ffe0ff */
/*0e40*/ LEA R18, R13, R18, 0x2 ; /* 0x000000120d127211 */
/* 0x000fe400078e10ff */
/*0e50*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0e60*/ LEA R12, R13, R12, 0x2 ; /* 0x0000000c0d0c7211 */
/* 0x000fe200078e10ff */
/*0e70*/ FFMA R8, R8, R24, R5 ; /* 0x0000001808087223 */
/* 0x001fc80000000005 */
/*0e80*/ FFMA R9, R22, R9, R8 ; /* 0x0000000916097223 */
/* 0x004fc80000000008 */
/*0e90*/ FFMA R10, R6, R10, R9 ; /* 0x0000000a060a7223 */
/* 0x008fc80000000009 */
/*0ea0*/ FFMA R5, R14, R11, R10 ; /* 0x0000000b0e057223 */
/* 0x010fe2000000000a */
/*0eb0*/ @P0 BRA 0xd50 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0ec0*/ @!P1 BRA 0xf90 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0ed0*/ IMAD.SHL.U32 R0, R17.reuse, 0x4, RZ ; /* 0x0000000411007824 */
/* 0x040fe400078e00ff */
/*0ee0*/ IMAD R17, R17, c[0x0][0x178], R4 ; /* 0x00005e0011117a24 */
/* 0x000fe400078e0204 */
/*0ef0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0f00*/ LDS R8, [R0] ; /* 0x0000000000087984 */
/* 0x0000680000000800 */
/*0f10*/ IMAD.WIDE.U32 R6, R17, R6, c[0x0][0x160] ; /* 0x0000580011067625 */
/* 0x000fcc00078e0006 */
/*0f20*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000e62000c1e1900 */
/*0f30*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0f40*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe40007ffe0ff */
/*0f50*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0f60*/ IADD3 R17, R17, c[0x0][0x178], RZ ; /* 0x00005e0011117a10 */
/* 0x000fe20007ffe0ff */
/*0f70*/ FFMA R5, R8, R6, R5 ; /* 0x0000000608057223 */
/* 0x002fd40000000005 */
/*0f80*/ @P0 BRA 0xef0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0f90*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0fa0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0207 */
/*0fb0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0fc0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x180] ; /* 0x0000600004067625 */
/* 0x000fc800078e0207 */
/*0fd0*/ FADD R5, R2, R5 ; /* 0x0000000502057221 */
/* 0x004fca0000000000 */
/*0fe0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101906 */
/*0ff0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6jacobiPfS_S_jS_
.globl _Z6jacobiPfS_S_jS_
.p2align 8
.type _Z6jacobiPfS_S_jS_,@function
_Z6jacobiPfS_S_jS_:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_gt_u32 s2, 0x400
s_cbranch_scc1 .LBB0_3
v_cvt_f32_u32_e32 v1, s2
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x44800000, v2
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v3, -v2, v1, 0x44800000
v_cvt_u32_f32_e32 v2, v2
v_cmp_ge_f32_e64 s6, |v3|, |v1|
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s7, v2
s_cmp_lg_u32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s4, s4, v3
v_add_co_ci_u32_e64 v2, null, s5, 0, s4
s_addc_u32 s5, s7, 0
s_lshl_b32 s4, s2, 2
s_and_b32 s5, s5, 0xffff
s_mov_b32 s6, s3
.LBB0_2:
global_load_b32 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s5
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
v_add_nc_u32_e32 v3, s4, v3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b32 s4, s[0:1], 0x18
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_mov_b32 s6, s4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_add_i32 s6, s6, -1
v_add_nc_u32_e32 v2, s4, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v5, s5
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s6, 0
ds_load_b32 v5, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, v4, v5
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v0, v3
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6jacobiPfS_S_jS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6jacobiPfS_S_jS_, .Lfunc_end0-_Z6jacobiPfS_S_jS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6jacobiPfS_S_jS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6jacobiPfS_S_jS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0d47_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2441:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2441:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "getMatrix doesn't get matrix\n"
.text
.globl _Z9getMatrixPfj
.type _Z9getMatrixPfj, @function
_Z9getMatrixPfj:
.LFB2431:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
testq %rdi, %rdi
je .L4
movq %rdi, %r13
movl %esi, %r12d
movl $0, %r14d
testl %esi, %esi
je .L3
.L5:
movl %r14d, %ebp
movl $0, %ebx
.L7:
call rand@PLT
movl %eax, %edx
movl %ebp, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movl %ebx, %eax
addl $1, %ebx
addl %r12d, %ebp
cmpl %ebx, %r12d
jne .L7
leal 1(%r14), %edx
cmpl %eax, %r14d
je .L8
movl %edx, %r14d
jmp .L5
.L4:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
leal 2(%rax), %edi
movl $0, %ecx
movl $0, %edx
movss .LC4(%rip), %xmm1
.L9:
movl %ecx, %esi
leaq 0(%r13,%rsi,4), %rsi
movaps %xmm1, %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rsi)
movl %edx, %esi
addl $1, %edx
addl %edi, %ecx
cmpl %esi, %eax
jne .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2431:
.size _Z9getMatrixPfj, .-_Z9getMatrixPfj
.globl _Z5get_fPfj
.type _Z5get_fPfj, @function
_Z5get_fPfj:
.LFB2432:
.cfi_startproc
endbr64
testl %esi, %esi
je .L20
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,4), %rbp
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2432:
.size _Z5get_fPfj, .-_Z5get_fPfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "computeBMatrix doesn't get matrix\n"
.section .rodata.str1.1
.LC8:
.string "error on allocate memory\n"
.text
.globl _Z14computeBMatrixPfj
.type _Z14computeBMatrixPfj, @function
_Z14computeBMatrixPfj:
.LFB2433:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testq %rdi, %rdi
je .L40
movq %rdi, %rbx
movl %esi, %ebp
movl %esi, %r12d
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %rdi
testq %rax, %rax
je .L25
testl %ebp, %ebp
je .L27
leal 1(%rbp), %esi
leaq (%rax,%r12,4), %r8
movl $0, %edx
movss .LC5(%rip), %xmm1
.L28:
movl %edx, %ecx
movaps %xmm1, %xmm0
divss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%rax)
addl %esi, %edx
addq $4, %rax
cmpq %r8, %rax
jne .L28
movl $0, %esi
.L29:
movl %esi, %edx
movq %rdi, %rax
.L30:
movl %edx, %ecx
leaq (%rbx,%rcx,4), %rcx
movss (%rcx), %xmm0
mulss (%rax), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addl %ebp, %edx
cmpq %r8, %rax
jne .L30
leal 1(%rsi), %r9d
cmpl %r9d, %ebp
je .L34
movl %r9d, %esi
jmp .L29
.L40:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %edx, %ecx
leaq (%rbx,%rcx,4), %rcx
subss (%rcx), %xmm0
movss %xmm0, (%rcx)
leal 1(%rax), %ecx
addl %r9d, %edx
cmpl %eax, %esi
je .L41
movl %ecx, %eax
.L33:
movaps %xmm1, %xmm0
cmpl %eax, %r8d
jne .L32
movaps %xmm2, %xmm0
jmp .L32
.L41:
leal 1(%r8), %eax
cmpl %r8d, %esi
je .L27
movl %eax, %r8d
.L31:
movl %r8d, %edx
movl %r10d, %eax
jmp .L33
.L34:
movl $0, %r8d
movl $0, %r10d
pxor %xmm1, %xmm1
movss .LC5(%rip), %xmm2
jmp .L31
.L27:
call free@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2433:
.size _Z14computeBMatrixPfj, .-_Z14computeBMatrixPfj
.section .rodata.str1.8
.align 8
.LC9:
.string "compute_g get invalud arguments\n"
.text
.globl _Z9compute_gPfS_j
.type _Z9compute_gPfS_j, @function
_Z9compute_gPfS_j:
.LFB2434:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L43
testq %rsi, %rsi
je .L43
testl %edx, %edx
je .L50
leal 1(%rdx), %r8d
movq %rsi, %rax
movl %edx, %edx
leaq (%rsi,%rdx,4), %rsi
movl $0, %edx
movss .LC5(%rip), %xmm1
.L46:
movl %edx, %ecx
movaps %xmm1, %xmm0
divss (%rdi,%rcx,4), %xmm0
mulss (%rax), %xmm0
movss %xmm0, (%rax)
addl %r8d, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L46
ret
.L50:
ret
.L43:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2434:
.size _Z9compute_gPfS_j, .-_Z9compute_gPfS_j
.section .rodata.str1.8
.align 8
.LC10:
.string "precision get invalid parametr\n"
.text
.globl _Z9precisionPfS_S_j
.type _Z9precisionPfS_S_j, @function
_Z9precisionPfS_S_j:
.LFB2435:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %r11
testq %rsi, %rsi
sete %al
testq %rdx, %rdx
sete %dl
orb %dl, %al
jne .L52
movl %ecx, %r10d
testq %rdi, %rdi
je .L52
testl %ecx, %ecx
je .L58
movq %rsi, %r8
movl %ecx, %eax
leaq (%rsi,%rax,4), %rbx
movl %ecx, %esi
movl $0, %r9d
pxor %xmm2, %xmm2
movss .LC11(%rip), %xmm3
.L54:
movq %r11, %rdx
movl %r9d, %eax
pxor %xmm1, %xmm1
.L55:
movl %eax, %ecx
movss (%rdi,%rcx,4), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addl $1, %eax
addq $4, %rdx
cmpl %esi, %eax
jne .L55
movss (%r8), %xmm0
subss %xmm1, %xmm0
andps %xmm3, %xmm0
maxss %xmm2, %xmm0
movaps %xmm0, %xmm2
addq $4, %r8
addl %r10d, %r9d
addl %r10d, %esi
cmpq %rbx, %r8
jne .L54
.L51:
movaps %xmm2, %xmm0
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
pxor %xmm2, %xmm2
jmp .L51
.cfi_endproc
.LFE2435:
.size _Z9precisionPfS_S_j, .-_Z9precisionPfS_S_j
.globl _Z9transposePfj
.type _Z9transposePfj, @function
_Z9transposePfj:
.LFB2436:
.cfi_startproc
endbr64
testl %esi, %esi
je .L70
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leal 1(%rsi), %ebx
movl $0, %r9d
movl $0, %r10d
movl $0, %r11d
jmp .L64
.L67:
movl %r11d, %eax
movl %r10d, %edx
.L65:
movl %edx, %ecx
leaq (%rdi,%rcx,4), %r8
movss (%r8), %xmm0
movl %eax, %ecx
leaq (%rdi,%rcx,4), %rcx
movss (%rcx), %xmm1
movss %xmm1, (%r8)
movss %xmm0, (%rcx)
addl %esi, %edx
addl $1, %eax
cmpl %r9d, %eax
jne .L65
.L64:
addl $1, %r10d
addl %esi, %r11d
addl %ebx, %r9d
cmpl %r10d, %esi
je .L62
testl %r10d, %r10d
jne .L67
jmp .L64
.L62:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore 3
ret
.cfi_endproc
.LFE2436:
.size _Z9transposePfj, .-_Z9transposePfj
.section .rodata.str1.1
.LC12:
.string "Cuda Error : %s\n"
.text
.globl _Z17checkGPUOperationv
.type _Z17checkGPUOperationv, @function
_Z17checkGPUOperationv:
.LFB2437:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L76
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2437:
.size _Z17checkGPUOperationv, .-_Z17checkGPUOperationv
.globl _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
.type _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_, @function
_Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_:
.LFB2463:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6jacobiPfS_S_jS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2463:
.size _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_, .-_Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
.globl _Z6jacobiPfS_S_jS_
.type _Z6jacobiPfS_S_jS_, @function
_Z6jacobiPfS_S_jS_:
.LFB2464:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2464:
.size _Z6jacobiPfS_S_jS_, .-_Z6jacobiPfS_S_jS_
.section .rodata.str1.1
.LC13:
.string "precision : %f \n"
.LC15:
.string "success\n"
.text
.globl main
.type main, @function
main:
.LFB2438:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $4, %esi
movl $1024, %edi
call calloc@PLT
testq %r13, %r13
je .L86
movq %rax, %rbp
testq %r15, %r15
je .L86
testq %r12, %r12
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L86
testq %rbp, %rbp
je .L86
movl $1024, %esi
movq %r13, %rdi
call _Z9getMatrixPfj
movl $1024, %esi
movq %r12, %rdi
call _Z5get_fPfj
movl $4194304, %edx
movq %r13, %rsi
movq %r15, %rdi
call memcpy@PLT
movl $512, %ecx
movq 8(%rsp), %rdi
movq %r12, %rsi
rep movsq
movl $1024, %edx
movq 8(%rsp), %rbx
movq %rbx, %rsi
movq %r13, %rdi
call _Z9compute_gPfS_j
movl $1024, %esi
movq %r15, %rdi
call _Z14computeBMatrixPfj
movl $1024, %esi
movq %r15, %rdi
call _Z9transposePfj
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $3, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq .LC13(%rip), %r14
jmp .L94
.L86:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L85
.L90:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L100
.L91:
movq 40(%rsp), %rax
movq 32(%rsp), %rdx
movq %rdx, 40(%rsp)
movq %rax, 32(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L90
movq 40(%rsp), %r8
movl $1024, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z6jacobiPfS_S_jS_PfS_S_jS_
jmp .L90
.L100:
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z17checkGPUOperationv
movl $1024, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z9precisionPfS_S_j
movss %xmm0, (%rsp)
cvtss2sd %xmm0, %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%rsp), %xmm1
comiss .LC14(%rip), %xmm1
jbe .L92
movss 4(%rsp), %xmm2
comiss %xmm1, %xmm2
jbe .L92
movss (%rsp), %xmm3
movss %xmm3, 4(%rsp)
.L94:
movl $512, %ebx
jmp .L91
.L92:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L85:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L101
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2438:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6jacobiPfS_S_jS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2466:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6jacobiPfS_S_jS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2466:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC2:
.long 1056964608
.align 4
.LC3:
.long 1092616192
.align 4
.LC4:
.long 1148846080
.align 4
.LC5:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC14:
.long 869711765
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "jacobi.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9getMatrixPfj
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0xbf000000 # float -0.5
.LCPI0_2:
.long 0x41200000 # float 10
.LCPI0_3:
.long 0x447a0000 # float 1000
.text
.globl _Z9getMatrixPfj
.p2align 4, 0x90
.type _Z9getMatrixPfj,@function
_Z9getMatrixPfj: # @_Z9getMatrixPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testq %rdi, %rdi
je .LBB0_9
# %bb.1: # %.preheader22
movl %esi, %ebx
testl %esi, %esi
je .LBB0_8
# %bb.2: # %.preheader21.preheader
movq %rdi, %r14
movl %ebx, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_3: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %r15, %r12
movl %ebp, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movl %r13d, %eax
movss %xmm0, (%r14,%rax,4)
addl %ebx, %r13d
decq %r12
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
incl %ebp
cmpl %ebx, %ebp
jne .LBB0_3
# %bb.6: # %.lr.ph
incl %ebx
xorl %eax, %eax
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%r14,%rcx,4)
addl %ebx, %eax
decq %r15
jne .LBB0_7
.LBB0_8: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $29, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z9getMatrixPfj, .Lfunc_end0-_Z9getMatrixPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z5get_fPfj
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0xbf000000 # float -0.5
.LCPI1_2:
.long 0x41200000 # float 10
.text
.globl _Z5get_fPfj
.p2align 4, 0x90
.type _Z5get_fPfj,@function
_Z5get_fPfj: # @_Z5get_fPfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z5get_fPfj, .Lfunc_end1-_Z5get_fPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14computeBMatrixPfj
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl _Z14computeBMatrixPfj
.p2align 4, 0x90
.type _Z14computeBMatrixPfj,@function
_Z14computeBMatrixPfj: # @_Z14computeBMatrixPfj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testq %rdi, %rdi
je .LBB2_1
# %bb.3:
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
movl $4, %esi
movq %r15, %rdi
callq calloc
testq %rax, %rax
je .LBB2_18
# %bb.4: # %.preheader55
testl %ebx, %ebx
je .LBB2_17
# %bb.5: # %.lr.ph
leal 1(%rbx), %ecx
xorl %edx, %edx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl %edx, %edi
movaps %xmm0, %xmm1
divss (%r14,%rdi,4), %xmm1
movss %xmm1, (%rax,%rsi,4)
incq %rsi
addl %ecx, %edx
cmpq %rsi, %r15
jne .LBB2_6
# %bb.7: # %.preheader53.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_8: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movl %ecx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, %edi
mulss (%r14,%rdi,4), %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %rsi
addl %ebx, %edx
cmpq %rsi, %r15
jne .LBB2_9
# %bb.10: # in Loop: Header=BB2_8 Depth=1
incl %ecx
cmpl %r15d, %ecx
jne .LBB2_8
# %bb.11: # %.preheader.preheader
xorl %ecx, %ecx
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_12 Depth=1
incq %rcx
cmpq %r15, %rcx
je .LBB2_17
.LBB2_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
movl %ecx, %edx
xorl %esi, %esi
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=2
movl %edx, %edi
subss (%r14,%rdi,4), %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %rsi
addl %ebx, %edx
cmpq %rsi, %r15
je .LBB2_16
.LBB2_13: # Parent Loop BB2_12 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm1
cmpq %rsi, %rcx
je .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=2
xorps %xmm1, %xmm1
jmp .LBB2_15
.LBB2_17: # %._crit_edge
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $34, %esi
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
.LBB2_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14computeBMatrixPfj, .Lfunc_end2-_Z14computeBMatrixPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9compute_gPfS_j
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl _Z9compute_gPfS_j
.p2align 4, 0x90
.type _Z9compute_gPfS_j,@function
_Z9compute_gPfS_j: # @_Z9compute_gPfS_j
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB3_6
# %bb.1:
testq %rsi, %rsi
je .LBB3_6
# %bb.2: # %.preheader
testl %edx, %edx
je .LBB3_5
# %bb.3: # %.lr.ph
movl %edx, %eax
incl %edx
xorl %ecx, %ecx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movl %ecx, %r9d
movaps %xmm0, %xmm1
divss (%rdi,%r9,4), %xmm1
mulss (%rsi,%r8,4), %xmm1
movss %xmm1, (%rsi,%r8,4)
incq %r8
addl %edx, %ecx
cmpq %r8, %rax
jne .LBB3_4
.LBB3_5: # %._crit_edge
retq
.LBB3_6:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $32, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z9compute_gPfS_j, .Lfunc_end3-_Z9compute_gPfS_j
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z9precisionPfS_S_j
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z9precisionPfS_S_j
.p2align 4, 0x90
.type _Z9precisionPfS_S_j,@function
_Z9precisionPfS_S_j: # @_Z9precisionPfS_S_j
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB4_5
# %bb.1:
testq %rsi, %rsi
je .LBB4_5
# %bb.2:
testq %rdx, %rdx
je .LBB4_5
# %bb.3: # %.preheader33
testl %ecx, %ecx
je .LBB4_4
# %bb.6: # %.preheader.preheader
movl %ecx, %eax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
xorl %r9d, %r9d
xorps %xmm3, %xmm3
.p2align 4, 0x90
.LBB4_8: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%r9), %r10d
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%r9,4), %xmm0
addss %xmm0, %xmm3
incq %r9
cmpq %r9, %rax
jne .LBB4_8
# %bb.9: # in Loop: Header=BB4_7 Depth=1
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss %xmm3, %xmm0
andps %xmm1, %xmm0
maxss %xmm2, %xmm0
incq %r8
addq %rax, %rcx
movaps %xmm0, %xmm2
cmpq %rax, %r8
jne .LBB4_7
# %bb.10: # %._crit_edge
retq
.LBB4_4:
xorps %xmm0, %xmm0
retq
.LBB4_5:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $31, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end4:
.size _Z9precisionPfS_S_j, .Lfunc_end4-_Z9precisionPfS_S_j
.cfi_endproc
# -- End function
.globl _Z21__device_stub__jacobiPfS_S_jS_ # -- Begin function _Z21__device_stub__jacobiPfS_S_jS_
.p2align 4, 0x90
.type _Z21__device_stub__jacobiPfS_S_jS_,@function
_Z21__device_stub__jacobiPfS_S_jS_: # @_Z21__device_stub__jacobiPfS_S_jS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6jacobiPfS_S_jS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end5:
.size _Z21__device_stub__jacobiPfS_S_jS_, .Lfunc_end5-_Z21__device_stub__jacobiPfS_S_jS_
.cfi_endproc
# -- End function
.globl _Z9transposePfj # -- Begin function _Z9transposePfj
.p2align 4, 0x90
.type _Z9transposePfj,@function
_Z9transposePfj: # @_Z9transposePfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB6_6
# %bb.1: # %.preheader.preheader
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %rdx
addq %rax, %rcx
cmpq %rax, %rdx
je .LBB6_6
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testq %rdx, %rdx
je .LBB6_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
movl %edx, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, %r10d
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rcx,%r9), %r11d
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rdi,%r10,4)
movss %xmm0, (%rdi,%r11,4)
incq %r9
addl %esi, %r8d
cmpq %r9, %rdx
jne .LBB6_4
jmp .LBB6_5
.LBB6_6: # %._crit_edge26
retq
.Lfunc_end6:
.size _Z9transposePfj, .Lfunc_end6-_Z9transposePfj
.cfi_endproc
# -- End function
.globl _Z17checkGPUOperationv # -- Begin function _Z17checkGPUOperationv
.p2align 4, 0x90
.type _Z17checkGPUOperationv,@function
_Z17checkGPUOperationv: # @_Z17checkGPUOperationv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipGetLastError
testl %eax, %eax
jne .LBB7_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB7_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z17checkGPUOperationv, .Lfunc_end7-_Z17checkGPUOperationv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI8_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI8_1:
.long 0xbf000000 # float -0.5
.LCPI8_2:
.long 0x41200000 # float 10
.LCPI8_3:
.long 0x447a0000 # float 1000
.LCPI8_4:
.long 0x3f800000 # float 1
.LCPI8_6:
.long 0x33d6bf95 # float 1.00000001E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI8_5:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
movl $4, %esi
callq calloc
testq %rbp, %rbp
je .LBB8_41
# %bb.1:
testq %rbx, %rbx
je .LBB8_41
# %bb.2:
testq %r15, %r15
je .LBB8_41
# %bb.3:
testq %r14, %r14
je .LBB8_41
# %bb.4:
movq %rax, %r13
testq %rax, %rax
je .LBB8_41
# %bb.5: # %.preheader21.i.preheader
movq %r14, 56(%rsp) # 8-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq %rbp, %r14
.p2align 4, 0x90
.LBB8_6: # %.preheader21.i
# =>This Loop Header: Depth=1
# Child Loop BB8_7 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_7: # Parent Loop BB8_6 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI8_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
movss .LCPI8_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r12)
addq $4096, %r12 # imm = 0x1000
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB8_7
# %bb.8: # in Loop: Header=BB8_6 Depth=1
incl %ebx
addq $4, %r14
cmpl $1024, %ebx # imm = 0x400
jne .LBB8_6
# %bb.9: # %.preheader.i.preheader
xorl %eax, %eax
movss .LCPI8_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB8_10: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movss (%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rbp,%rax)
addq $4100, %rax # imm = 0x1004
cmpq $4198400, %rax # imm = 0x401000
jne .LBB8_10
# %bb.11: # %.lr.ph.i.preheader
xorl %ebx, %ebx
movq 64(%rsp), %r14 # 8-byte Reload
movq 56(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB8_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI8_0(%rip), %xmm0
addss .LCPI8_1(%rip), %xmm0
mulss .LCPI8_2(%rip), %xmm0
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB8_12
# %bb.13: # %_Z5get_fPfj.exit
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movq %rbp, %rsi
callq memcpy@PLT
movl $4096, %edx # imm = 0x1000
movq %r12, %rdi
movq %r15, %rsi
callq memcpy@PLT
xorl %eax, %eax
movss .LCPI8_4(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbp, %rcx
.p2align 4, 0x90
.LBB8_14: # =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm1
divss (%rcx), %xmm1
mulss (%r12,%rax,4), %xmm1
movss %xmm1, (%r12,%rax,4)
incq %rax
addq $4100, %rcx # imm = 0x1004
cmpq $1024, %rax # imm = 0x400
jne .LBB8_14
# %bb.15: # %_Z9compute_gPfS_j.exit
movq %r14, %rdi
movl $1024, %esi # imm = 0x400
callq _Z14computeBMatrixPfj
xorl %eax, %eax
movq %r14, %rcx
movq %r14, %rdx
jmp .LBB8_16
.p2align 4, 0x90
.LBB8_19: # %._crit_edge.i
# in Loop: Header=BB8_16 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4, %rcx
cmpq $1024, %rax # imm = 0x400
je .LBB8_20
.LBB8_16: # %.preheader.i89
# =>This Loop Header: Depth=1
# Child Loop BB8_18 Depth 2
testq %rax, %rax
je .LBB8_19
# %bb.17: # %.lr.ph.i91
# in Loop: Header=BB8_16 Depth=1
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_18: # Parent Loop BB8_16 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rdx,%rdi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rsi)
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq %rdi, %rax
jne .LBB8_18
jmp .LBB8_19
.LBB8_20: # %_Z9transposePfj.exit
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.21: # %_Z17checkGPUOperationv.exit
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.22: # %_Z17checkGPUOperationv.exit98
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.23: # %_Z17checkGPUOperationv.exit100
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.24: # %_Z17checkGPUOperationv.exit102
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.25: # %_Z17checkGPUOperationv.exit104
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $3, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.26: # %_Z17checkGPUOperationv.exit106
movq %rbp, 72(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.27: # %_Z17checkGPUOperationv.exit108
movabsq $4294967300, %rbp # imm = 0x100000004
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
leaq 252(%rbp), %r14
leaq 160(%rsp), %r12
.p2align 4, 0x90
.LBB8_28: # =>This Loop Header: Depth=1
# Child Loop BB8_29 Depth 2
# Child Loop BB8_34 Depth 2
# Child Loop BB8_35 Depth 3
movl $512, %ebx # imm = 0x200
jmp .LBB8_29
.p2align 4, 0x90
.LBB8_31: # in Loop: Header=BB8_29 Depth=2
callq hipDeviceSynchronize
decl %ebx
je .LBB8_32
.LBB8_29: # Parent Loop BB8_28 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_31
# %bb.30: # in Loop: Header=BB8_29 Depth=2
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $1024, 52(%rsp) # imm = 0x400
movq %rsi, 128(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z6jacobiPfS_S_jS_, %edi
movq %r12, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB8_31
.p2align 4, 0x90
.LBB8_32: # in Loop: Header=BB8_28 Depth=1
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB8_42
# %bb.33: # %.preheader.i112.preheader
# in Loop: Header=BB8_28 Depth=1
xorps %xmm0, %xmm0
movq 72(%rsp), %rax # 8-byte Reload
xorl %ecx, %ecx
movaps .LCPI8_5(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB8_34: # %.preheader.i112
# Parent Loop BB8_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_35 Depth 3
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB8_35: # Parent Loop BB8_28 Depth=1
# Parent Loop BB8_34 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss (%r13,%rdx,4), %xmm2
addss %xmm2, %xmm1
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB8_35
# %bb.36: # in Loop: Header=BB8_34 Depth=2
movss (%r15,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
andps %xmm3, %xmm2
maxss %xmm0, %xmm2
incq %rcx
addq $4096, %rax # imm = 0x1000
movaps %xmm2, %xmm0
cmpq $1024, %rcx # imm = 0x400
jne .LBB8_34
# %bb.37: # %_Z9precisionPfS_S_j.exit
# in Loop: Header=BB8_28 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl $.L.str.6, %edi
movb $1, %al
movaps %xmm2, 208(%rsp) # 16-byte Spill
callq printf
movaps 208(%rsp), %xmm1 # 16-byte Reload
ucomiss .LCPI8_6(%rip), %xmm1
jbe .LBB8_39
# %bb.38: # %_Z9precisionPfS_S_j.exit
# in Loop: Header=BB8_28 Depth=1
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss %xmm1, 28(%rsp) # 4-byte Spill
ja .LBB8_28
.LBB8_39:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB8_40:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_41:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %eax
jmp .LBB8_40
.LBB8_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6jacobiPfS_S_jS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "getMatrix doesn't get matrix\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "computeBMatrix doesn't get matrix\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error on allocate memory\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "compute_g get invalud arguments\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "precision get invalid parametr\n"
.size .L.str.4, 32
.type _Z6jacobiPfS_S_jS_,@object # @_Z6jacobiPfS_S_jS_
.section .rodata,"a",@progbits
.globl _Z6jacobiPfS_S_jS_
.p2align 3, 0x0
_Z6jacobiPfS_S_jS_:
.quad _Z21__device_stub__jacobiPfS_S_jS_
.size _Z6jacobiPfS_S_jS_, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Cuda Error : %s\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "precision : %f \n"
.size .L.str.6, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6jacobiPfS_S_jS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "success"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__jacobiPfS_S_jS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6jacobiPfS_S_jS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} | code for sm_80
Function : _Z14oddEvenEigSortPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fe20004000000 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc60000000f00 */
/*0070*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ LOP3.LUT R9, R4, 0xfffffffe, R3, 0xe2, !PT ; /* 0xfffffffe04097812 */
/* 0x000fc800078ee203 */
/*00a0*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R6, R9, R4, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fca00078e0204 */
/*00f0*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FSETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720b */
/* 0x004fda0003f04000 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0150*/ STG.E [R6.64+0x4], R8 ; /* 0x0000040806007986 */
/* 0x0001f0000c101904 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0180*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0190*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R2, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300027812 */
/* 0x000fd400078ec0ff */
/*01b0*/ @!P0 BRA 0xc20 ; /* 0x00000a6000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R7, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002077a10 */
/* 0x000fe40007ffe1ff */
/*01d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R9 ; /* 0x0000001fff067819 */
/* 0x000fe40000011409 */
/*01e0*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f04270 */
/*01f0*/ LEA R8, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a0009087a11 */
/* 0x000fc800078210ff */
/*0200*/ LEA.HI.X R9, R9, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b0009097a11 */
/* 0x000fe200008f1406 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0220*/ @!P0 BRA 0xaa0 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0250*/ @!P1 BRA 0x7b0 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x004ea8000c1e1900 */
/*0280*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*0290*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*02a0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*02b0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*02c0*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*02e0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*02f0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0300*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0087e8000c101904 */
/*0310*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000f28000c1e1900 */
/*0320*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0340*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0109e8000c101904 */
/*0350*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x020be8000c101904 */
/*0360*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ea8000c1e1900 */
/*0370*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002ee2000c1e1900 */
/*0380*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*0390*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101904 */
/*03a0*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0083e8000c101904 */
/*03b0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*03e0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0045e8000c101904 */
/*03f0*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0087e8000c101904 */
/*0400*/ LDG.E R27, [R10.64+0x4] ; /* 0x000004040a1b7981 */
/* 0x010f28000c1e1900 */
/*0410*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x020f62000c1e1900 */
/*0420*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0430*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0109e8000c101904 */
/*0440*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x020be8000c101904 */
/*0450*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x001ea8000c1e1900 */
/*0460*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x002ee2000c1e1900 */
/*0470*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0480*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0041e8000c101904 */
/*0490*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0083e8000c101904 */
/*04a0*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004040e177981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ee2000c1e1900 */
/*04c0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*04d0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0045e8000c101904 */
/*04e0*/ STG.E [R14.64+0x4], R21 ; /* 0x000004150e007986 */
/* 0x0087e8000c101904 */
/*04f0*/ LDG.E R27, [R8.64+0x4] ; /* 0x00000404081b7981 */
/* 0x010f28000c1e1900 */
/*0500*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x020f62000c1e1900 */
/*0510*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0520*/ STG.E [R8.64], R27 ; /* 0x0000001b08007986 */
/* 0x0109e8000c101904 */
/*0530*/ STG.E [R8.64+0x4], R25 ; /* 0x0000041908007986 */
/* 0x020be8000c101904 */
/*0540*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x001ea8000c1e1900 */
/*0550*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x002ee2000c1e1900 */
/*0560*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0570*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0041e8000c101904 */
/*0580*/ STG.E [R10.64+0x4], R17 ; /* 0x000004110a007986 */
/* 0x0083e8000c101904 */
/*0590*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05c0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0045e8000c101904 */
/*05d0*/ STG.E [R12.64+0x4], R21 ; /* 0x000004150c007986 */
/* 0x0087e8000c101904 */
/*05e0*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004040e1b7981 */
/* 0x010f28000c1e1900 */
/*05f0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x020f62000c1e1900 */
/*0600*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*0610*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0109e8000c101904 */
/*0620*/ STG.E [R14.64+0x4], R25 ; /* 0x000004190e007986 */
/* 0x020be8000c101904 */
/*0630*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x001ea8000c1e1900 */
/*0640*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x002ee2000c1e1900 */
/*0650*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0660*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0670*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0680*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*06b0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*06c0*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*06d0*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x010ee8000c1e1900 */
/*06e0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x020f22000c1e1900 */
/*06f0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0700*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0085e8000c101904 */
/*0710*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x0105e8000c101904 */
/*0720*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ee8000c1e1900 */
/*0730*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002f22000c1e1900 */
/*0740*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0760*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007ffe0ff */
/*0770*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*0780*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0085e8000c101904 */
/*0790*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0105f0000c101904 */
/*07a0*/ @P1 BRA 0x270 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*07b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*07c0*/ @!P1 BRA 0xa80 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x004ea8000c1e1900 */
/*07e0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0800*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0810*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0820*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*0840*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0850*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0860*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0087e8000c101904 */
/*0870*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f62000c1e1900 */
/*0890*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*08a0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0109e8000c101904 */
/*08b0*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x020be8000c101904 */
/*08c0*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ea8000c1e1900 */
/*08d0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002ee2000c1e1900 */
/*08e0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*08f0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101904 */
/*0900*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0083e8000c101904 */
/*0910*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*0930*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0940*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0045e8000c101904 */
/*0950*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0087e8000c101904 */
/*0960*/ LDG.E R27, [R10.64+0x4] ; /* 0x000004040a1b7981 */
/* 0x010f28000c1e1900 */
/*0970*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x020f62000c1e1900 */
/*0980*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0990*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0109e8000c101904 */
/*09a0*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x0209e8000c101904 */
/*09b0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x001f68000c1e1900 */
/*09c0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x002ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*09e0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0209e8000c101904 */
/*09f0*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0049e8000c101904 */
/*0a00*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004040e177981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x008ee2000c1e1900 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0a40*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0a60*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0049e8000c101904 */
/*0a70*/ STG.E [R14.64+0x4], R21 ; /* 0x000004150e007986 */
/* 0x0089e8000c101904 */
/*0a80*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc20 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x014ea8000c1e1900 */
/*0ab0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*0ac0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0ad0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0ae0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0af0*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*0b10*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0b20*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0b30*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*0b40*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000ee8000c1e1900 */
/*0b50*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f22000c1e1900 */
/*0b60*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b70*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0085e8000c101904 */
/*0b80*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x0105e8000c101904 */
/*0b90*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ee8000c1e1900 */
/*0ba0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002f22000c1e1900 */
/*0bb0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0bd0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0bf0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0085e8000c101904 */
/*0c00*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0105f0000c101904 */
/*0c10*/ @P0 BRA 0xaa0 ; /* 0xfffffe8000000947 */
/* 0x004fea000383ffff */
/*0c20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c30*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c40*/ IMAD R6, R6, c[0x0][0x170], R5 ; /* 0x00005c0006067a24 */
/* 0x000fca00078e0205 */
/*0c50*/ IADD3 R5, R3, R6, RZ ; /* 0x0000000603057210 */
/* 0x000fca0007ffe0ff */
/*0c60*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0c70*/ IADD3 R4, P0, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f1e0ff */
/*0c80*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fc600000e0605 */
/*0c90*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe20000000f00 */
/*0ca0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0005 */
/*0cb0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee8000c1e1900 */
/*0cc0*/ LDG.E R3, [R6.64+-0x4] ; /* 0xfffffc0406037981 */
/* 0x000f62000c1e1900 */
/*0cd0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc600078e0206 */
/*0cf0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0d00*/ STG.E [R6.64+-0x4], R9 ; /* 0xfffffc0906007986 */
/* 0x0081e8000c101904 */
/*0d10*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0201f0000c101904 */
/*0d20*/ @P0 BRA 0xc90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} | .file "tmpxft_001088c3_00000000-6_OddEvenSort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
.type _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii, @function
_Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14oddEvenEigSortPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii, .-_Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
.globl _Z14oddEvenEigSortPfS_ii
.type _Z14oddEvenEigSortPfS_ii, @function
_Z14oddEvenEigSortPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14oddEvenEigSortPfS_ii, .-_Z14oddEvenEigSortPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14oddEvenEigSortPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14oddEvenEigSortPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} | #include <hip/hip_runtime.h>
/* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14oddEvenEigSortPfS_ii
.globl _Z14oddEvenEigSortPfS_ii
.p2align 8
.type _Z14oddEvenEigSortPfS_ii,@function
_Z14oddEvenEigSortPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lg_u32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s3
s_add_i32 s3, s2, -1
v_lshl_or_b32 v0, v1, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v5, v3
s_cmp_lt_i32 s2, 1
global_store_b64 v[1:2], v[4:5], off
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, s2
.LBB0_4:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v3
global_store_b64 v[1:2], v[4:5], off
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14oddEvenEigSortPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14oddEvenEigSortPfS_ii, .Lfunc_end0-_Z14oddEvenEigSortPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14oddEvenEigSortPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14oddEvenEigSortPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Odd-even sort
* This will need to be called within a loop that runs from 0 to
* the ceiling of N/2 - 1, where N is the number of eigenvalues
* We assume a linear array of threads and it will be the caller's
* responsibility to ensure the thread indices are in bounds
* Note to self: There is a GPU Quicksort available, but I have to modify
* it to also move around eigenvectors... challenging, striving for accuracy
*/
__global__ void oddEvenEigSort( float *eigenvalues, float *eigenvectors, int N, int odd = 0 ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
elementNum *= 2;
if( odd ) {
elementNum++;
}
if( elementNum >= N - 1 ) {
return;
}
if( eigenvalues[elementNum] > eigenvalues[elementNum + 1] ) {
float tmp = eigenvalues[elementNum];
eigenvalues[elementNum] = eigenvalues[elementNum + 1];
eigenvalues[elementNum + 1] = tmp;
for( int i = 0; i < N; i++ ) {
tmp = eigenvectors[i * N + elementNum];
eigenvectors[i * N + elementNum] = eigenvectors[i * N + elementNum + 1];
eigenvectors[i * N + elementNum + 1] = tmp;
}
}
} | .text
.file "OddEvenSort_kernel.hip"
.globl _Z29__device_stub__oddEvenEigSortPfS_ii # -- Begin function _Z29__device_stub__oddEvenEigSortPfS_ii
.p2align 4, 0x90
.type _Z29__device_stub__oddEvenEigSortPfS_ii,@function
_Z29__device_stub__oddEvenEigSortPfS_ii: # @_Z29__device_stub__oddEvenEigSortPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14oddEvenEigSortPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__oddEvenEigSortPfS_ii, .Lfunc_end0-_Z29__device_stub__oddEvenEigSortPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14oddEvenEigSortPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14oddEvenEigSortPfS_ii,@object # @_Z14oddEvenEigSortPfS_ii
.section .rodata,"a",@progbits
.globl _Z14oddEvenEigSortPfS_ii
.p2align 3, 0x0
_Z14oddEvenEigSortPfS_ii:
.quad _Z29__device_stub__oddEvenEigSortPfS_ii
.size _Z14oddEvenEigSortPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14oddEvenEigSortPfS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__oddEvenEigSortPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14oddEvenEigSortPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14oddEvenEigSortPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fe20004000000 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc60000000f00 */
/*0070*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ LOP3.LUT R9, R4, 0xfffffffe, R3, 0xe2, !PT ; /* 0xfffffffe04097812 */
/* 0x000fc800078ee203 */
/*00a0*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R6, R9, R4, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fca00078e0204 */
/*00f0*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FSETP.GT.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720b */
/* 0x004fda0003f04000 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0150*/ STG.E [R6.64+0x4], R8 ; /* 0x0000040806007986 */
/* 0x0001f0000c101904 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0180*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0190*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R2, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300027812 */
/* 0x000fd400078ec0ff */
/*01b0*/ @!P0 BRA 0xc20 ; /* 0x00000a6000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R7, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002077a10 */
/* 0x000fe40007ffe1ff */
/*01d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R9 ; /* 0x0000001fff067819 */
/* 0x000fe40000011409 */
/*01e0*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f04270 */
/*01f0*/ LEA R8, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a0009087a11 */
/* 0x000fc800078210ff */
/*0200*/ LEA.HI.X R9, R9, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b0009097a11 */
/* 0x000fe200008f1406 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0220*/ @!P0 BRA 0xaa0 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0250*/ @!P1 BRA 0x7b0 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x004ea8000c1e1900 */
/*0280*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*0290*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*02a0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*02b0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*02c0*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*02e0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*02f0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0300*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0087e8000c101904 */
/*0310*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000f28000c1e1900 */
/*0320*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0340*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0109e8000c101904 */
/*0350*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x020be8000c101904 */
/*0360*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ea8000c1e1900 */
/*0370*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002ee2000c1e1900 */
/*0380*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*0390*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101904 */
/*03a0*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0083e8000c101904 */
/*03b0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*03e0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0045e8000c101904 */
/*03f0*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0087e8000c101904 */
/*0400*/ LDG.E R27, [R10.64+0x4] ; /* 0x000004040a1b7981 */
/* 0x010f28000c1e1900 */
/*0410*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x020f62000c1e1900 */
/*0420*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0430*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0109e8000c101904 */
/*0440*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x020be8000c101904 */
/*0450*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x001ea8000c1e1900 */
/*0460*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x002ee2000c1e1900 */
/*0470*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0480*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0041e8000c101904 */
/*0490*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0083e8000c101904 */
/*04a0*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004040e177981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ee2000c1e1900 */
/*04c0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*04d0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0045e8000c101904 */
/*04e0*/ STG.E [R14.64+0x4], R21 ; /* 0x000004150e007986 */
/* 0x0087e8000c101904 */
/*04f0*/ LDG.E R27, [R8.64+0x4] ; /* 0x00000404081b7981 */
/* 0x010f28000c1e1900 */
/*0500*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x020f62000c1e1900 */
/*0510*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0520*/ STG.E [R8.64], R27 ; /* 0x0000001b08007986 */
/* 0x0109e8000c101904 */
/*0530*/ STG.E [R8.64+0x4], R25 ; /* 0x0000041908007986 */
/* 0x020be8000c101904 */
/*0540*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x001ea8000c1e1900 */
/*0550*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x002ee2000c1e1900 */
/*0560*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0570*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0041e8000c101904 */
/*0580*/ STG.E [R10.64+0x4], R17 ; /* 0x000004110a007986 */
/* 0x0083e8000c101904 */
/*0590*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05c0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0045e8000c101904 */
/*05d0*/ STG.E [R12.64+0x4], R21 ; /* 0x000004150c007986 */
/* 0x0087e8000c101904 */
/*05e0*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004040e1b7981 */
/* 0x010f28000c1e1900 */
/*05f0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x020f62000c1e1900 */
/*0600*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*0610*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0109e8000c101904 */
/*0620*/ STG.E [R14.64+0x4], R25 ; /* 0x000004190e007986 */
/* 0x020be8000c101904 */
/*0630*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x001ea8000c1e1900 */
/*0640*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x002ee2000c1e1900 */
/*0650*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0660*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0670*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0680*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*06b0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*06c0*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*06d0*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x010ee8000c1e1900 */
/*06e0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x020f22000c1e1900 */
/*06f0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0700*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0085e8000c101904 */
/*0710*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x0105e8000c101904 */
/*0720*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ee8000c1e1900 */
/*0730*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002f22000c1e1900 */
/*0740*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0760*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007ffe0ff */
/*0770*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*0780*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0085e8000c101904 */
/*0790*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0105f0000c101904 */
/*07a0*/ @P1 BRA 0x270 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*07b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*07c0*/ @!P1 BRA 0xa80 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x004ea8000c1e1900 */
/*07e0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0800*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0810*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0820*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*0840*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0850*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0860*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0087e8000c101904 */
/*0870*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f62000c1e1900 */
/*0890*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*08a0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0109e8000c101904 */
/*08b0*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x020be8000c101904 */
/*08c0*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ea8000c1e1900 */
/*08d0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002ee2000c1e1900 */
/*08e0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc600078e020e */
/*08f0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101904 */
/*0900*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0083e8000c101904 */
/*0910*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*0930*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0940*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0045e8000c101904 */
/*0950*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0087e8000c101904 */
/*0960*/ LDG.E R27, [R10.64+0x4] ; /* 0x000004040a1b7981 */
/* 0x010f28000c1e1900 */
/*0970*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x020f62000c1e1900 */
/*0980*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0990*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0109e8000c101904 */
/*09a0*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x0209e8000c101904 */
/*09b0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x001f68000c1e1900 */
/*09c0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x002ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*09e0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0209e8000c101904 */
/*09f0*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0049e8000c101904 */
/*0a00*/ LDG.E R23, [R14.64+0x4] ; /* 0x000004040e177981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x008ee2000c1e1900 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0a40*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0a60*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0049e8000c101904 */
/*0a70*/ STG.E [R14.64+0x4], R21 ; /* 0x000004150e007986 */
/* 0x0089e8000c101904 */
/*0a80*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc20 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x014ea8000c1e1900 */
/*0ab0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*0ac0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0ad0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0041e8000c101904 */
/*0ae0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0083e8000c101904 */
/*0af0*/ LDG.E R23, [R10.64+0x4] ; /* 0x000004040a177981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ee2000c1e1900 */
/*0b10*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020a */
/*0b20*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0045e8000c101904 */
/*0b30*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*0b40*/ LDG.E R27, [R12.64+0x4] ; /* 0x000004040c1b7981 */
/* 0x000ee8000c1e1900 */
/*0b50*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f22000c1e1900 */
/*0b60*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b70*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0085e8000c101904 */
/*0b80*/ STG.E [R12.64+0x4], R25 ; /* 0x000004190c007986 */
/* 0x0105e8000c101904 */
/*0b90*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004040e137981 */
/* 0x001ee8000c1e1900 */
/*0ba0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x002f22000c1e1900 */
/*0bb0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fe200078e020e */
/*0bd0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0bf0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0085e8000c101904 */
/*0c00*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0105f0000c101904 */
/*0c10*/ @P0 BRA 0xaa0 ; /* 0xfffffe8000000947 */
/* 0x004fea000383ffff */
/*0c20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c30*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c40*/ IMAD R6, R6, c[0x0][0x170], R5 ; /* 0x00005c0006067a24 */
/* 0x000fca00078e0205 */
/*0c50*/ IADD3 R5, R3, R6, RZ ; /* 0x0000000603057210 */
/* 0x000fca0007ffe0ff */
/*0c60*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0c70*/ IADD3 R4, P0, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f1e0ff */
/*0c80*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fc600000e0605 */
/*0c90*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe20000000f00 */
/*0ca0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0005 */
/*0cb0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee8000c1e1900 */
/*0cc0*/ LDG.E R3, [R6.64+-0x4] ; /* 0xfffffc0406037981 */
/* 0x000f62000c1e1900 */
/*0cd0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc600078e0206 */
/*0cf0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0d00*/ STG.E [R6.64+-0x4], R9 ; /* 0xfffffc0906007986 */
/* 0x0081e8000c101904 */
/*0d10*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0201f0000c101904 */
/*0d20*/ @P0 BRA 0xc90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14oddEvenEigSortPfS_ii
.globl _Z14oddEvenEigSortPfS_ii
.p2align 8
.type _Z14oddEvenEigSortPfS_ii,@function
_Z14oddEvenEigSortPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lg_u32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s3
s_add_i32 s3, s2, -1
v_lshl_or_b32 v0, v1, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v5, v3
s_cmp_lt_i32 s2, 1
global_store_b64 v[1:2], v[4:5], off
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, s2
.LBB0_4:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v3
global_store_b64 v[1:2], v[4:5], off
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14oddEvenEigSortPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14oddEvenEigSortPfS_ii, .Lfunc_end0-_Z14oddEvenEigSortPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14oddEvenEigSortPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14oddEvenEigSortPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001088c3_00000000-6_OddEvenSort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
.type _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii, @function
_Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14oddEvenEigSortPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii, .-_Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
.globl _Z14oddEvenEigSortPfS_ii
.type _Z14oddEvenEigSortPfS_ii, @function
_Z14oddEvenEigSortPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14oddEvenEigSortPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14oddEvenEigSortPfS_ii, .-_Z14oddEvenEigSortPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14oddEvenEigSortPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14oddEvenEigSortPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "OddEvenSort_kernel.hip"
.globl _Z29__device_stub__oddEvenEigSortPfS_ii # -- Begin function _Z29__device_stub__oddEvenEigSortPfS_ii
.p2align 4, 0x90
.type _Z29__device_stub__oddEvenEigSortPfS_ii,@function
_Z29__device_stub__oddEvenEigSortPfS_ii: # @_Z29__device_stub__oddEvenEigSortPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14oddEvenEigSortPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__oddEvenEigSortPfS_ii, .Lfunc_end0-_Z29__device_stub__oddEvenEigSortPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14oddEvenEigSortPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14oddEvenEigSortPfS_ii,@object # @_Z14oddEvenEigSortPfS_ii
.section .rodata,"a",@progbits
.globl _Z14oddEvenEigSortPfS_ii
.p2align 3, 0x0
_Z14oddEvenEigSortPfS_ii:
.quad _Z29__device_stub__oddEvenEigSortPfS_ii
.size _Z14oddEvenEigSortPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14oddEvenEigSortPfS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__oddEvenEigSortPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14oddEvenEigSortPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits