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2 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8MyKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
IMAD R5, R0, R0, RZ ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelPii
.globl _Z8MyKernelPii
.p2align 8
.type _Z8MyKernelPii,@function
_Z8MyKernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelPii, .Lfunc_end0-_Z8MyKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 319 | 2,031 |
3 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00122270_00000000-6_occupancy.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Launched blocks of size %d with gridSize %d. Theoretical occupancy: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L11
.L4:
leal 1048575(%rbx), %eax
cltd
idivl %ebx
movl %eax, %ebp
call cudaDeviceSynchronize@PLT
leaq 40(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
leaq 44(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 44(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 356(%rsp), %ecx
movl %ebx, %eax
imull 40(%rsp), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 672(%rsp), %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq 28(%rsp), %rdi
movl 24(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 32(%rsp), %rdi
movl 24(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 36(%rsp), %rdi
movl 24(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 40(%rsp), %rdi
movl 24(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 48(%rsp), %rdi
leaq _Z8MyKernelPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L4
movl 28(%rsp), %eax
movl %eax, 12(%rsp)
movl 32(%rsp), %r15d
movl 72(%rsp), %r13d
movl 36(%rsp), %eax
cmpl %eax, %r13d
cmovg %eax, %r13d
leal -1(%r15,%r13), %eax
cltd
idivl %r15d
imull %r15d, %eax
movl %eax, %ebp
movl $0, %r14d
movl $0, %ebx
jmp .L5
.L6:
cmpl %r14d, 12(%rsp)
je .L4
subl %r15d, %ebp
.L5:
testl %ebp, %ebp
jle .L4
cmpl %ebp, %r13d
movl %ebp, %r12d
cmovle %r13d, %r12d
leaq 44(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %r12d, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L4
movl %r12d, %eax
imull 44(%rsp), %eax
cmpl %r14d, %eax
jle .L6
movl %eax, %r14d
movl %r12d, %ebx
jmp .L6
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z28__device_stub__Z8MyKernelPiiPii
.type _Z28__device_stub__Z8MyKernelPiiPii, @function
_Z28__device_stub__Z8MyKernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8MyKernelPiiPii, .-_Z28__device_stub__Z8MyKernelPiiPii
.globl _Z8MyKernelPii
.type _Z8MyKernelPii, @function
_Z8MyKernelPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8MyKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernelPii, .-_Z8MyKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8MyKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "occupancy.hip"
.globl _Z23__device_stub__MyKernelPii
.type _Z23__device_stub__MyKernelPii,@function
_Z23__device_stub__MyKernelPii:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8MyKernelPii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelPii, .Lfunc_end0-_Z23__device_stub__MyKernelPii
.cfi_endproc
.globl main
.type main,@function
main:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1496, %rsp
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
leaq 20(%rsp), %r14
movl $_Z8MyKernelPii, %edx
movq %r14, %rsi
xorl %ecx, %ecx
xorl %r8d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl (%r14), %ecx
leal 1048575(%rcx), %eax
cltd
idivl %ecx
movl %eax, %ebx
callq hipDeviceSynchronize
movl (%r14), %edx
leaq 12(%rsp), %r15
movl $_Z8MyKernelPii, %esi
movq %r15, %rdi
xorl %ecx, %ecx
callq hipOccupancyMaxActiveBlocksPerMultiprocessor
leaq 8(%rsp), %r12
movq %r12, %rdi
callq hipGetDevice
movl (%r12), %esi
leaq 24(%rsp), %r12
movq %r12, %rdi
callq hipGetDevicePropertiesR0600
movl (%r14), %esi
movl (%r15), %eax
imull %esi, %eax
movl 308(%r12), %edi
movl 624(%r12), %ecx
cltd
idivl %edi
cvtsi2ss %eax, %xmm0
movl %ecx, %eax
cltd
idivl %edi
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %edx
movb $1, %al
callq printf
xorl %eax, %eax
addq $1496, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_ctor,@function
__hip_module_ctor:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_dtor,@function
__hip_module_dtor:
.cfi_startproc
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
.type _Z8MyKernelPii,@object
.section .rodata,"a",@progbits
.globl _Z8MyKernelPii
.p2align 3, 0x0
_Z8MyKernelPii:
.quad _Z23__device_stub__MyKernelPii
.size _Z8MyKernelPii, 8
.type .L.str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Launched blocks of size %d with gridSize %d. Theoretical occupancy: %f\n"
.size .L.str, 72
.type .L__unnamed_1,@object
.L__unnamed_1:
.asciz "_Z8MyKernelPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230
.long 1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
``` | 3,445 | 2,582 |
4 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10matrix_addPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
S2R R2, SR_TID.Y ;
S2R R5, SR_CTAID.Y ;
IMAD R0, R3, c[0x0][0x0], R0 ;
IMAD R3, R5, c[0x0][0x4], R2 ;
LEA R0, R3, R0, 0x5 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x170] ;
FADD R9, R2, R5 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_addPKfS0_Pf
.globl _Z10matrix_addPKfS0_Pf
.p2align 8
.type _Z10matrix_addPKfS0_Pf,@function
_Z10matrix_addPKfS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_addPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_addPKfS0_Pf, .Lfunc_end0-_Z10matrix_addPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_addPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_addPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 426 | 2,274 |
5 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00124e24_00000000-6_adder.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%02.0f "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPKfii
.type _Z12print_matrixPKfii, @function
_Z12print_matrixPKfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
testl %edx, %edx
je .L3
movl %esi, %r15d
movslq %edx, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
addl %r15d, %r14d
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L3
.L5:
testl %r15d, %r15d
jne .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPKfii, .-_Z12print_matrixPKfii
.globl _Z15create_matrix_dPPfii
.type _Z15create_matrix_dPPfii, @function
_Z15create_matrix_dPPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
imull %edx, %esi
movslq %esi, %rbx
salq $2, %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
movq 0(%rbp), %rdi
movq %rbx, %rdx
movl $0, %esi
call cudaMemset@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15create_matrix_dPPfii, .-_Z15create_matrix_dPPfii
.globl _Z15create_matrix_hPPfii
.type _Z15create_matrix_hPPfii, @function
_Z15create_matrix_hPPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
imull %edx, %esi
movslq %esi, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 0(%rbp)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z15create_matrix_hPPfii, .-_Z15create_matrix_hPPfii
.globl _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
.type _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf, @function
_Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_addPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf, .-_Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
.globl _Z10matrix_addPKfS0_Pf
.type _Z10matrix_addPKfS0_Pf, @function
_Z10matrix_addPKfS0_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10matrix_addPKfS0_Pf, .-_Z10matrix_addPKfS0_Pf
.section .rodata.str1.1
.LC3:
.string "first matrix\n"
.LC4:
.string "second matrix\n"
.LC5:
.string "resultant matrix\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 8(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 16(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 24(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
leaq 32(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
leaq 40(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
movq (%rsp), %rbp
movq 8(%rsp), %rbx
movq %rbp, %rdi
movq %rbx, %rsi
movl $0, %ecx
movss .LC2(%rip), %xmm1
.L24:
movl $0, %eax
.L25:
leal (%rcx,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rdi,%rax,4)
movss %xmm1, (%rsi,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L25
addl $32, %ecx
subq $-128, %rdi
subq $-128, %rsi
cmpl $1024, %ecx
jne .L24
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $4, 60(%rsp)
movl $4, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 16(%rsp), %r12
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %rbp, %rdi
call _Z12print_matrixPKfii
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %r12, %rdi
call _Z12print_matrixPKfii
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10matrix_addPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_addPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "adder.hip"
.globl _Z25__device_stub__matrix_addPKfS0_Pf
.type _Z25__device_stub__matrix_addPKfS0_Pf,@function
_Z25__device_stub__matrix_addPKfS0_Pf:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10matrix_addPKfS0_Pf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_addPKfS0_Pf, .Lfunc_end0-_Z25__device_stub__matrix_addPKfS0_Pf
.cfi_endproc
.globl _Z12print_matrixPKfii
.type _Z12print_matrixPKfii,@function
_Z12print_matrixPKfii:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp)
testl %edx, %edx
je .LBB1_6
movq %rdi, %r14
movslq 4(%rsp), %r15
movl %edx, %r12d
movl %r15d, %r13d
shlq $2, %r15
xorl %ebp, %ebp
.LBB1_2:
cmpl $0, 4(%rsp)
je .LBB1_5
xorl %ebx, %ebx
.LBB1_4:
xorps %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_4
.LBB1_5:
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r15, %r14
cmpq %r12, %rbp
jne .LBB1_2
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPKfii, .Lfunc_end1-_Z12print_matrixPKfii
.cfi_endproc
.globl _Z15create_matrix_dPPfii
.type _Z15create_matrix_dPPfii,@function
_Z15create_matrix_dPPfii:
.cfi_startproc
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
imull %edx, %esi
movslq %esi, %r14
shlq $2, %r14
movq %r14, %rsi
callq hipMalloc
movq (%rbx), %rdi
xorl %esi, %esi
movq %r14, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp hipMemset
.Lfunc_end2:
.size _Z15create_matrix_dPPfii, .Lfunc_end2-_Z15create_matrix_dPPfii
.cfi_endproc
.globl _Z15create_matrix_hPPfii
.type _Z15create_matrix_hPPfii,@function
_Z15create_matrix_hPPfii:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
imull %edx, %esi
movslq %esi, %rsi
shlq $2, %rsi
movl $1, %edi
callq calloc@PLT
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15create_matrix_hPPfii, .Lfunc_end3-_Z15create_matrix_hPPfii
.cfi_endproc
.globl main
.type main,@function
main:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %edi
movl $4096, %esi
callq calloc@PLT
movq %rax, %r15
movl $1, %edi
movl $4096, %esi
callq calloc@PLT
movq %rax, %r14
movl $1, %edi
movl $4096, %esi
callq calloc@PLT
movq %rax, %rbx
leaq 24(%rsp), %r12
movl $4096, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
xorl %r13d, %r13d
movl $4096, %edx
xorl %esi, %esi
callq hipMemset
leaq 16(%rsp), %r12
movl $4096, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $4096, %edx
xorl %esi, %esi
callq hipMemset
leaq 8(%rsp), %r12
movl $4096, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $4096, %edx
xorl %esi, %esi
callq hipMemset
xorl %eax, %eax
.LBB4_1:
movl $32, %ecx
movq %r13, %rdx
.LBB4_2:
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r15,%rdx,4)
movl $1065353216, (%r14,%rdx,4)
incq %rdx
decq %rcx
jne .LBB4_2
incq %rax
addq $32, %r13
cmpq $32, %rax
jne .LBB4_1
movq 24(%rsp), %rdi
movl $4096, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi
movabsq $34359738376, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z25__device_stub__matrix_addPKfS0_Pf
.LBB4_6:
movq 8(%rsp), %rsi
movl $4096, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
movq %r15, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbx, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_ctor,@function
__hip_module_ctor:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB5_2
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_addPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_dtor,@function
__hip_module_dtor:
.cfi_startproc
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
.type _Z10matrix_addPKfS0_Pf,@object
.section .rodata,"a",@progbits
.globl _Z10matrix_addPKfS0_Pf
.p2align 3, 0x0
_Z10matrix_addPKfS0_Pf:
.quad _Z25__device_stub__matrix_addPKfS0_Pf
.size _Z10matrix_addPKfS0_Pf, 8
.type .L.str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%02.0f "
.size .L.str, 8
.type .L__unnamed_1,@object
.L__unnamed_1:
.asciz "_Z10matrix_addPKfS0_Pf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230
.long 1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.type .Lstr,@object
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "first matrix"
.size .Lstr, 13
.type .Lstr.1,@object
.Lstr.1:
.asciz "second matrix"
.size .Lstr.1, 14
.type .Lstr.2,@object
.Lstr.2:
.asciz "resultant matrix"
.size .Lstr.2, 17
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_addPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_addPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
``` | 5,103 | 4,760 |
8 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
BSSY B0, 0x1c0 ;
S2R R5, SR_CTAID.X ;
S2R R4, SR_TID.X ;
S2R R6, SR_CTAID.Y ;
S2R R11, SR_TID.Y ;
IMAD R5, R5, c[0x0][0x0], R4 ;
I2F.U32 R4, R5 ;
IMAD R2, R6, c[0x0][0x4], R11 ;
I2F R7, R3 ;
MUFU.RCP R0, R7 ;
FCHK P0, R4, R7 ;
FFMA R9, -R7, R0, 1 ;
FFMA R9, R0, R9, R0 ;
IMAD R0, R2, R3, R5 ;
FFMA R6, R4, R9, RZ ;
IMAD R0, R0, 0x3, RZ ;
FFMA R3, -R7, R6, R4 ;
FFMA R3, R9, R3, R6 ;
@!P0 BRA 0x1b0 ;
IMAD.MOV.U32 R8, RZ, RZ, R4 ;
MOV R4, 0x1b0 ;
CALL.REL.NOINC 0x570 ;
BSYNC B0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ;
LDG.E R6, [R6.64] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ;
LDG.E R5, [R4.64] ;
BSSY B0, 0x350 ;
I2F R9, R6 ;
IMAD.IADD R8, R2, 0x1, R5 ;
HFMA2.MMA R2, -RZ, RZ, 2.15625, 0 ;
I2F.U32 R8, R8 ;
FFMA R2, R3, R2, -2 ;
MUFU.RCP R10, R9 ;
FCHK P0, R8, R9 ;
FFMA R11, -R9, R10, 1 ;
FFMA R11, R10, R11, R10 ;
FFMA R10, R8, R11, RZ ;
FFMA R7, -R9, R10, R8 ;
FFMA R7, R11, R7, R10 ;
@!P0 BRA 0x340 ;
IMAD.MOV.U32 R7, RZ, RZ, R9 ;
MOV R4, 0x330 ;
CALL.REL.NOINC 0x570 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
BSYNC B0 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x40200000 ;
BSSY B0, 0x470 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
CS2R R4, SRZ ;
FFMA R8, R7, R6, -1.25 ;
CS2R R6, SRZ ;
FADD R3, -R6, R3 ;
IADD3 R4, R4, 0x1, RZ ;
FADD R6, R7, R7 ;
FADD R7, R2, R3 ;
ISETP.GE.U32.AND P0, PT, R4, 0x100, PT ;
FFMA R5, R6, R5, R8 ;
FMUL R3, R7, R7 ;
FMUL R6, R5, R5 ;
FADD R9, R6, R3 ;
FSETP.LE.AND P1, PT, R9, 4, PT ;
@!P0 BRA P1, 0x3b0 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ;
LDG.E R3, [R2.64] ;
ISETP.GE.AND P0, PT, R0, R3, PT ;
@P0 EXIT ;
ISETP.NE.AND P0, PT, R4, 0x100, PT ;
IADD3 R2, P1, R0, c[0x0][0x160], RZ ;
LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ;
STG.E.U8 [R2.64], RZ ;
@P0 STG.E.U8 [R2.64+0x1], R4 ;
@P0 STG.E.U8 [R2.64+0x2], RZ ;
@P0 EXIT ;
MOV R0, 0x1 ;
STG.E.U8 [R2.64+0x2], RZ ;
STG.E.U8 [R2.64+0x1], R0 ;
EXIT ;
SHF.R.U32.HI R5, RZ, 0x17, R7.reuse ;
BSSY B1, 0xbd0 ;
SHF.R.U32.HI R3, RZ, 0x17, R8 ;
IMAD.MOV.U32 R6, RZ, RZ, R7 ;
LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R3, RZ, RZ, R8 ;
IADD3 R12, R11, -0x1, RZ ;
IADD3 R10, R9, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0x7b0 ;
FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0xbb0 ;
LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ;
@!P0 BRA 0xb90 ;
FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ;
@!P1 BRA !P2, 0xb90 ;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0xb70 ;
LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0xb40 ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
ISETP.GE.AND P1, PT, R12, RZ, PT ;
@P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ;
@!P0 FFMA R3, R8, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R6, R7, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R5, R5, 0x40, RZ ;
LEA R7, R11, 0xc0800000, 0x17 ;
BSSY B2, 0xb30 ;
IMAD.IADD R7, R6, 0x1, -R7 ;
IADD3 R6, R9, -0x7f, RZ ;
MUFU.RCP R8, R7 ;
FADD.FTZ R10, -R7, -RZ ;
IMAD R3, R6, -0x800000, R3 ;
FFMA R9, R8, R10, 1 ;
FFMA R12, R8, R9, R8 ;
FFMA R8, R3, R12, RZ ;
FFMA R9, R10, R8, R3 ;
FFMA R9, R12, R9, R8 ;
IADD3 R8, R6, 0x7f, -R11 ;
FFMA R10, R10, R9, R3 ;
IADD3 R8, R8, R5, RZ ;
FFMA R3, R12, R10, R9 ;
SHF.R.U32.HI R6, RZ, 0x17, R3 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R11, R6, 0x1, R8 ;
IADD3 R5, R11, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ;
@!P0 BRA 0xb10 ;
ISETP.GT.AND P0, PT, R11, 0xfe, PT ;
@P0 BRA 0xae0 ;
ISETP.GE.AND P0, PT, R11, 0x1, PT ;
@P0 BRA 0xb20 ;
ISETP.GE.AND P0, PT, R11, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xb20 ;
FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ;
IADD3 R8, R11.reuse, 0x20, RZ ;
FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ;
ISETP.NE.AND P2, PT, R11, RZ, PT ;
LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R5, R12, R10, R9 ;
ISETP.NE.AND P1, PT, R11, RZ, PT ;
IMAD.MOV R9, RZ, RZ, -R11 ;
LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ;
SHF.L.U32 R8, R7, R8, RZ ;
SEL R6, R9, RZ, P2 ;
ISETP.NE.AND P1, PT, R8, RZ, P1 ;
SHF.R.U32.HI R6, RZ, R6, R7 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R8, RZ, 0x1, R6 ;
SEL R5, RZ, 0x1, !P0 ;
LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ;
LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ;
IMAD.IADD R8, R8, 0x1, R5 ;
LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ;
BRA 0xb20 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xb20 ;
IMAD R3, R8, 0x800000, R3 ;
BSYNC B2 ;
BRA 0xbc0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xbc0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
BRA 0xbc0 ;
MUFU.RSQ R3, -QNAN ;
BRA 0xbc0 ;
FADD.FTZ R3, R8, R7 ;
BSYNC B1 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0xbf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x34
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[10:11], 0x0
s_load_b32 s3, s[6:7], 0x0
s_load_b32 s6, s[8:9], 0x0
s_lshr_b32 s7, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s10, v0
v_cvt_f32_i32_e32 v4, s3
v_cvt_f32_i32_e32 v5, s6
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v2, v2
v_div_scale_f32 v6, null, v4, v4, v3
v_div_scale_f32 v12, vcc_lo, v3, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v7, null, v5, v5, v2
v_rcp_f32_e32 v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
v_dual_fmac_f32 v9, v11, v9 :: v_dual_fmac_f32 v8, v10, v8
v_div_scale_f32 v10, s2, v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v15, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_mul_f32_e32 v11, v12, v8
v_fma_f32 v7, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v6, v11, v12
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v11, v12
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0x40200000
v_div_fmas_f32 v7, v7, v9, v13
v_mov_b32_e32 v9, -2.0
v_div_fixup_f32 v3, v6, v4, v3
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v8, 0
v_div_fixup_f32 v4, v7, v5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, 0 :: v_dual_fmamk_f32 v2, v3, 0x40500000, v9
v_dual_fmaak_f32 v3, s2, v4, 0xbfa00000 :: v_dual_mov_b32 v4, 0
s_mov_b32 s2, 0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v6, v7 :: v_dual_add_f32 v6, v8, v8
s_add_i32 s7, s6, 1
s_cmpk_gt_u32 s6, 0xfe
s_cselect_b32 s6, -1, 0
v_add_f32_e32 v8, v2, v5
v_fma_f32 v4, v4, v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v8, v8
v_mul_f32_e32 v7, v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v4, v4, v6
v_cmp_nge_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s7
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s6
s_or_b32 s2, s6, s2
s_mov_b32 s6, s7
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s0, s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0x100, v5
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, 1, v5
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_lshlrev_b16 v2, 8, v2
s_clause 0x1
global_store_b8 v[0:1], v3, off offset:2
global_store_b16 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 3,587 | 3,781 |
9 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001780a1_00000000-6_mandel_brot_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
.type _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_, @function
_Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_, .-_Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
.globl kernel
.type kernel, @function
kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "mandel_brot_kernel.hip"
.globl __device_stub__kernel
.type __device_stub__kernel,@function
__device_stub__kernel:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $kernel, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_ctor,@function
__hip_module_ctor:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_dtor,@function
__hip_module_dtor:
.cfi_startproc
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
.type kernel,@object
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230
.long 1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
``` | 1,915 | 1,798 |
10 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10kernel_addPKfS0_iPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x178] ;
MOV R11, c[0x0][0x0] ;
IMAD R0, R11, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
@!P0 BRA 0x70 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_addPKfS0_iPf
.globl _Z10kernel_addPKfS0_iPf
.p2align 8
.type _Z10kernel_addPKfS0_iPf,@function
_Z10kernel_addPKfS0_iPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_addPKfS0_iPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_addPKfS0_iPf, .Lfunc_end0-_Z10kernel_addPKfS0_iPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_addPKfS0_iPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_addPKfS0_iPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 472 | 2,471 |
11 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0005fcf2_00000000-6_kernel_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.type _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, @function
_Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_addPKfS0_iPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, .-_Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.globl _Z10kernel_addPKfS0_iPf
.type _Z10kernel_addPKfS0_iPf, @function
_Z10kernel_addPKfS0_iPf:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z10kernel_addPKfS0_iPf, .-_Z10kernel_addPKfS0_iPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_addPKfS0_iPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addPKfS0_iPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, @function
_GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf:
.LFB2174:
.cfi_startproc
ret
.cfi_endproc
.LFE2174:
.size _GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, .-_GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "kernel_add.hip"
.globl _Z25__device_stub__kernel_addPKfS0_iPf
.type _Z25__device_stub__kernel_addPKfS0_iPf,@function
_Z25__device_stub__kernel_addPKfS0_iPf:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 4(%rsp), %rsi
movl %edx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10kernel_addPKfS0_iPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_addPKfS0_iPf, .Lfunc_end0-_Z25__device_stub__kernel_addPKfS0_iPf
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_ctor,@function
__hip_module_ctor:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_addPKfS0_iPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_dtor,@function
__hip_module_dtor:
.cfi_startproc
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
.type _Z10kernel_addPKfS0_iPf,@object
.section .rodata,"a",@progbits
.globl _Z10kernel_addPKfS0_iPf
.p2align 3, 0x0
_Z10kernel_addPKfS0_iPf:
.quad _Z25__device_stub__kernel_addPKfS0_iPf
.size _Z10kernel_addPKfS0_iPf, 8
.type .L__unnamed_1,@object
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_addPKfS0_iPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230
.long 1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_addPKfS0_iPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_addPKfS0_iPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
``` | 2,111 | 1,923 |
12 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20sum_Matrices_columnaPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
IMAD R2, R2, c[0x0][0x4], R3 ;
ISETP.GT.AND P0, PT, R2, 0x4, PT ;
@P0 EXIT ;
S2R R3, SR_CTAID.X ;
IADD3 R4, -R2.reuse, 0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R5, -R2, 0x4, RZ ;
S2R R0, SR_TID.X ;
LOP3.LUT P1, R10, R4, 0x3, RZ, 0xc0, !PT ;
BSSY B0, 0x2f0 ;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ;
@!P1 BRA 0x2e0 ;
IMAD R5, R3, c[0x0][0x0], R0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD R8, R2, 0x5, R5 ;
IMAD.WIDE R4, R8, R9, c[0x0][0x170] ;
IMAD.WIDE R6, R8, R9, c[0x0][0x168] ;
MOV R14, R4 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
MOV R13, R7 ;
IMAD.MOV.U32 R15, RZ, RZ, R5 ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
IMAD.MOV.U32 R11, RZ, RZ, R9 ;
MOV R4, R12 ;
IMAD.MOV.U32 R7, RZ, RZ, R11 ;
MOV R6, R8 ;
IMAD.MOV.U32 R5, RZ, RZ, R13 ;
LDG.E R7, [R6.64] ;
LDG.E R4, [R4.64] ;
IADD3 R10, R10, -0x1, RZ ;
MOV R5, R15 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
IADD3 R8, P4, R8, 0x14, RZ ;
IADD3 R12, P3, R12, 0x14, RZ ;
IADD3 R2, R2, 0x1, RZ ;
IMAD.X R11, RZ, RZ, R11, P4 ;
IADD3.X R13, RZ, R13, RZ, P3, !PT ;
IADD3 R9, R4, R7, RZ ;
IMAD.MOV.U32 R4, RZ, RZ, R14 ;
STG.E [R4.64], R9 ;
IADD3 R14, P2, R14, 0x14, RZ ;
IMAD.X R15, RZ, RZ, R15, P2 ;
@P1 BRA 0x1a0 ;
BSYNC B0 ;
@!P0 EXIT ;
IMAD R3, R3, c[0x0][0x0], R0 ;
IADD3 R0, R2, -0x4, RZ ;
IMAD R8, R2, 0x5, R3 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R8, R3, c[0x0][0x168] ;
IMAD.WIDE R4, R8.reuse, R3.reuse, c[0x0][0x160] ;
LDG.E R9, [R6.64] ;
LDG.E R10, [R4.64] ;
IMAD.WIDE R2, R8, R3, c[0x0][0x170] ;
IMAD.IADD R9, R9, 0x1, R10 ;
STG.E [R2.64], R9 ;
LDG.E R10, [R6.64+0x14] ;
LDG.E R11, [R4.64+0x14] ;
IADD3 R11, R10, R11, RZ ;
STG.E [R2.64+0x14], R11 ;
LDG.E R10, [R6.64+0x28] ;
LDG.E R13, [R4.64+0x28] ;
IMAD.IADD R13, R10, 0x1, R13 ;
STG.E [R2.64+0x28], R13 ;
LDG.E R10, [R6.64+0x3c] ;
LDG.E R15, [R4.64+0x3c] ;
IADD3 R0, R0, 0x4, RZ ;
IADD3 R8, R8, 0x14, RZ ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
IADD3 R15, R10, R15, RZ ;
STG.E [R2.64+0x3c], R15 ;
@!P0 BRA 0x330 ;
EXIT ;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z17sum_Matrices_filaPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
S2R R3, SR_TID.X ;
S2R R9, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R8, R8, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R8, 0x4, PT ;
@P0 EXIT ;
IADD3 R0, -R8.reuse, 0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R3, -R8, 0x4, RZ ;
BSSY B0, 0x300 ;
LOP3.LUT P1, R10, R0, 0x3, RZ, 0xc0, !PT ;
IMAD R9, R9, c[0x0][0x4], R2 ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
@!P1 BRA 0x2f0 ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R9, 0x5, R8 ;
IMAD.WIDE R2, R6, R7, c[0x0][0x170] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
MOV R12, R4 ;
IMAD.MOV.U32 R14, RZ, RZ, R2 ;
MOV R11, R7 ;
IMAD.MOV.U32 R15, RZ, RZ, R3 ;
IMAD.MOV.U32 R13, RZ, RZ, R5 ;
IMAD.MOV.U32 R2, RZ, RZ, R12 ;
MOV R5, R11 ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
MOV R3, R13 ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IADD3 R10, R10, -0x1, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, R15 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
IADD3 R12, P3, R12, 0x4, RZ ;
IADD3 R6, P4, R6, 0x4, RZ ;
IADD3 R8, R8, 0x1, RZ ;
IMAD.X R13, RZ, RZ, R13, P3 ;
IADD3.X R11, RZ, R11, RZ, P4, !PT ;
IMAD.IADD R7, R2, 0x1, R5 ;
MOV R2, R14 ;
STG.E [R2.64], R7 ;
IADD3 R14, P2, R14, 0x4, RZ ;
IADD3.X R15, RZ, R15, RZ, P2, !PT ;
@P1 BRA 0x1b0 ;
BSYNC B0 ;
IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ;
MOV R2, c[0x0][0x168] ;
@!P0 EXIT ;
IMAD R9, R9, 0x5, R8 ;
MOV R4, c[0x0][0x160] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
IADD3 R8, R8, -0x4, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
IADD3 R15, R9, 0x1, RZ ;
IMAD.WIDE R18, R9, 0x4, R2 ;
IMAD.WIDE R6, R9, 0x4, R4 ;
LDG.E R18, [R18.64] ;
LDG.E R11, [R6.64] ;
IMAD.WIDE R12, R15, 0x4, R2 ;
MOV R6, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, R23 ;
IMAD.WIDE R20, R9, 0x4, R6 ;
IADD3 R23, R18, R11, RZ ;
IMAD.WIDE R10, R15.reuse, 0x4, R4 ;
STG.E [R20.64], R23 ;
LDG.E R0, [R12.64] ;
LDG.E R25, [R10.64] ;
IMAD.WIDE R16, R15, 0x4, R6 ;
IMAD.IADD R25, R0, 0x1, R25 ;
STG.E [R16.64], R25 ;
LDG.E R0, [R12.64+0x4] ;
LDG.E R19, [R10.64+0x4] ;
IADD3 R19, R0, R19, RZ ;
STG.E [R16.64+0x4], R19 ;
LDG.E R0, [R12.64+0x8] ;
LDG.E R21, [R10.64+0x8] ;
IADD3 R8, R8, 0x4, RZ ;
IADD3 R2, P2, R2, 0x10, RZ ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
IADD3 R4, P3, R4, 0x10, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
IADD3.X R5, RZ, R5, RZ, P3, !PT ;
IMAD.IADD R21, R0, 0x1, R21 ;
IADD3 R0, P1, R6, 0x10, RZ ;
STG.E [R16.64+0x8], R21 ;
IADD3.X R23, RZ, R7, RZ, P1, !PT ;
@!P0 BRA 0x390 ;
EXIT ;
BRA 0x5b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z19sum_Matrices_NormalPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GT.AND P0, PT, R3, 0x4, PT ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GT.OR P0, PT, R0, 0x4, P0 ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R0, R3, 0x5, R0 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R0, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19sum_Matrices_NormalPiS_S_
.globl _Z19sum_Matrices_NormalPiS_S_
.p2align 8
.type _Z19sum_Matrices_NormalPiS_S_,@function
_Z19sum_Matrices_NormalPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e32 5, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19sum_Matrices_NormalPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19sum_Matrices_NormalPiS_S_, .Lfunc_end0-_Z19sum_Matrices_NormalPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17sum_Matrices_filaPiS_S_
.globl _Z17sum_Matrices_filaPiS_S_
.p2align 8
.type _Z17sum_Matrices_filaPiS_S_,@function
_Z17sum_Matrices_filaPiS_S_:
s_load_b32 s4, s[0:1], 0x24
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e32 5, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v6, -1, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_mad_u64_u32 v[3:4], null, v2, 5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 0
.LBB1_2:
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_nc_u32_e32 v6, 1, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_lt_i32_e32 vcc_lo, 3, v6
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v8, v7
global_store_b32 v[4:5], v7, off
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sum_Matrices_filaPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17sum_Matrices_filaPiS_S_, .Lfunc_end1-_Z17sum_Matrices_filaPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20sum_Matrices_columnaPiS_S_
.globl _Z20sum_Matrices_columnaPiS_S_
.p2align 8
.type _Z20sum_Matrices_columnaPiS_S_,@function
_Z20sum_Matrices_columnaPiS_S_:
s_load_b32 s8, s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s8, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 5, v1
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v3, v1, 2, v1
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s0, s8, 0xffff
v_add_nc_u32_e32 v2, -1, v1
s_mul_i32 s14, s14, s0
s_mov_b32 s1, 0
v_add3_u32 v0, v0, s14, v3
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 1, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, 5, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 3, v2
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sum_Matrices_columnaPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20sum_Matrices_columnaPiS_S_, .Lfunc_end2-_Z20sum_Matrices_columnaPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19sum_Matrices_NormalPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19sum_Matrices_NormalPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sum_Matrices_filaPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sum_Matrices_filaPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sum_Matrices_columnaPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20sum_Matrices_columnaPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 3,649 | 7,090 |
13 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002ae34_00000000-6_sum.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15imprimir_MatrizPA5_i
.type _Z15imprimir_MatrizPA5_i, @function
_Z15imprimir_MatrizPA5_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 20(%rdi), %rbp
leaq 120(%rdi), %r13
leaq _ZSt4cout(%rip), %r12
jmp .L4
.L5:
movl $32, %esi
call _ZNSo3putEc@PLT
.L6:
addq $4, %rbx
cmpq %rbp, %rbx
je .L16
.L7:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L5
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.L16:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L17
cmpb $0, 56(%rbx)
je .L10
movzbl 67(%rbx), %esi
.L11:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %rbp
cmpq %r13, %rbp
je .L3
.L4:
leaq -20(%rbp), %rbx
jmp .L7
.L17:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L10:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z15imprimir_MatrizPA5_i, .-_Z15imprimir_MatrizPA5_i
.globl _Z15imprimir_vectorPi
.type _Z15imprimir_vectorPi, @function
_Z15imprimir_vectorPi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rdi, %rbx
leaq 20(%rdi), %rbp
leaq _ZSt4cout(%rip), %r12
jmp .L23
.L21:
movl $32, %esi
call _ZNSo3putEc@PLT
.L22:
addq $4, %rbx
cmpq %rbp, %rbx
je .L27
.L23:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L21
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L22
.L27:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z15imprimir_vectorPi, .-_Z15imprimir_vectorPi
.globl _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
.type _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_, @function
_Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19sum_Matrices_NormalPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_, .-_Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
.globl _Z19sum_Matrices_NormalPiS_S_
.type _Z19sum_Matrices_NormalPiS_S_, @function
_Z19sum_Matrices_NormalPiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z19sum_Matrices_NormalPiS_S_, .-_Z19sum_Matrices_NormalPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $384, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 48(%rsp), %rax
leaq 160(%rsp), %rdx
leaq 148(%rsp), %rcx
.L38:
movl $1, (%rax)
movl $1, (%rdx)
movl $1, 4(%rax)
movl $1, 4(%rdx)
movl $1, 8(%rax)
movl $1, 8(%rdx)
movl $1, 12(%rax)
movl $1, 12(%rdx)
movl $1, 16(%rax)
movl $1, 16(%rdx)
addq $20, %rax
addq $20, %rdx
cmpq %rcx, %rax
jne .L38
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call _Z15imprimir_MatrizPA5_i
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 160(%rsp), %rbx
movq %rbx, %rdi
call _Z15imprimir_MatrizPA5_i
movq %rsp, %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 24(%rsp)
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L39:
call cudaDeviceSynchronize@PLT
leaq 272(%rsp), %rbp
movl $2, %ecx
movl $100, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 372(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L40:
movl $0, %ebx
.L41:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L41
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %r14, %rbp
jne .L40
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
jmp .L39
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
.type _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_, @function
_Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sum_Matrices_filaPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_, .-_Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
.globl _Z17sum_Matrices_filaPiS_S_
.type _Z17sum_Matrices_filaPiS_S_, @function
_Z17sum_Matrices_filaPiS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17sum_Matrices_filaPiS_S_, .-_Z17sum_Matrices_filaPiS_S_
.globl _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
.type _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_, @function
_Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_:
.LFB3700:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20sum_Matrices_columnaPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_, .-_Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
.globl _Z20sum_Matrices_columnaPiS_S_
.type _Z20sum_Matrices_columnaPiS_S_, @function
_Z20sum_Matrices_columnaPiS_S_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z20sum_Matrices_columnaPiS_S_, .-_Z20sum_Matrices_columnaPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20sum_Matrices_columnaPiS_S_"
.section .rodata.str1.1
.LC3:
.string "_Z17sum_Matrices_filaPiS_S_"
.LC4:
.string "_Z19sum_Matrices_NormalPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sum_Matrices_columnaPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sum_Matrices_filaPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19sum_Matrices_NormalPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "sum.hip"
.globl _ZSt21ios_base_library_initv
.globl _Z34__device_stub__sum_Matrices_NormalPiS_S_
.type _Z34__device_stub__sum_Matrices_NormalPiS_S_,@function
_Z34__device_stub__sum_Matrices_NormalPiS_S_:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z19sum_Matrices_NormalPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__sum_Matrices_NormalPiS_S_, .Lfunc_end0-_Z34__device_stub__sum_Matrices_NormalPiS_S_
.cfi_endproc
.globl _Z32__device_stub__sum_Matrices_filaPiS_S_
.type _Z32__device_stub__sum_Matrices_filaPiS_S_,@function
_Z32__device_stub__sum_Matrices_filaPiS_S_:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17sum_Matrices_filaPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z32__device_stub__sum_Matrices_filaPiS_S_, .Lfunc_end1-_Z32__device_stub__sum_Matrices_filaPiS_S_
.cfi_endproc
.globl _Z35__device_stub__sum_Matrices_columnaPiS_S_
.type _Z35__device_stub__sum_Matrices_columnaPiS_S_,@function
_Z35__device_stub__sum_Matrices_columnaPiS_S_:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20sum_Matrices_columnaPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z35__device_stub__sum_Matrices_columnaPiS_S_, .Lfunc_end2-_Z35__device_stub__sum_Matrices_columnaPiS_S_
.cfi_endproc
.globl _Z15imprimir_MatrizPA5_i
.type _Z15imprimir_MatrizPA5_i,@function
_Z15imprimir_MatrizPA5_i:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
movl $_ZSt4cout, %r12d
leaq 15(%rsp), %r14
.LBB3_1:
xorl %r13d, %r13d
.LBB3_2:
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_6
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_7
.LBB3_6:
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB3_7:
incq %r13
cmpq $5, %r13
jne .LBB3_2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $20, %rbx
cmpq $5, %r15
jne .LBB3_1
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15imprimir_MatrizPA5_i, .Lfunc_end3-_Z15imprimir_MatrizPA5_i
.cfi_endproc
.globl _Z15imprimir_vectorPi
.type _Z15imprimir_vectorPi,@function
_Z15imprimir_vectorPi:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 15(%rsp), %r14
.LBB4_1:
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB4_3
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_4
.LBB4_3:
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB4_4:
incq %r15
cmpq $5, %r15
jne .LBB4_1
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15imprimir_vectorPi, .Lfunc_end4-_Z15imprimir_vectorPi
.cfi_endproc
.globl main
.type main,@function
main:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $368, %rsp
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 144(%rsp), %rax
leaq 32(%rsp), %rcx
movl $1, %edx
.LBB5_1:
xorl %esi, %esi
.LBB5_2:
movl %edx, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $5, %rsi
jne .LBB5_2
incq %rbx
addq $20, %rax
addq $20, %rcx
cmpq $5, %rbx
jne .LBB5_1
leaq 144(%rsp), %rbx
movq %rbx, %rdi
callq _Z15imprimir_MatrizPA5_i
movl $_ZSt4cout, %r13d
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 32(%rsp), %r14
movq %r14, %rdi
callq _Z15imprimir_MatrizPA5_i
leaq 24(%rsp), %r15
movl $100, %esi
movq %r15, %rdi
callq hipMalloc
leaq 16(%rsp), %r12
movl $100, %esi
movq %r12, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq (%r15), %rdi
movl $100, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $100, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi
movabsq $21474836485, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z34__device_stub__sum_Matrices_NormalPiS_S_
.LBB5_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
leaq 256(%rsp), %rbx
movl $100, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
.LBB5_7:
xorl %r15d, %r15d
.LBB5_8:
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB5_8
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $5, %r14
jne .LBB5_7
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $368, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_ctor,@function
__hip_module_ctor:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB6_2
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19sum_Matrices_NormalPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sum_Matrices_filaPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sum_Matrices_columnaPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
.p2align 4, 0x90
.type __hip_module_dtor,@function
__hip_module_dtor:
.cfi_startproc
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
.type _Z19sum_Matrices_NormalPiS_S_,@object
.section .rodata,"a",@progbits
.globl _Z19sum_Matrices_NormalPiS_S_
.p2align 3, 0x0
_Z19sum_Matrices_NormalPiS_S_:
.quad _Z34__device_stub__sum_Matrices_NormalPiS_S_
.size _Z19sum_Matrices_NormalPiS_S_, 8
.type _Z17sum_Matrices_filaPiS_S_,@object
.globl _Z17sum_Matrices_filaPiS_S_
.p2align 3, 0x0
_Z17sum_Matrices_filaPiS_S_:
.quad _Z32__device_stub__sum_Matrices_filaPiS_S_
.size _Z17sum_Matrices_filaPiS_S_, 8
.type _Z20sum_Matrices_columnaPiS_S_,@object
.globl _Z20sum_Matrices_columnaPiS_S_
.p2align 3, 0x0
_Z20sum_Matrices_columnaPiS_S_:
.quad _Z35__device_stub__sum_Matrices_columnaPiS_S_
.size _Z20sum_Matrices_columnaPiS_S_, 8
.type .L.str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object
.L__unnamed_1:
.asciz "_Z19sum_Matrices_NormalPiS_S_"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object
.L__unnamed_2:
.asciz "_Z17sum_Matrices_filaPiS_S_"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object
.L__unnamed_3:
.asciz "_Z20sum_Matrices_columnaPiS_S_"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230
.long 1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__sum_Matrices_NormalPiS_S_
.addrsig_sym _Z32__device_stub__sum_Matrices_filaPiS_S_
.addrsig_sym _Z35__device_stub__sum_Matrices_columnaPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19sum_Matrices_NormalPiS_S_
.addrsig_sym _Z17sum_Matrices_filaPiS_S_
.addrsig_sym _Z20sum_Matrices_columnaPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
``` | 7,547 | 7,239 |
16 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
``` | ```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
``` | 24 | 293 |
17 | Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d7a49_00000000-6_cuda_syn_block.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12__syncblocksPVj
.type _Z12__syncblocksPVj, @function
_Z12__syncblocksPVj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12__syncblocksPVj, .-_Z12__syncblocksPVj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
``` | ```amdasm
.text
.file "cuda_syn_block.hip"
.type __hip_cuid_,@object
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
``` | 922 | 172 |
18 | Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R34, SR_TID.X ;
ULDC UR5, c[0x3][0x20] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x3][0x0] ;
ULEA UR6, UR5, 0x4, 0x2 ;
S2UR UR4, SR_CTAID.X ;
IADD3 R32, R3.reuse, c[0x3][0x20], RZ ;
IADD3 R29, R3, -c[0x3][0x8], RZ ;
IADD3 R0, R32, -0x1, RZ ;
IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
IMAD.SHL.U32 R31, R34, 0x4, RZ ;
STS [R34.X4], RZ ;
IMAD R29, R29, UR4, RZ ;
IADD3 R30, R31, UR6, RZ ;
STS [R31+UR6], RZ ;
IMAD R28, R3, UR4, -R34 ;
STS [R30+UR6], RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 EXIT ;
ISETP.NE.AND P0, PT, R32, 0x2, PT ;
UMOV UR4, URZ ;
IADD3 R27, R34, c[0x0][0x1a8], RZ ;
UIADD3 UR5, UR5, -0x1, URZ ;
IMAD.IADD R26, R29.reuse, 0x1, -R34 ;
ULDC.64 UR8, c[0x0][0x118] ;
IADD3 R25, R29, c[0x3][0x0], RZ ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
CS2R R22, SRZ ;
CS2R R16, SRZ ;
CS2R R20, SRZ ;
IMAD.MOV.U32 R37, RZ, RZ, RZ ;
IMAD.MOV.U32 R19, RZ, RZ, RZ ;
@!P0 BRA 0xc70 ;
LOP3.LUT R3, R0.reuse, 0x1, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
CS2R R22, SRZ ;
CS2R R16, SRZ ;
IMAD.IADD R0, R0, 0x1, -R3 ;
CS2R R20, SRZ ;
IMAD.MOV.U32 R37, RZ, RZ, RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R19, RZ, RZ, RZ ;
ISETP.GE.AND P0, PT, R26, c[0x3][0xc], PT ;
IMAD.SHL.U32 R8, R28, 0x4, RZ ;
ISETP.LT.AND P1, PT, R26.reuse, R25, !P1 ;
IMAD.MOV.U32 R33, RZ, RZ, 0x4 ;
ISETP.GE.AND P0, PT, R26, R29, !P0 ;
BSSY B0, 0x550 ;
SHF.R.S32.HI R35, RZ, 0x1f, R28 ;
IMAD.WIDE R10, R28, R33, c[0x0][0x170] ;
PLOP3.LUT P1, PT, P0, P1, PT, 0x80, 0x0 ;
IADD3 R2, P2, R8, c[0x0][0x180], RZ ;
IMAD.WIDE R12, R28, R33.reuse, c[0x0][0x188] ;
IADD3 R4, P3, R8.reuse, c[0x0][0x1a0], RZ ;
IADD3 R6, P4, R8, c[0x0][0x178], RZ ;
IMAD.WIDE R14, R28, R33, c[0x0][0x190] ;
IADD3 R8, P5, R8, c[0x0][0x198], RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
SHF.L.U64.HI R35, R28, 0x2, R35 ;
@!P1 BRA 0x540 ;
IADD3 R16, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R37, [R31+UR6] ;
LEA.HI.X.SX32 R17, R26, c[0x0][0x164], 0x1, P0 ;
LDG.E.S8 R16, [R16.64] ;
LDS R17, [R30+UR6] ;
IMAD R18, R16, c[0x3][0x10], R27 ;
LDS R16, [R34.X4] ;
IMAD.WIDE R18, R18, R33, c[0x0][0x168] ;
LDG.E R19, [R18.64] ;
ISETP.NE.AND P1, PT, R34, RZ, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P1 BRA 0x540 ;
ISETP.GE.AND P0, PT, R28, 0x1, PT ;
LDG.E R16, [R10.64] ;
LDG.E R37, [R12.64] ;
LDG.E R17, [R14.64] ;
@P0 LDG.E R24, [R14.64+-0x4] ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
@P0 LDG.E R22, [R10.64+-0x4] ;
ISETP.EQ.OR P1, PT, RZ, c[0x0][0x1a8], !P1 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
SEL R24, R26, R24, P1 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
IADD3.X R3, R35.reuse, c[0x0][0x184], RZ, P2, !PT ;
IADD3.X R5, R35.reuse, c[0x0][0x1a4], RZ, P3, !PT ;
IADD3.X R7, R35.reuse, c[0x0][0x17c], RZ, P4, !PT ;
BSSY B0, 0x7c0 ;
IADD3.X R9, R35, c[0x0][0x19c], RZ, P5, !PT ;
@!P0 BRA 0x7b0 ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IMAD.IADD R22, R22, 0x1, R19 ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IADD3 R18, R37, -c[0x3][0x18], RZ ;
IMNMX R20, R21, R20, !PT ;
IADD3 R21, R16, -c[0x3][0x14], RZ ;
IMNMX R18, R18, R21, !PT ;
IMNMX R21, RZ, R18, !PT ;
IMNMX R21, R20, R21, !PT ;
IMNMX R21, R21, R22, !PT ;
ISETP.NE.AND P0, PT, R21, R20, PT ;
SEL R22, R23, R24, !P0 ;
LDG.E R24, [R2.64] ;
ISETP.NE.AND P0, PT, R21.reuse, RZ, PT ;
ISETP.NE.AND P3, PT, R34, UR5, PT ;
STS [R31+UR6+0x4], R18 ;
ISETP.NE.AND P1, PT, R21, R18, PT ;
STS [R34.X4+0x4], R21 ;
SEL R23, R17, R22, !P1 ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
@!P0 IADD3 R23, R26, 0x1, RZ ;
@!P3 IMAD.MOV.U32 R22, RZ, RZ, R16 ;
STS [R30+UR6+0x4], R23 ;
ISETP.GE.AND P2, PT, R21, R24, PT ;
IMAD.MOV.U32 R24, RZ, RZ, R17.reuse ;
@!P3 IMAD.MOV.U32 R24, RZ, RZ, R17 ;
@P2 STG.E [R2.64], R21 ;
@P2 STG.E [R4.64], R23 ;
@!P3 STG.E [R6.64], R21 ;
@!P3 STG.E [R12.64], R18 ;
@!P3 STG.E [R8.64], R23 ;
BSYNC B0 ;
IADD3 R36, R26, 0x1, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
ISETP.GE.AND P0, PT, R36.reuse, c[0x3][0xc], PT ;
ISETP.LT.AND P2, PT, R36.reuse, R25, !P1 ;
BSSY B0, 0x9c0 ;
ISETP.GE.AND P0, PT, R36, R29, !P0 ;
PLOP3.LUT P2, PT, P0, P2, PT, 0x80, 0x0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P2 BRA 0x9b0 ;
IADD3 R16, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R37, [R31+UR6] ;
LEA.HI.X.SX32 R17, R26, c[0x0][0x164], 0x1, P0 ;
LDG.E.S8 R16, [R16.64+0x1] ;
LDS R17, [R30+UR6] ;
IMAD R18, R16, c[0x3][0x10], R27 ;
LDS R16, [R34.X4] ;
IMAD.WIDE R18, R18, R33, c[0x0][0x168] ;
LDG.E R19, [R18.64] ;
ISETP.NE.AND P2, PT, R34, RZ, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P2 BRA 0x9b0 ;
ISETP.GE.AND P0, PT, R28, RZ, PT ;
LDG.E R17, [R14.64+0x4] ;
LDG.E R16, [R10.64+0x4] ;
LDG.E R37, [R12.64+0x4] ;
@P0 LDG.E R24, [R14.64] ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a8], PT ;
@P0 LDG.E R22, [R10.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
SEL R24, R36, R24, !P2 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xbf0 ;
@!P0 BRA 0xbe0 ;
LDG.E R10, [R2.64+0x4] ;
IADD3 R11, R37, -c[0x3][0x18], RZ ;
IMAD.IADD R18, R22, 0x1, R19 ;
IADD3 R14, R16, -c[0x3][0x14], RZ ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IMNMX R14, R11, R14, !PT ;
IMNMX R20, R21, R20, !PT ;
IMNMX R11, RZ, R14, !PT ;
STS [R31+UR6+0x4], R14 ;
ISETP.NE.AND P4, PT, R34, UR5, PT ;
IMNMX R11, R20, R11, !PT ;
IMNMX R21, R11, R18, !PT ;
ISETP.NE.AND P2, PT, R21.reuse, RZ, PT ;
STS [R34.X4+0x4], R21 ;
ISETP.NE.AND P3, PT, R21.reuse, R20, PT ;
@!P4 IMAD.MOV.U32 R22, RZ, RZ, R16 ;
ISETP.GE.AND P0, PT, R21, R10, PT ;
SEL R10, R23, R24, !P3 ;
IMAD.MOV.U32 R24, RZ, RZ, R17.reuse ;
ISETP.NE.AND P3, PT, R21, R14, PT ;
@!P4 IMAD.MOV.U32 R24, RZ, RZ, R17 ;
SEL R23, R17, R10, !P3 ;
@!P2 IADD3 R23, R26, 0x2, RZ ;
@P0 STG.E [R2.64+0x4], R21 ;
@P0 STG.E [R4.64+0x4], R23 ;
@!P4 STG.E [R6.64+0x4], R21 ;
@!P4 STG.E [R12.64+0x4], R14 ;
STS [R30+UR6+0x4], R23 ;
@!P4 STG.E [R8.64+0x4], R23 ;
BSYNC B0 ;
IADD3 R0, R0, -0x2, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
UIADD3 UR4, UR4, 0x2, URZ ;
IADD3 R26, R26, 0x2, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IADD3 R28, R28, 0x2, RZ ;
@P0 BRA 0x2c0 ;
UMOV UR4, 0x1 ;
IADD3 R32, R32, -0x1, RZ ;
LOP3.LUT P0, RZ, R32, 0x1, RZ, 0xc0, !PT ;
@!P0 EXIT ;
ISETP.GE.AND P0, PT, R26.reuse, c[0x3][0xc], PT ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
BSSY B0, 0xed0 ;
ISETP.GE.AND P0, PT, R26, R29, !P0 ;
IMAD.WIDE R2, R28, R11, c[0x0][0x188] ;
ISETP.LT.AND P1, PT, R26, R25, !P1 ;
SHF.R.S32.HI R9, RZ, 0x1f, R28 ;
PLOP3.LUT P1, PT, P0, P1, PT, 0x80, 0x0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P1 BRA 0xec0 ;
IADD3 R6, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R16, [R34.X4] ;
LEA.HI.X.SX32 R7, R26, c[0x0][0x164], 0x1, P0 ;
LDS R37, [R31+UR6] ;
LDG.E.S8 R6, [R6.64] ;
LDS R17, [R30+UR6] ;
ISETP.NE.AND P1, PT, R34, RZ, PT ;
IMAD R4, R6, c[0x3][0x10], R27 ;
IMAD.WIDE R4, R4, R11, c[0x0][0x168] ;
LDG.E R19, [R4.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P1 BRA 0xec0 ;
ISETP.GE.AND P1, PT, R28.reuse, 0x1, PT ;
IMAD.WIDE R6, R28.reuse, R11.reuse, c[0x0][0x190] ;
LDG.E R37, [R2.64] ;
IMAD.WIDE R4, R28, R11, c[0x0][0x170] ;
LDG.E R17, [R6.64] ;
LDG.E R16, [R4.64] ;
@P1 LDG.E R24, [R6.64+-0x4] ;
@P1 LDG.E R22, [R4.64+-0x4] ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
ISETP.EQ.OR P1, PT, RZ, c[0x0][0x1a8], !P1 ;
SEL R24, R26, R24, P1 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x1160 ;
@!P0 BRA 0x1150 ;
IMAD.SHL.U32 R8, R28.reuse, 0x4, RZ ;
SHF.L.U64.HI R28, R28, 0x2, R9 ;
IADD3 R4, P0, R8, c[0x0][0x180], RZ ;
IADD3.X R5, R28, c[0x0][0x184], RZ, P0, !PT ;
LDG.E R6, [R4.64] ;
IADD3 R0, R37, -c[0x3][0x18], RZ ;
IMAD.IADD R22, R19, 0x1, R22 ;
IADD3 R7, R16, -c[0x3][0x14], RZ ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IMNMX R0, R0, R7, !PT ;
IMNMX R20, R21, R20, !PT ;
IMNMX R7, RZ, R0, !PT ;
STS [R31+UR6+0x4], R0 ;
IMNMX R7, R20, R7, !PT ;
IMNMX R9, R7, R22, !PT ;
ISETP.NE.AND P1, PT, R9.reuse, R0, PT ;
STS [R34.X4+0x4], R9 ;
ISETP.NE.AND P0, PT, R9.reuse, RZ, PT ;
ISETP.NE.AND P2, PT, R9, R20, PT ;
@P1 SEL R17, R23, R24, !P2 ;
@!P0 IADD3 R17, R26, 0x1, RZ ;
ISETP.NE.AND P0, PT, R34, UR5, PT ;
STS [R30+UR6+0x4], R17 ;
ISETP.GE.AND P3, PT, R9, R6, PT ;
@P3 IADD3 R6, P1, R8, c[0x0][0x1a0], RZ ;
@P3 STG.E [R4.64], R9 ;
@P3 IADD3.X R7, R28, c[0x0][0x1a4], RZ, P1, !PT ;
@P3 STG.E [R6.64], R17 ;
@P0 BRA 0x1150 ;
IADD3 R4, P0, R8.reuse, c[0x0][0x178], RZ ;
IADD3 R6, P1, R8, c[0x0][0x198], RZ ;
IADD3.X R5, R28.reuse, c[0x0][0x17c], RZ, P0, !PT ;
IADD3.X R7, R28, c[0x0][0x19c], RZ, P1, !PT ;
STG.E [R4.64], R9 ;
STG.E [R2.64], R0 ;
STG.E [R6.64], R17 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0x1180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
``` | ```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.globl _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.p2align 8
.type _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i,@function
_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, queryPartLength@rel32@lo+4
s_addc_u32 s3, s3, queryPartLength@rel32@hi+12
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_load_b32 s4, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, partSeqSize@rel32@lo+4
s_addc_u32 s3, s3, partSeqSize@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
v_add_nc_u32_e32 v18, 0, v4
ds_store_b32 v18, v1
s_waitcnt lgkmcnt(0)
s_lshl_b32 s5, s4, 2
s_add_i32 s4, s4, -1
s_add_i32 s6, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s6, 4
v_add_nc_u32_e32 v19, s6, v4
s_add_i32 s5, s3, s5
s_add_i32 s6, s4, s2
v_add_nc_u32_e32 v20, s5, v4
s_cmp_lt_i32 s6, 1
ds_store_b32 v19, v1 offset:4
ds_store_b32 v20, v1 offset:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_19
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, overlapLength@rel32@lo+4
s_addc_u32 s9, s9, overlapLength@rel32@hi+12
s_load_b512 s[16:31], s[0:1], 0x0
s_load_b32 s14, s[8:9], 0x0
s_clause 0x1
s_load_b32 s33, s[0:1], 0x48
s_load_b64 s[12:13], s[0:1], 0x40
s_add_i32 s7, s2, 1
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, queryLength@rel32@lo+4
s_addc_u32 s9, s9, queryLength@rel32@hi+12
s_mul_i32 s7, s7, s15
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, seqLibLength@rel32@lo+4
s_addc_u32 s11, s11, seqLibLength@rel32@hi+12
v_sub_nc_u32_e32 v2, s7, v0
s_load_b32 s7, s[8:9], 0x0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_add_nc_u32_e32 v21, s3, v4
v_cmp_eq_u32_e64 s0, s4, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add3_u32 v22, s5, 4, v4
s_load_b32 s34, s[10:11], 0x0
v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v30, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[16:17], 2, v[2:3]
v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, s2, s14
v_dual_mov_b32 v26, 0 :: v_dual_add_nc_u32 v3, s33, v0
s_mul_i32 s8, s8, s15
v_add_co_u32 v4, s1, s24, v16
v_sub_nc_u32_e32 v23, s8, v0
s_add_i32 s14, s8, s2
s_cmp_eq_u32 s33, 0
v_add_co_ci_u32_e64 v5, s1, s25, v17, s1
s_cselect_b32 s9, -1, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gapExtension@rel32@lo+4
s_addc_u32 s3, s3, gapExtension@rel32@hi+12
v_ashrrev_i32_e32 v0, 31, v23
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, gapOpen@rel32@lo+4
s_addc_u32 s5, s5, gapOpen@rel32@hi+12
s_load_b32 s10, s[2:3], 0x0
s_load_b32 s11, s[4:5], 0x0
v_add_co_u32 v24, s2, s16, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v25, s2, s17, v0, s2
v_add_co_u32 v6, s2, s12, v16
v_add_co_ci_u32_e64 v7, s2, s13, v17, s2
v_add_co_u32 v8, s2, s22, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s23, v17, s2
v_add_co_u32 v10, s2, s26, v16
v_add_co_ci_u32_e64 v11, s2, s27, v17, s2
v_add_co_u32 v12, s2, s30, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s2, s31, v17, s2
v_add_co_u32 v14, s2, s20, v16
v_add_co_ci_u32_e64 v15, s2, s21, v17, s2
v_add_co_u32 v16, s2, s28, v16
v_cmp_gt_i32_e64 s1, s7, v3
v_add_co_ci_u32_e64 v17, s2, s29, v17, s2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v33, 0
v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v27, 0
s_mov_b64 s[4:5], 0
s_min_i32 s12, s34, s14
.LBB0_2:
v_add_co_u32 v34, null, v23, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s8, v34
v_cmp_gt_i32_e64 s3, s12, v34
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_8
v_add_co_u32 v29, s2, v24, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v30, s2, s5, v25, s2
global_load_i8 v31, v[29:30], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[29:30], null, s7, v31, v[3:4]
v_ashrrev_i32_e32 v30, 31, v29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[29:30], 2, v[29:30]
v_add_co_u32 v29, s2, s18, v29
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v30, s2, s19, v30, s2
global_load_b32 v29, v[29:30], off
ds_load_b32 v32, v18
ds_load_b32 v30, v19 offset:4
ds_load_b32 v31, v20 offset:4
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_7
s_waitcnt lgkmcnt(0)
global_load_b32 v32, v[14:15], off
global_load_b32 v30, v[10:11], off
global_load_b32 v31, v[16:17], off
v_add_co_u32 v35, null, v2, s4
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v35
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v0, -1, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[35:36], 2, v[0:1]
v_add_co_u32 v37, s2, s20, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v38, s2, s21, v36, s2
v_add_co_u32 v35, s2, s28, v35
v_add_co_ci_u32_e64 v36, s2, s29, v36, s2
global_load_b32 v33, v[37:38], off
global_load_b32 v0, v[35:36], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s15
s_cmp_eq_u32 s4, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s9, s2
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v0, v0, v34, s2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_18
v_subrev_nc_u32_e32 v35, s10, v30
v_subrev_nc_u32_e32 v36, s11, v32
v_subrev_nc_u32_e32 v28, s10, v28
v_subrev_nc_u32_e32 v27, s11, v27
v_add_nc_u32_e32 v37, v29, v33
s_mov_b32 s3, exec_lo
v_max_i32_e32 v33, v35, v36
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v28, v28, v27
v_max3_i32 v35, v33, v28, v37
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v27, 0, v35
v_cmpx_lt_i32_e32 0, v35
s_xor_b32 s3, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, v27, v28
v_cndmask_b32_e64 v0, v0, v26, s2
v_cmp_eq_u32_e64 s2, v27, v33
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v26, v0, v31, s2
s_and_not1_saveexec_b32 s2, s3
v_add_nc_u32_e32 v26, 1, v34
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[4:5], off
s_mov_b32 s3, exec_lo
ds_store_b32 v21, v33 offset:4
ds_store_b32 v18, v27 offset:4
ds_store_b32 v22, v26 offset:4
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v27, v0
s_cbranch_execz .LBB0_15
global_store_b32 v[4:5], v27, off
global_store_b32 v[6:7], v26, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_17
global_store_b32 v[8:9], v27, off
global_store_b32 v[10:11], v33, off
global_store_b32 v[12:13], v26, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
v_dual_mov_b32 v0, v31 :: v_dual_mov_b32 v33, v32
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s13
v_add_co_u32 v4, s2, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_add_co_u32 v6, s2, v6, 4
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
v_add_co_u32 v8, s2, v8, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
v_add_co_u32 v10, s2, v10, 4
v_add_co_ci_u32_e64 v11, s2, 0, v11, s2
v_add_co_u32 v12, s2, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s2, 0, v13, s2
v_add_co_u32 v14, s2, v14, 4
v_add_co_ci_u32_e64 v15, s2, 0, v15, s2
v_add_co_u32 v16, s2, v16, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v17, s2, 0, v17, s2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_19:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 76
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 35
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end0-_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected partSeqSize
.type partSeqSize,@object
.section .bss,"aw",@nobits
.globl partSeqSize
.p2align 2, 0x0
partSeqSize:
.long 0
.size partSeqSize, 4
.protected partsNumber
.type partsNumber,@object
.globl partsNumber
.p2align 2, 0x0
partsNumber:
.long 0
.size partsNumber, 4
.protected overlapLength
.type overlapLength,@object
.globl overlapLength
.p2align 2, 0x0
overlapLength:
.long 0
.size overlapLength, 4
.protected seqLibLength
.type seqLibLength,@object
.globl seqLibLength
.p2align 2, 0x0
seqLibLength:
.long 0
.size seqLibLength, 4
.protected queryLength
.type queryLength,@object
.globl queryLength
.p2align 2, 0x0
queryLength:
.long 0
.size queryLength, 4
.protected gapOpen
.type gapOpen,@object
.globl gapOpen
.p2align 2, 0x0
gapOpen:
.long 0
.size gapOpen, 4
.protected gapExtension
.type gapExtension,@object
.globl gapExtension
.p2align 2, 0x0
gapExtension:
.long 0
.size gapExtension, 4
.protected maxScore
.type maxScore,@object
.globl maxScore
.p2align 2, 0x0
maxScore:
.long 0
.size maxScore, 4
.protected queryPartLength
.type queryPartLength,@object
.globl queryPartLength
.p2align 2, 0x0
queryPartLength:
.long 0
.size queryPartLength, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym partSeqSize
.addrsig_sym overlapLength
.addrsig_sym seqLibLength
.addrsig_sym queryLength
.addrsig_sym gapOpen
.addrsig_sym gapExtension
.addrsig_sym queryPartLength
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 76
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 37
.sgpr_spill_count: 0
.symbol: _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
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