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Attacking_SCADA_systems_A_practical_perspective.pdf
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As Supervisory Control and Data Acquisition (SCADA) and Industrial and Automation Control System (IACS) architectures became more open and interconnected, some of their remotely controlled processes also became more exposed to cyber threats. Aspects such as the use of mature technologies and legacy equipment or even the unforeseen consequences of bridging IACS with external networks have contributed to this situation. This situation pr ompted the involvement of governmental, industrial and research organizations, as well as standardization entities, in order to create and promote a series of recommendations and standards for IACS cyber-security. Despite those efforts, which are mostly focused on prevention and mitigation, existing literature still lacks attack descriptions that can be reused to reproduce and further research specific use cases and scenarios of security incidents, useful for improving and developing new security detect ion strategies. In this paper, we describe the implementation of a set of attacks targeting a SCADA hybrid testbed that reproduces an electrical grid for energy distribution (medium and high voltage). This environment makes use of real SCADA equipment to faithfully reproduce a real operational deployment, providing a better insight into less evident SCADA- and device- specificities.
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Attacking SCADA systems: a practical perspective Lu s Rosa1, Tiago Cruz1, Paulo Sim es1, Edmundo Monteiro1, Leonid Lev2 1CISUC-DEI, University of Coimbra, Portugal 2IEC Israel Electric Corportation, Israel {lmrosa, tjcruz, psimoes, edmundo}@dei.uc.pt, [email protected] Keywords Industrial Control Systems, SCADA, Security I. INTRODUCTION Supervisory Control and Data Acquisition (SCADA) systems are used to manage and automate processes in critical infrastructures such as electricity grids or water distribution facilities. According to the ISA definition [1], SCADA-based Industrial and Automation Control Systems (IACS) are structured into five distinct levels: level 0, reserved for the sensors and actuators; level 1, that contains devices such as Programmable Logic Controllers (PLC s) and Remote Terminal Units (RTU s); level 2, composed of supervisory control equipment's such as the Human-Machine Interface (HMI); level 3: for the Manufacturing Execution Systems (MES), such as the systems hosting production planning software; and level 4 for the remaining business related systems. The interconnection of level 0 and level 1 devices (e.g. PLC s and RTU s) and the interconnection of level 1 devices with level 2 devices (e.g. HMI s) are probably the most vulnerable points of IACS infrastructures. They were traditionally isolated and based on proprietary protocols and technologies without in trinsic security capabilities, relying on obscurity and air-gapping principles for such purpose. Nevertheless, with the progressive adoption of Ethernet- and TCP/IP-based networks, standardized SCADA protocols and VPN-based remote access (t o reduce maintenance costs), these networks are more connected than ever to the remaining infrastructure the corporate ne twork and even the Internet either by sharing physical network and computing resources or via (not foolproof) interconnection firewalls, routers or gateways. This paradigm change drastically increases the risks, due to the increased system complexity, the introduction of new attack vectors and the amplified exposure of existing security vulnerabilities. SCADA systems are intrinsically different from traditional ICT systems [2]. Automated real time physical processes do not need high throughput but demand continuous availability with guaranteed low delay and low jitter. More, their primary focus is on availability and service continuity opposed to classic ICT systems, where information confidentiality and integrity come first [3]. SCADA systems also have much longer lifetime cycles, due to their high upgrade costs easily reaching obsolescence by ICT standards. Even simple security patches take much longer to deploy, due to the need for previous testing and certification Recognizing those specificities and risks, as well as the tremendous impact they can ha ve on SCADA-based critical infrastructures such as energy gr ids, water distribution systems, transportation systems or factory plants, there is currently a strong investment on research towards enhancing the security of (both legacy and more recent) SCADA systems. There is an extensive literature researching various approaches for introducing IACS-specific intrusion detection mechanisms, as well as for improving the intrinsic security of SCADA systems. However, due to logistic constraints and the difficulty of using real-world production systems for research purposes, not many works are based on wider testbed scenarios reproducing real infrastructures, instead using very simplified test benches or general-purpose datasets. Among these, the large majority is focused on the defensive perspective of the targeted infrastructure, instead of th e attacker s point of view. While this is understandable considering how difficult it is to build larger, more realistic testbeds and the fact that researchers aim is to improve the SCADA systems cyber- security awareness and capabilities we believe it is also important to grasp the attacker s perspective, including the challenges he faces to implement a successful attack. In this paper, we provide a practical description of somehow representative cybe r-attacks (network based enumeration, communication hijacking and service disruption) targeting SCADA systems within a testbed that represents an 978-3-901882-89-0 @2017 IFIP 741 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply. electricity grid (regional network of medium and high voltage distribution). This testbed consists of a hybrid environment that includes real networking and SCADA assets (e.g. PLCs, HMIs, process control servers) controlling an emulated power grid (so we can assess the possible impact of these attacks on the physical world). We explain those attacks and discuss some of the challenges faced by an a ttacker to implement them. This work was performed in the scope of the CockpitCI [4] and ATENA [5] research projects, which aim at providing a holistic approach to security, safety and resilience of energy distribution grids, including the detection and prevention of cyber-attacks and the analysis of the mutual interdependency between their ICT assets (communications network, servers, SCADA control applications, PLC s and RTU s) and the energy side (e.g. transmission lines, substations, power transformers and generators, quality of energy service). Detection of cyber-attacks and situational awareness is a key part of these projects, and as such we built a specialized detection layer that has been extensively described and evaluated in previous works (e.g. [6-7]). This paper complements them by focusing not so much on the detection and mitigation solutions, but rather on the process of preparing and executing the attacks used for validation purposes. For sake of readability and represen tativeness, we decided to focus on simple, classic attacks, inst ead of more complex actions. The rest of the paper is organized as follows. Next section, we discuss related work. Section III introduces the testbed environment we used. The im plemented cyber-attacks are discussed in Section IV, and Section V concludes the paper. II. R ELATED WORK As already mentioned, existing research literature discusses different types of cyber-attack s against SCADA systems, such as Denial of Service (DoS) attacks [8-10], Man-in-the-Middle (MitM) attacks [11-12] or malware-based attacks [13]. Nevertheless, those discussions are usually focused on the defense mechanisms (and not on the attacks), based on small and/or simulated scenarios or lack detail on the practical implementation of the attack. Post-incident research on real -world attacks are valuable sources. Rolf Langer s report on the well-known Stuxnet malware [14] targeting Iran Nu clear facilities is a good example of such sources. Other high-profile well covered include the Duqu malware [15] or the 2015 Black Energy attack allegedly responsible for power outages in the Ukrainian Power Grid [16]. These sources have the advantage of being based on real, successful attacks but are usua lly limited to the analysis of complex high-profile incidents often supported by nation-state resources instead of simpler but representative attack profiles. III. T ARGET ENVIRONMENT A. HEDVa Testbed With the purpose of supporting the demonstration and validation of the CockpitCI framework, a testbed reproducing a regional-scale energy distribution network was built by Israel Electric Corporation (IEC). From ICT and SCADA perspectives this testbed is composed of real assets, including IT network, control and field level components, servers and services that typically integrate such a system. Within this scenario, an electrical distribution grid topology was entirely emulated using specialized soft ware developed at IEC, given the practical impossibility of us ing a real, large-scale energy distribution infrastructure (composed of many substations and hundreds of kilometers of power lines). This approach results in a hybrid testbed, where all ICT and SCADA components are real and believe to be monitoring and controlling a real energy grid. This is achieved by using an agent-based grid simulation model that uses real PLC equipment to emulate elements such as feeders or circuit breakers. The interface between th e real and emulated domains of the grid scenario includes all the monitoring data and controls that would exist in a real operational environment. Figure 1 provides an overview of this testbed (designated as HEDVa: Hybrid Environment for Design and Validation), of which only a subset will be relevant to the scope of this paper. By using such an environment, it became possible to research more complex interdependencies between different components (e.g. network, SCADA devices) and different domains (e.g. impact of ICT faults on the quality of energy on the different points of the grid). Furthermore, having a real deployment of ICT and SCADA systems allowed more realistic assessments and the collection of more extensive and realistic validation data. Figure 1: Overview of the HEDVa Testbed [6] B. The Modbus Protocol Among the wide range of different SCADA protocols available, the HEDVa Testbed uses Modbus over TCP/IP [17- 18]. Modbus is a protocol used to query field data using a polling client/server approach. Communication is based on query/response transactions identified by a transaction ID field and distinguished by a function code field. According to the Modbus data model, different types of tables are mapped into the PLC memory (such as discrete inputs, coils or holding registers). These values are queried via their respective function code and memory address (see Figure 2). There is no built-in mechanism (or fields) for authentication, authorization or encryption. Hence, without proper security enforcement in the remaining network stack, it 2017 IFIP/IEEE International Symposium on Integrated Network Management (IM2017): Experience Session - Full Paper 742 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply. becomes possible to dissect the Modbus messages payload (i.e. critical information from a physical process). Figure 2: Example of the interaction between two Modbus devices Forging communication or field data is also possible by simply crafting a valid value fo r the transaction ID field (see Figure 3), as this value is frequently predictable (due to lack of randomness in poor Modbus implementations) or even blindly discarded by some Modbus implementations. Moreover, Modbus/TCP runs on the top of non-encrypted TCP sessions. Figure 3: Modbus Frame and header format Even considering the real-time nature of the underlying processes, the polling based mechanism provided by the Modbus protocol is not effec tively real-time. The intervals between each request directly impact the delay time between a change in the physical process and the time the change is observed by the HMI operator. This results in a small but viable time window for hijacking communications before the Operator and/or the HMI appl ication notice any changes. Despite all these security vulnerabilities of Modbus apparently making the attacker s work too easy, Modbus holds a significant market share (over 20%, considering all its variations [19]) and many of the other protocols are not much different. This means the testbed represents of a large subset of the systems currently in operation. Several open source components can be used to build Modbus hacking tools, such as the Nmap s modbus-discover script [20] or Modscan [21] that allows to map and enumerate PLCs using Modbus over TCP within a network by exploring their replies. Another example is a python library extended from Scapy (a widely-used p acket manipulation framework easy to extend and integrate with other applications) that contains Modbus specific functions to easily craft Modbus frames [22]. Next section will discuss with the execution of a series of attacks, which also served fo r validating the proposed DIDS. IV. ATTACK STAGING AND EXECUTION All the attack scenarios assumed the attacker had access to the process control network (e.g. as result of a compromised host this step, which corresponds to the exploitation of the initial attack was intentionally omitted). For practical demonstrations, a dedicated host was deployed on the HEDVa, to serve as a base for the attacker, which could be easily relocated on the infrastructure, since it was hosted on a virtual machine. A similar attack strategy could be implemented (with the proper adjustments) to tr igger an attack (for instance, forging or sending Modbus packets) directly from a compromised HMI or other component. A three-stage attack strategy was devised, pursuing the following goals: monitoring the process values (to gain knowledge about the nature and characteristics of the controlled process), change them without being noticed in the SCADA HMI consoles and finally, induce service disruption on the energy grid. These should cover a large subset of a cyber-attack targeting a SCADA system. A by no means exhaustive list of the implemen ted attacks includes classical and Modbus specific scans, different variants of Denial of service attacks based on network floods, and a SCADA specific MitM specifically cu stomized for this process environment. Next, we describe some of those attacks. A. The HEDVa use case scenario for attack implementation For the sake of readability, we ll describe the attacks using a subset of the HEDVa testbed, configured to emulate an electricity distribution grid composed by two energy feeders and several circuit breakers, controlled by real Modbus PLCs (see Figure 4). Several HEDVa assets, including services, equipment (such as network switches and PLCs), servers (both physical and virtualized) and networks are also part of this use case. The PLCs and the remaining elements of the SCADA infrastructure in charge of th e emulated grid are connected using an Ethernet LAN infrastructure (using VLAN segmentation for domain separation). Figure 4: Representation of the electrical grid use case scenario The scenario deployed on the HEDVa (see Figure 5) includes two Human Machin e Interface (HMI) hosts, controlling and supervising the PLCs, an OPC server, a dedicated database for past even ts and offline analysis, and a deployment of the CockpitCI DIDS (not depicted). However, the DIDS security detection components didn t play any active role they were used to observe and document the attacks, without interfering with the attacker s actions. This scenario not only offered the means to validate the CockpitCI DIDS, but it also offered the opportunity to implement and analyze a series of security strategies. For the TCP Header MBAP Header Function Code IP Header DataTransactionID ProtocolID UnitID Length Modbus PL Cs T wo en er g y f eed er sCircuit break ersAll me asure Vo ltage and curre nt 2017 IFIP/IEEE International Symposium on Integrated Network Management (IM2017): Experience Session - Full Paper 743 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply. latter purpose, and complementar y to the classic penetration testing and auditing procedures, a series of team drills were executed to obtain relevant data on the most effective tactical defensive and offensive strategies. Switch HMI2 SCADA / OPC Server HMI1 Switch Security Gateway / Router Switch NIDS Attacker Switch Figure 5: Reference scenario for the use cases Besides these efforts, the acquisition of relevant datasets for development, training and offline evaluation of anomaly detection methods was also another important role of the HEDVa scenario. For capturing all the network interactions for further analysis, a centralized network point of capture was configured. This was achieved using port monitoring / mirroring in the switch layer, as opposed to a distributed packet acquisition solution to avoid all the issues with duplicated packets or timestamp synchronization. B. Network Reconnaissance Network scouting is one of the first steps of an attack, meant to gather information about all the components of the target environment, to discover and identify topologies, hosts and services. For instance, traditional network components such as HMIs are identified by IP and MAC addresses, operating system versions and a set of services (using techniques such as FIN scans, see Figure 6) in such cases, the specific service footprint, together with TCP fingerprinting data is useful to identify specific components or software implementations. Figure 6: First step of a Network/Modbus scan In addition to that, each PL C is also identified and addressed by the unitID field, part of the Modbus frame (see Figure 7). For simple scenar ios where one IP address correspond to one PLC, the unitID can be set to a fixed known value (typically 1 ) or may be ignored by the Modbus implementation. Nevertheless, a Modbus gateway, using only one IP address, may hide several PLCs with different unitIDs. As part of an attack, a Modbus request with a wrong unitID, blindly used by an attacker, may be discarded or easily flagged with proper security mechanisms. Thus, and for Modbus over TCP, it is critical to perform a Modbus enumeration on top of the traditional TCP/IP scans. Both types of scans are relevant as they can be used not only to discover devices and types of services but also to perform fingerprinting and discover PLCs behind gateways. Figure 7: Modbus Device Scan / Enumeration Network scouting provides a perspective on the target infrastructure from the network point-of-view, corresponding to the layers 2-4 of the OSI model. Despite its usefulness as a tool to identify and enumerate devices and services it doesn t provide process-level information, which is required to implement sophisticated attacks. The next subsection will present the technique that was us ed to obtain such information. C. Using ARP poisoning to implement a MitM attack The concept of a ARP poisoning MitM attack usually comprises two parts: an ARP spoofing and a communication hijacking step. In the first stag e, the idea is to spoof the ARP cache of both target devices, belonging to the same link, by sending malicious and unsolicited ARP is-at messages to the network (see Figure 8) to force both devices to send the packets through the attacker MAC address. This requires th e attacker to know at least the IP and MAC addresses of the victims and the link they are connected to. As soon as the ARP cache of each victim is spoofed, the traffic gets redirected through the attacker. Figure 8: ARP poisoning attack In the second attack stage (see Figure 9), when the traffic is already being redirected, the attacker can choose to read the messages and forward them, or actively change them. Depending on the type of TCP connection, its payload and the actual data the attacker is interested in, the process may get Control System Network22 HMI1 Attacker Attacker PLC SwitchFIN 11FINPort StatePort State Do it slo w lyAnd fo r all the ne two rkS tage 1: Ho sts and se rvice s Control System Network1 12 2 (spoofed) ARP Cache Table: ip_plc mac_atacker(spoofed) ARP Cache Table: ip_hmi mac_atacker HMI1 Attacker Attacker PLC SwitchARP Spoofed ReplyARP Spoofed ReplySt a g e 1 : ARP p o iso ning 2017 IFIP/IEEE International Symposium on Integrated Network Management (IM2017): Experience Session - Full Paper 744 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply. complex. For persistent TCP connections, as opposed to one TCP connection per data request (Modbus can be implemented using the two communication models), the attacker will need to keep the TCP fields consistent (e.g. sequence and acknowledgement numbers) and the connection open (e.g. TCP keep-alive packets). Figure 9: TCP hijacking Moreover, in the case of Modbus, the requested values typically change in real-time and some of them are directly changed by the SCADA operator (e.g. Modbus writes), this means the attacker n eeds to somehow keep track not only of all the interactions but also comput e and reproduce the effects in the physical process (e.g close of a circuit breaker in electric path may change the physical values such as current and voltage in other parts of the circuit). The complexity of this increases as the number of elements, relations and interdependencies increases. D. Attack strategy and execution The objective of the attacker can be su mmarized as such: hijack the entire grid in such a way that the main HMI (HMI1) has no clue about the ongoing attack. Moreover, the attack goal should be accomplished by the a ttacker while going unnoticed. One of the first challenges faced by the attacker has to do with understanding the network topology and communication flows. For instance, the HMI1 host (one of the victims) is not part of the same network link as the PLCs, requiring the attacker to implement an ARP spoof targeting the gateway interface of the network link where the attacker is placed instead of the HMI1 (see Figure 10). Figure 10: ARP poisoning for the implemented attack Besides HMI1, there is a second HMI (HMI2) developed to observe and validate the attack, which was not spoofed. HMI1 uses TCP persistent connections to control several PLCs (11, to be more precise). Thus, the a ttacker needs to know how to handle or forward any spoofed packets in real-time, while avoiding TCP connection drops, to prevent any suspicious behaviour on the HMI console that could unveil his presence (see Figure 11). Packet drops auto matically raise an alarm and change the view of the HMI for the corresponding PLC after a couple of seconds, indicating a potential issue. A TCP connection lost or a lack of a Modbus reply from the PLC is also visible from the HMI console. The second HMI did not use persistent connections. Later, during the trials, it was discovered that each PLC only supported a maximum of two simultaneous TCP connections. This may limit the way TCP connections are handled and re directed by the attacker. Figure 11: TCP hijacking for the implemented attack At first, the main concern was to place the attacker in the middle of the communication between the HMI1 and the PLCs to capture and analyze relevant process information. This allowed the attacker to gather more detailed information about the communications and the controlled process, learning how each Modbus register value affected the others (e.g. circuit breakers, current and voltage ranges). Once the attacker was able to figure out the basic behavior of the controlled process, it was time to step up the challenge and hijack the entire process. This required forging the entire grid state in such a way that any HMI interaction may produce a realistic state update, while decoupling HMI-PLC interactions. For this purpose, the attacker needs to reply to the Modbus requests in real-time. Moreover, TCP session hijacking requires the attacker to maintain the integrity of the TCP connection (such as TCP sequence numbers) to avoid a connection drop. Then, the following task is cr afting the Modbus frames and recreate a fake view of the entir e scenario in real-time. This task was implemented using a in-house application on the top of Scapy framework [22] since common open-source tools normally used for this sort of attacks are not SCADA/Modbus aware and did not fulfill the project needs, either by not offering an integrated solution for all the steps or by lacking flexibility to adjust settings to the HEDVa scenario. After the ARP spoofing, the attacker first starts by capturing the current state of th e grid. This is achieved by dumping and decoding one complete interaction cycle (i.e. the set of Modbus request-reply transactions) between the HMI1 and all PLCs. This represents the initial state of the simulated view and it allows to restore the previously grid state after stopping the attack (in case the attacker wants to do so). The attacker is also responsible to perform deep inspection of each packet and selectively intercept all the TCP connections from 2017 IFIP/IEEE International Symposium on Integrated Network Management (IM2017): Experience Session - Full Paper 745 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply. the HMI1 to the PLCs while forwarding the others (i.e. the communications between HMIs and PLCs). When requests from the HMI1 are received, the attacker will compute the responses based on its own replica of the model (obtained during the process analysis stage). This effectively decouples the HMI1 from the PLCs, creating two distinct communication flows: one between the HMI1 and the attacker and the other one betw een the attacker and each PLC. This allows not only to hijack the data exchanged between them but also trigger any kind of service disruption against the PLCs compromising the physical process behind them. Since the true state of the PLCs is hidden from HMI1, the attacker is free to do whatever he wants without the knowledge of the legit SCADA operator. Moreover, all the changes performed by the SCADA operator such as opening or closing a breaker are properly intercepted and handled by the attacker. Finally, whenever the attacker decides to stop the attack, he only needs to perform the inverse of the first steps, dumping the values of the simulated HMI1 view to the PLCs, so that there is no difference between the HMI1 and PLC states, also restoring the ARP caches by sending additional unsolicited ARP replies with the correct a ssociations between MAC and IP addresses. V. C ONCLUSIONS AND FUTURE WORK The attack procedures here described illustrate a complete intrusion procedure applied to a specific IACS use case. The reconnaissance step is like other types of network scans, the main difference is the Modbus unitID field, depending on the components and how they are deployed. The service disruption is also straight-forward since as soon as the attacker has access to the network, it is simple to redirect Modbus traffic (causing the disruption) or even flood the PLCs, as they typically have moderate / small amount of resources available. The communication hijacki ng attack that was implemented has proven to be considerably more complex and tightly coupled to the field processes in the SCADA environment than, for instance, a HTTP hijacking attempt. This is due to several reasons, such as the need to re produce part the physical process behavior without getting detected. Despite new infection paths, types of attacks or strategies to get unnoticed, further efforts and research should focus on improving the process of recreate and maintain the fake views used by the attacker during the communication hijacking and for specific known domains like energy grids. This work is part of a wide r effort where multiple cyber detection technologies are being researched to understand how these types of cyber security events could be adequately handled. Moreover, this effort also intends to alleviate the lack of open available datasets (such as raw traces from SCADA IACS) allowing to further expl ore and research new security approaches and detection mechanisms. A CKNOWLEDGMENT This work was partially funded by the CockpitCI European Project (FP7-SEC-2011-1 Project 285647) and by the ATENA European Project (H2020-DS-2015-1 Project 700581). R EFERENCES [1] ISA, ISA-62443-1-1 security for industrial automation and control systems part 1: Terminology, c oncepts, and models draft 5, International Society for Automation, 2015. [2] NIST, 800-82, Guide to Industrial Control Systems (ICS) Security, Rev. 2, National Institute of Standards and Technology, 2015. [3] ISA-99.00.01, Security for Industrial Automation and Control Systems - Part 1: Terminology, Concepts, and Models, American National Standard. 2007. [4] FP7 CockpitCI Research Proj ect, https://www.cockpitci.eu/ [5] H2020 ATENA Research Project, https://www.atena-h2020.eu/ [6] T. Cruz, L. Rosa, J. Proenca, L. Maglaras, M. Aubigny, L. Lev, J. Jiang, P. Simoes, A cyber security dete ction framework for supervisory control and data acquisition systems, IEEE Transactions on Industrial Informatics, Preprint. doi:10.1109/TII.2016.2599841 [7] T. Cruz, J. Proen a, P. Sim es , M. Aubigny, M. Ouedraogo, A. Graziano, L. Maglaras, A Distributed IDS for Industrial Control Systems, International Journal of Cyber Warfare and Terrorism, 4(2), 1- 22, April-June 2014. DOI: 10.4018/ijcwt.2014040101 [8] C. Queiroz, A. Mahmood, J. Hu, Z. Tari, and X. Yu, Building a scada security testbed, in Network and System Security, 2009. NSS 09. Third International Conference on, pp. 357 364, IEEE, 2009. [9] M. Mallouhi, Y. Al-Nashif, D. Cox, T. Chadaga, and S. Hariri, A testbed for analyzing security of SCADA control systems (tasscs), in Innovative Smart Grid Technologies, 2011 IEEE PES, pp. 1 7, 2011. [10] S. Bhatia, N. Kush, C. Djamaludin, J. Akande, and E. Foo, Practical modbus flooding attack and detecti on, in Proceedings of the 12th Australasian Information Security Conference-Volume 149, pp. 57 65, Australian Computer Society, Inc., 2014. [11] B. Chen, N. Pattanaik, A. Goulart, K. L. Butler- Purry, and D. Kundur, Implementing attacks for modbus/TCP protocol in a real-time cyber physical system test bed, in Co mm. Quality and Reliability, 2015 IEEE International Workshop Technical Committee on, pp. 1 6, 2015 [12] E. E. Miciolino, G. Bernieri, F. Pascucci, and R. Setola, Communications network analysis in a SCADA system testbed under cyber-attacks, in Telecommunications Forum (TELFOR) 2015 23rd, pp. 341 344, 2015. [13] D. Chen, Y. Peng, and H. Wang, Dev elopment of a testbed for process control system cybersecurity research, in 3rd International Conference on Electric and Electronics, Atlantis Press, 2013. [14] R. Langner, To kill a centrifuge a tec hnical analysis of what stuxnet s creators tried to achieve, The Langner Group, November 2003. [15] Laboratory of Cryptography and Syst em Security (CrySyS), Duqu: A Stuxnet-like malware found in th e wild, http://www.crysys.hu/ publications/files/bencsathPBF11duqu.pdf. [16] Blackenergy & quedagh: the convergence of crimeware and apt attacks. ,https://www.fsecure.c om/documents/996508/1030745/blacken ergy_whitepaper.pdf. [17] Modbus Organization, Modbus protocol specification, [18] Modbus Organization, Modbus messaging on TCP/IP implementation guide [19] IM S Research, The World Market for Industrial Ethernet 2013 Edition . [20] Nmap scripting engine-modbus-discove r nse script. , https://nmap.org/ nsedoc/scripts/modbus-discover.html. [21] Mark Bristow, Modscan, https://code.google.com/archive/p/modscan/ [22] A. Gervais, Modbus/TCP library for scapy 0.1. 2017 IFIP/IEEE International Symposium on Integrated Network Management (IM2017): Experience Session - Full Paper 746 Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:40:15 UTC from IEEE Xplore. Restrictions apply.
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PLC_Code-Level_Vulnerabilities.pdf
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C ode vulnerabilities in the ladder logic of PLCs (Programmable Logic Controllers) have not been sufficiently addressed in the literature. Most of the research related to PLC threats or attacks focuses on the hardware portion of ICS (Industrial Control Systems) or SCADA (Supervisory Control and Data Acquisition) systems such as: industrial components, peripheral devices, or networks. It does not adequately discuss PLC code-level vulnerabilities and attacks. This paper provides an overview of some critical vulnerabilities within the PLC ladder logic code or program and recommends corresponding steps or methods to keep PLCs safer and more secure. The paper focuses on ladder logic code vulnerabilit ies and weak points that might be exploited by malicious attacks. Those weak points could be a result of intentional malicious pieces of code embedded within the ladder logic code or inadvertent ones such as bad code practices or human errors.
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PLC Code-Level Vulnerabilities Abraham Serhane1, 2, Mohamad Raad1 1International University of Beirut 146404 Mazraa, Beirut, Lebanon Email: [email protected] Raad Raad2, Willy Susilo2 2University of Wollongong, Northfields Ave, Wollongong NSW 2522, Australia Index Terms DoS: Denial of Service, HMI: Human Machine Interface, ICS: Industrial Control Systems, JSR: Jump to Subroutine instruction PLC: Programmable Logic Controller, OTE: Output Energize instruction, SBR: Subroutine instruction, SCADA: Supervisory Control and Data Acquisition. I. INTRODUCTION PLCs are widely used in automated, industrial facilities and factories including national critical infrastructure: Power gri ds, water treatment, nuclear reactors, assembly lines, etc. PLCs a re dedicated and reliable real-time devices. Despite their reliability, accuracy, flexibility, and industrial robustness, PLCs are becoming a big concern after the Stuxnet malicious attack i n June 2010. Stuxnet malware highlighted the vulnerability of PLCs. The malware targeted PLCs and was able to stealthily and maliciously spy, attack, and compromise PLC related devices and codes [1], [2], [3] causing serious damages. Since Stuxnet s attack, PLCs have attracted the attention of the hackers with different malware attacks such as: BlackEnergy, Flame, and Wiper [4], [5], [6]. In 2011, the number of SCADA attacks increased by 300%. The average number of ICS flaws increased by 5% every year after [7], see Fig. 1. A study conducted by Kaspersky Lab shows that most of these PLC- related attacks are either critical ones, 49%, or of medium risk, 42%, see Fig. 2. The report clearly indicates that only 85% of these known published vulnerabilities are fixed but the rest are either partially fixed, can t be fixed, or not fixed at all [8]. According to Symantec, there were about 135 public vulnerabilities reported that are related to ICS/PLC-BS in 2015. While in 2014, only 35 ICS-related vulnerabilities were reported [9]. Much attention is usually directed towards external attacks li ke network intrusion, compromised SCADA devices and DoS (Denial of Service attacks), but little attention is given to t he ladder logic code vulnerability [10]. It has been assumed that ladder logic code is secure and safe as long as the network is healthy and protected from malware or intruders. But that is no t sufficient since the ladder logic itself has its own overlooked or unnoticed vulnerabilities which will be discussed in detail in this paper. Indeed, not many solutions exist to help secure PLCs such as certificateless cryptography [11] or intrusion detectio n through expected response times under normal operating conditions such as [12] and [13]. II. PLC OVERVIEW PLCs are a family of embedded devices. Besides its hardware architecture, PLC has it own OS system. Its software side is our concern because it is usually the one which is the most vulnerable to cyber-attacks. PLC software consists of the following: 1) PLC OS: PLCs provide the main control of ICS/SCADA systems. They are real-time systems. They are responsible of real-time interaction with all inputs (status or feedback of sensors, HMIs, other PLCs , and field devices, etc.) via industrial networks and transmit the proper outputs or commands after executing certain programs, ladder logic code, within the PLC in a very limited time. Unlike regular microcontrollers, PLCs consist of firmware (OS) which make them vulnerable to attacks and threats. PLCs generally contain a real-time operating system such as OS-9 or VxWorks [14]. If the OS is compromised by a hacker, the whole system can be completely taken over opening the door to varieties of malicious attacks and threats . 2) Ladder Logic Code: Ladder logic is the programming language that the code - logic - of the PLC programs is written in using special compilers or software. RSLogix5000, for instance, is a software used to write, edit, and compile ladder logic codes. The software uses IEC 61131-3 languages for the ,QWHUQDWLRQDO&RQIHUHQFHRQ&RPSXWHUDQG$SSOLFDWLRQV ,&& $ ,((( Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:38:14 UTC from IEEE Xplore. Restrictions apply. logic, where IEC 61131-3 is an open international standard [15] for PLC programming Language. Every OEM vendor has its own PLC features and framework. While some are very advanced and allow several ways in writing logic, some others are very primitive and straightforward. However, Most of the PLCs ladder logic programs can be written as: Ladder Logic Diagrams (graphical); see Fig. 3(a). FBD: Functional Block Diagram (graphical); see Fig. 3(b). Structured Text (textual: XIO Examine if Open, XIC Examine if Closed, etc.) The most popular of the above code structure is ladder logic. I t is the program that controls, processes, and monitors all the parameters, inputs, outputs, and other decisions needed to run any automated or manually controlled devices or systems. Therefore, the code must be highly reliable with real-time data availability and high integrity to make prompt and precise logical calls and decisions. unlike some other high-level languages, ladder logic code is accessible and editable at any time even when the PLC is running without stopping or restarting the whole PLC ladder logic program. Therefore, any code vulnerabilities could lead to major catastrophic problems; even though the external environment is secure. III. LADDER LOGIC CODE VULNERABILITIES Not well structured and designed l adder logic code increases th e risks of vulnerabilities and security holes; even though the programmer is conforming to the company s standards and recommendations. And that could be more aggravated if the logic is not written by professional , experienced people; which is mostly the case. Standards are very subjective and are mainl y company oriented. Such standards are mainly created and instituted to keep systems functioning, well optimized, and saf e, but less attention is given to security threats and vulnerabili ties. Such cases create a back door to hackers or could inherit the PLC programs insecure and dormant or unnoticed threats. The following are some main examples of bad coding scenarios that any programmer should avoid. Ladder logic code vulnerabilities are summarized as follows: Using d uplicated instructions: reusing certain operands Such as: OTE, counters, timers, and JSR. more than once in the ladder code leads to undesired result. Fig. 4 shows an example of a duplicated OTE operand - Y1. The duplication in this logic makes Y1 triggered during its unintended time. The reason is that Y1 is going to be turned ON in the first rung and right away turns OFF if X2 is enabled. So, it goes ON or OFF based on the scanning result of the rung it belongs to. An unintended fluctuating value of an operand would make it hard to debug or notice. Keep in mind that duplicating certain outputs w ould n ot be allow ed in s om e PLCs, but s om e others would allow it. Snooping: a ladder logic code that can be written to log certain critical parameter and values to be leaked stealthily for spying purposes without affecting the logic flow and purpose. That can be done by utilizing array instructions like FIFO and some other arrays -based ones; e.g. ADD ON user defined instructions. Such instructions can be added unnoticed to the code and does not raise any suspicious or unusual behavior. Fig. 1. SCADA Vulnerability Disclosures by Year [4]. Fig. 2. SCADA s and other components vulnerabilities [5]. (a) (b) Fig. 3. Ladder Logic Diagram (a) compared to FBD (b). ,QWHUQDWLRQDO&RQIHUHQFHRQ&RPSXWHUDQG$SSOLFDWLRQV ,&& $ ,((( Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:38:14 UTC from IEEE Xplore. Restrictions apply. Fig. 4. Duplicating OTE operand. Missing certain coils or outputs : occurs when a rung is missing a specific output coil (such as OTEs, latches or sets, unlatches, etc.) which other tag(s) depends on; see Fig. 5 . Missing coils increases the risk of vulnerability threats. It is a warning sign that someone could be deliberately tampering with logic to deviate certain critical values; risking the system to make wrong calls and decisions. Fig. 6 shows the proper way to handle OTE instructions where each rung has its proper pre-condition and output operands. Y11, an OTE instruction, depends on the value of the normally open instruction Y2. Not having Y2 instruction (deleted or replaced by non-useful false instruction) as a precondition to Y11, makes Y11 rung -condition- out False (Y11 always OFF). That would be hard to notice. Bypassing: either by manually forcing the values of certain operands while the ladder logic is online or by using empty branches, jumpers, as shown in Fig 7. DoS: the user can write online or upload a malicious piece of ladder logic to the PLC that might be activated or triggered at a certain time. That could slow down the PLC in a severe matter, totally halt it, or cause major faults . The operator can t access the ladder logic, edit it, or monitor values in real-time. The attack can be done through: - Coding a repetitive SBR calls via JSR instructions. - Coding infinite loop via jumpers. - Nest timers and jumpers. - Improperly inserting MCR - Master Control Reset - instructions that de-energized non- retentive instructions like OTE coils. - Coding certain ladder logic that might lead to fatal errors or major faults. Such faults might require restarting the PLC or re-uploading correct clean ladder logic which leads to data loss and temporarily shut down to the whole automated system associated with that PLC. The recovery could be time consuming and might cause damage to some meticulous industrial activities or devices; in addition to data loose of critical parameters or values. One of the solutions for such problems is to monitor jumpers and other looping routines using counters and timers. If the loops are going on more than expected warn the operator and halt certain suspicious routines. Using hard coded values: in certain situation using hard coded values or parameters endangers the process or its related program; see Fig. 8. Numeric values are easier to modify than those driven by continuous feedback. Modification can be on purpose, inadvertent, or by malicious attacks. For instance, a programmer by mistake might enter a wrong value in the database table where the values of the instructions are easily displayed and accessible; that could also happen by toggling the values of the instruction displayed in the rung. Fig. 9 shows a solution that can keep source B numeric value updated even if it is modified inadvertently by a toggle or by updating the values in the PLC database table. Fig. 5.The tag y2 is missing related input(s). Fig. 6. Outputs instructions are properly energized. Fig. 7. Using an empty branch as a jumper. Fig. 8. Numeric values are vulnerable. ,QWHUQDWLRQDO&RQIHUHQFHRQ&RPSXWHUDQG$SSOLFDWLRQV ,&& $ ,((( Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:38:14 UTC from IEEE Xplore. Restrictions apply. Fig. 9. Compare real-time numeric values not card coded ones. Racing: occurs when two codes or operands of logic are racing against each other leading to inconsistent results and can be used to create a threat that could damage devices. Misplaced operands within the same code or even one rung - such as the racing scenario in timers is a good example that often happens. Fig. 10 shows that having the done bit of the timer (tmr1), tmr1.DN, before the branch causes a racing problem if the timer s accumulator reaches the value of the Preset one s (assuming X1 is always ON). In other words, whenever the timer (tmr1) is done, it is reset again and the Valve01 is energized because the precondition, tmr1.DN, is false. There is always a chance the Valve01 will never get turned off or be de-energized. That would make it hard to locate the problem because the logic looks legitimate. The proper correction is shown in Fig. 11. Lack of thorough diagnostics and alarm messages : when there are no detailed and in-depth alarms, diagnostics, or preconditions the devices might be at great risk because the operator will only notice the damage after it occurs. Overall, the resultant is device damage or time delay in recovering, debugging, or maintaining. For i nstance, not setting an alarm message or warning for motor overload before enabling or while running it could damage the motor especially if the physical overload switch is compromised or it does not exist. The problem will be more aggravated if the compromised device is critical e.g. nuclear reactor and yet lacking critical alarms or warning. Another concern is when there are sufficient alarms and warning messages that can prompt the operator, but they got disabled either through another wrong or malicious piece of logic or by external user who manages to get through the code. A good practice is to add a ladder logic code that can simulate all faults scenarios and check their status alive before running production. Another good practice is to create a heart- beat pulse bit flashes every 50ms that is synchronized with the alarms program section. Compiler warning: overlooking certain PLC compiler warnings would be critical since they might be a real threat; e.g. a compiler warns about duplicate outputs, Fig. 12. Unused tags or operands: dormant malicious code or external attacks might take advanta ge of any unused tag because they are already predefined and using them will be stealth and not raise any flag. So many PLC programmers leave unused tags in the PLC database. Any malicious attack the proper time and circumstances to trigger signals that might activate malicious output to interrupt or manipulate data. That can be done by utilizing instructions (Timers, Jumpers, etc.) that can overload the PLC OS, slow it down, truncate critical data, or generate certain datatype faults and errors. Program Mode: keeping the PLC in Program Mode or Unlocked Mode , allows others to intentionally or inadvertently upload wrong or malicious ladder logic code; jeopardizing the whole automated system. The user can even wipe out the whole ladder logic or upload any suspicious one. Also, Keeping the PLC in Program Mode , makes the PLC vulnerable to any code manipulation with no need to delete or overwrite the whole program. It allows others to do online editing for ladder logic (add or delete pieces of code or data) while the ladder logic is running. That can be done by any user without being noticed since there will be no need to do a critical ladder logic code upload to the PLC; only critical uploads usually cause systems to stop and reset. The lack of authentication : before uploading new or modified ladder logic code to the PLC no authentication is conducted. Attackers can use this to upload malicious code, vulnerable code, or improper code or they can even compromise the PLC. To avoid that, a software such as comparison tools should be used to ensure the integrity of critical pieces of code by comparing them to the original program. Fig. 10. Racing condition. Fig. 11. Racing condition solved. ,QWHUQDWLRQDO&RQIHUHQFHRQ&RPSXWHUDQG$SSOLFDWLRQV ,&& $ ,((( Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:38:14 UTC from IEEE Xplore. Restrictions apply. Fig. 12. Compilers warning. IV. LADDER LOGIC - BACKDOORS Many companies and vendors assume that ladder logic is secure and not accessible by hackers and intruders because the PLC networks are usually air gapped. But that is not true for the following reasons: Random threats: the malicious attack could be done by a floating malware that is designed to affect certain PLC brands. It is deployed remotely, by USB, or locally by infected PC on the PLC network. Such attacks could be initialized on purpose or inadvertent. Isolating PLC networks completely from others is not realistic because there is always a need to connect a PC or HMI which could be infected - to a PLC where a programmer needs to monitor or edit ladder logic. Internal threats : could be because of upset employees, bad coding practice, infected logic written on infected PC, or intentional attacks; e.g. give remote access to hackers, open certain ports, or insert infected USB. External threats : external stealthy access to the PLC code to either keep a malicious code dormant and trigger it at a proper time or to be a "hit and run" scenario. Dormant pieces of logic could be used to steal sensitive information and parameters which could be used latter on to sabotage or damag e automated systems. V. CONCLUSION Vulnerabilities of PLCs are growing, leading to an increasing risk of threats and attacks. There are few works and scattered local efforts involved in improving PLC ladder logic code, but challenges still there. In this paper we have solely focused on the code level vulnerabilities of ladder logic that resides and runs on PLCs. The paper provides a summary and details of some major fundamental ladder logic code vulnerabilities and threats. Those vulnerabilities might be existing in any typical ladder logic: unnoticed or unknown never thought of. Ladder logic code vulnerabilities could be dormant threat s that can be triggered at any time risking the whole automated system that is associated with. Even though code vulnerabilities could occur because of bad coding practice , some might be unknown even to professional programmers. In addition, we have provided solutions for the vulnerabilities mentioned above. Following the solutions and recommendations provided would highly mitigate, reduce, or eliminate malicious attacks or threat. REFERENCES [1] Langner R. Stuxnet: Dissecting a cyberwarfare weapon. IEEE Security & Privacy . 2011; 9(3): 49-51. [2] Troy Nash, Backdoors and Holes in Network Perimeters A Case St udy for Improving Your Control System Security, Vol 1.1, August 20 05, Vulnerability and Risk Assessment Program, Lawrence Livermore National Laboratory, UCRL-MI- 215398 . [3] J. Weiss. Stuxnet: Cybersecurity Trojan Horse. InTech, 2010. [4] Alexander Gostev, The Flame: Questions and Answers , Securelis t Blog, Kaspersky,May 2012 https://www.securelist.com/en/blog/208193522/The_Flame_Question s_a nd_Answers [5] url: https://threatpost.com/blackenergy-malware-used-in-attacks -against- industrial -control-systems/109067/. (October 29, 2014). [Accessed 17/02/2018] [6] R. M. Lee, M. J. Assante, and T. Conway. Analysis of the Cyber Attack on the Ukrainian Power Grid. Technical report, E-ISAC, 2016. [7] Overload: Critical Lessons from 15 Years of ICS Vulnerabilities , URL: https://www2.fireeye.com/rs/848-DID-242/images/ics-vulnerabilit y- trend -report-final.pdf, August 2016. [8] Kaspersky Lab, Industrial Control Systems Vulnerabilities Stat istics, 2015.URL:https://kasperskycontenthub.com/securelist/files/2016/ 07/KL_ REPORT_ICS_Statistic_vulnerabilities.pdf [9] S. Corporation, Internet Security Threat Report | Appendices, VOLUME 21, APRIL 2016. [10] Valentine, S. and Farkas, C. Software Security: Application-Lev el Vulnerabilities in SCADA Systems. IRI 2011. [11] Z. Zhang, W. Susilo, R. Raad, Mobile ad-hoc network key managem ent with certificateless cryptography, Signal Processing and Commun ication Systems, ICSPCS 2008. 2nd International Conference on, 2008, IE EE. [12] S . Q a z i , R . R a a d , Y . M u , W . S u s i l o , S e c u r i n g D S R a g a i n s t w o r m h o le attacks in multirate ad hoc networks, Journal of Network and Co mputer Applications, Vol. 36, 2, pp 582 -592, 2013, Elsevier. [13] S. Qazi, R. Raad, Y. Mu, W. Susilo, Multirate DelPHI to secure multirate ad hoc networks against wormhole attacks, Journal of Informatio n Security and Applications, Volume 39, pp 31-40, Elsevier, 2018. [14] "PLC Security Risk: Controller Operating Systems - Tofino Indus trial Security Solution". www.tofinosecurity.com. [15] https://www.isa.org/standards-publications/isa-publications/int ech- magazine/2012/october/system-integration-iec-61131-3-industrial - control-programming-standard-advancements/ ,QWHUQDWLRQDO&RQIHUHQFHRQ&RPSXWHUDQG$SSOLFDWLRQV ,&& $ ,((( Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:38:14 UTC from IEEE Xplore. Restrictions apply.
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Applying_static_code_analysis_on_industrial_controller_code.pdf
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Static code analysis techniques are a well- established tool to improve the e ciency of software developers and for checking the correctness of safety-critical software com- ponents. However , their use is often limited to general purpose or mainstream programming languages. For these languages, static code analysis has found its way into many integrated development environments and is available to a large number of software developers. In other domains, e. g., for the programming languages used to develop many industrial control applications,tools supporting sophisticated static code analysis techniques arerarely used. This paper reports on the experience of the authors while adapting static code analysis to a software development environment for engineering the control software of industrialprocess automation systems. The applicability of static codeanalysis for industrial controller code is demonstrated by a casestudy using a real-world control system.
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Applying Static Code Analysis on Industrial Controller Code Stefan Stattelmann , Sebastian Biallas , Bastian Schlich , and Stefan Kowalewski ABB Corporate Research Germany, Ladenburg, Germany Email: [email protected] Embedded Software Laboratory, RWTH Aachen University, Aachen, Germany Email: [email protected] I. Introduction In industry, automation and control tasks are frequently operated using programmable logic controllers (PLCs). This paper describes the experience of the authors while adapting the Arcade.PLC1framework as described by Biallas et al. in [1] for use with the ABB Compact Control Builder control application development environment. The goal of this project was to apply static analysis techniques to programming languages of the IEC 61131-3 standard [2] used in ABB Compact Control Builder in order to improve the development process of control applications. Software development environments for IEC 61131-3 lan- guages often lack any support for static code analysis, except for error messages during compilation. There are some commercial tools available for checking syntactic properties of control applications or individual modules. However, these tools only check very basic properties (e. g., coding guidelines) [3] and are not integrated into the development environment. While the latter is often intended, e. g., to avoid recerti cation of safety-related software tools, the very basic nature of existing tools might also be rooted in a lack of awareness about the capabilities of formal methods in the automation domain. Improving this awareness was part of the motivation for the work described in the following. II. ABB Compact Control Builder and Arcade.PLC ABB Compact Control Builder is an ABB tool to develop control applications for AC 800M automation controllers. This family of control devices is used for the automation of complex industrial processes, e. g., in the chemical industry. While the 1Aachen Rigorous Code Analysis and Debugging Environment for PLCscore languages used in Compact Control Builder are a subset of the languages de ned in IEC 61131-3, there are certain extensions to the standard. This includes instantiation rules, e. g., singleton function blocks, and means to specify the order in which function blocks in an aggregated type are executed. One distinguishing factor of the AC 800M controller, and thus the respective Control Builder tools, is the use of native code execution. This means that all control programs are compiled from source code into binary machine code before deploying them to the controller. This includes all function block types and other modules provided as reusable libraries, except for certain rmware functions. The latter are part of the runtime environment of the controller. However, Compact Control Builder libraries are not distributed in compiled form, but as source code. To avoid modi cations and inappropriate use of library components by control engineers developing a control application, the source code les are encrypted. Depending on the level of protection, this encryption can include only the internal code or the complete interface of the components. In both cases, Compact Control Builder decrypts the libraries to perform the compilation from source code into native code. Arcade.PLC is a framework for the analysis and veri cation of programs for PLCs. Unmodi ed PLC programs in the languages Instruction List, Function Block Diagram, and Structured Text can be supplied by the user of the tool. Then, one function, function block or program can be selected formodel checking or static analysis. Arcade.PLC allows for specifying the intended functionality of function blocks or control programs using di erent logics as speci cation language. The integrated model checker can then prove or refute that a program conforms to the given speci cation. The otherkey aspect of Arcade.PLC is static analysis using abstract interpretation [4], which is the main focus of this paper. Figure 1 depicts the static analysis process of Arcade.PLC. Each program is rst translated into an intermediate representation (IR). This IR only contains simple instructions (assignments, jumps, conditional jumps, calls). It normalizes di erent PLC languages and simpli es further analyses. Then, a control ow graph (CFG) is build from the IR. This CFG is then analyzed with a ow-sensitive, partly context-sensitive abstract interpretation framework that annotates each node of the CFG with abstract values for the relevant variables. This information is processed by the check engine which executes a set of prede ned checks. If a violation is detected, the IR is mapped back to the original source code position and the warning is presented to the user. 2014 IEEE Emerging T ec hnology and F actory Automation (ETF A) 978-1-4799-4845-1/14/$31.00 c/circlecopyrt 2014 IEEE Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:41:16 UTC from IEEE Xplore. Restrictions apply. $ % ! % # Fig. 1. The static analysis process of Arcade.PLC [5] III. Non-Technical Challenges A. Understanding the Domain Understanding the domain of industrial automation is a key challenge for deploying static analysis techniques in this context. One very important aspect is that the development practices for control applications di er from those used in companies only dealing in software. The di erent approach to software development in the automation domain prohibits applying existing o -the-shelf solutions for general purpose programming languages. One very obvious reason for this is the use of domain-speci c programming languages, e. g., those de ned in IEC 61131-3, but the di erences go beyond that. In most cases, control programs aim to mimic the real-world and the components they are interacting with. This leads to a software development process which is based on frequent reuse of standard components to control certain parts of the system. When a program is written for a concrete system, these components are just instantiated, con gured, and connected in an appropriate way. As the developer of an application might not know all internal details of the instantiated components, there is a large potential for programming errors. On the other hand, the relative simplicity of the IEC 61131-3 languages makes them attractive for analysis. The troublesome features of other programming languages, e. g., pointers, ref- erences, and dynamic memory allocation, are not present inthese languages. Although when looking at real-world code, the hardness of this claim is softened, as there are extensions which introduce these features. Overall, the semantics of the languages used in control applications is straightforward and thus, they are easy to analyze. B. Expectations vs. Reality While most development environments for control appli- cations claim to follow the IEC 61131-3 standard [2], in practice each vendor modi es and extends on the programming languages de ned in the standard. This also applies to ABB Compact Control Builder. One very obvious deviation from IEC 61131-3 standard is that the interface and the internal variables of a function block are not de ned in the source code itself, but using specialized tables which are part of the development environment. Thus, this information has to be extracted from proprietary XML les. It can also be accessed using a special interface based on .net technology. As Arcade.PLC is based on Java, we chose not to use this interface and work on the XML les directly.We encountered one intricate extensions which makes Compact Control Builder programs syntactically incompatible with the existing Structured Text parser in Arcade.PLC: for a certain type of variable, it is possible to append the su x :status to scan their internal state. As the operator :can usually only occur within switch-statements, the existing parser reported the use of this feature as an error. One important lesson we learned is that in the end, real- world code is the best way to learn how software developers in a certain domain write code. Therefore, it is also the best way to identify the common use of programming languages as well as corner cases, which usually come with little documentation. Extensions like the previously described examples exist in many other development tools used in the automation domain as well. C. Access to Real-World Code The automation domain, in particular in the form of Compact Control Builder, comes with additional pitfalls when accessing source code for analysis. These pitfalls have organiza-tional and historical reasons. While all function block libraries are distributed as source code, the libraries are protected by encryption to avoid modi cation of the source code by the users of a library. This protection was introduced since modi cation by control engineers let to problems when di erent versions of a library were used for control applications which were relying on uno cial patches. Essentially, the fact that this encryption feature is necessary highlights that there is a lot of potential for improvement in the development process of control software. The missing information in encrypted libraries directly translates into a technical challenge: since libraries can be completely encrypted, even the signature of the function blocks in some libraries are not available for an external tool. Thus, the static analysis engine must derive an appropriate signature for types from encrypted libraries based on the way they are used in the unencrypted parts of the source code. During the adaption of Arcade.PLC for ABB Compact Control Builder, it was often not clear whether warnings were triggered by aws in the analysis or by missing information. This in turn let to a large amount of manual inspection of the source code. This issue could have been resolved by using unencrypted versions of the respective libraries, but this was not possible for all of them in the course of the project. IV . Technical Challenges A. Hidden Complexity At rst glance, many control application seem like a straightforward composition of relatively simple programorganizational units (POUs) with a dedicated functionality. However, since a control program can consist of many hundred POUs, the total number of lines of code in a program easily reaches tens of thousands. Furthermore, function block instanceshave their own internal variables and can interact through global variables. Thus, the state space to be handled by a static analysis tool can be very large. This complexity prohibits the use of simplistic analysis techniques for real-world applications. Additionally, the way function block calls are handled introduces even more variables: There are basically two ways to call a function block in most PLC languages. In the rst version, input and output parameters are passed directly (either given formal parameter names or as values only). Another, semantically equivalent way to call A function block, is to Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:41:16 UTC from IEEE Xplore. Restrictions apply. access the input and output parameters outside the call, such as: functionblock.input1 := 1; functionblock.input2 := a; functionblock(); result := functionblock.output; When implementing a static analysis which considers the data ow between function blocks, the above syntax entails that the input and output variables of every function block instance are accessible from its parent function block. For programsof realistic size, this makes the potential state space to be covered by an accurate static analysis very large. To reduce the amount of variables which have to be tracked, we use a pre- analysis for determining which variables of a function block areactually accessed in the remainder of the program [5] and only considers these variables during the analysis. This technique enables the analysis of complex programs in Arcade.PLC while still providing very accurate results, e. g., with respect to the possible value ranges of variables. B. Identifying Useful Analyses During the adaption of Arcade.PLC for Compact Control Builder we implemented checks for the following runtime errors and code smells: Conditions with constant result Illegal access into arrays or structured data types V ariables with constant values Missing case labels in switch statements Unreachable code Division by zero Most of these checks are based on well-known static analysis techniques and all of them are clearly useful from an academic perspective. However, not all of these checks yielded equally usable results in practice. All of these checks rely on the capability of Arcade.PLC to approximate the possible value range for all variables in a program. Based on this information, the additional checks can derive additional properties of a control program, e.g., that a conditional statement always yields the same result or that the value of a variable is constant. The remainder of this section will focus on the rst three checks. With respect to the check for conditions yielding a constant result, the following piece of control code shows a pattern which we frequently encountered during our case study: 42IfCONDITION1 Then 43 OUTPUT := 65535; 44ElsIf CONDITION2 Then 45 OUTPUT := INPUT1 And(INPUT2 Or(INPUT3 Xor65535)); 46ElsIf Not CONDITION2 Then 47 OUTPUT := INPUT1 And(INPUT2 Or(INPUT3 Xor0)); 48End_If; Checking the condition in line 46 is obviously super uous,as the condition in line 46 is the negation of the condition checked in line 44. Since line 46 can only be reached if the condition in line 44 is false, its condition will always be true. A simple else-statement would thus su ce in line 46 to preserve the original semantics of the code. Nonetheless, Arcade.PLC correctly reported that the condition in line 46 yields a constant result. However, since essentially every else-statement in the projects we analyzed was written in this way, this resulted in a larger number of reported warnings, which were not realproblems in the code. Thus, we ultimately chose to deactivate the analysis for conditions with constant results to make the number of warnings manageable. In addition, Compact Control Builder programs can make use of the rmware functions GetStructComponent and PutStructComponent . They allow accessing the n-th compo- nent of a structured data type. If nis less than 1 or greater than the number of elements in the structured data type, a runtime error is signaled during program execution. It is also checked if the accessed element has the wrong type. To allow for o ine checking of correct usage of these functions, Arcade.PLC rst determines the value range of the index expression of the respective calls. This is then used to check whether there are structure elements for all possible values of the indexexpression. If this is not the the case, a warning is issued. Additionally, it is also checked if all structure elements in the range described by the index expression have the correct type. The rst check is only an adaption of a well-known array index out of bounds check to these rmware functions. The second check, however, is a domain-speci c analysis which is able to detect an additional class of runtime errors statically. Two checks for constant variables were added to Ar- cade.PLC. The basic version only checks whether a variablenever changes its value over the execution of the program, while the more advanced version checks whether the constant variable is also used in a statement which should modify its value, e. g., an assignment. The rst variant only indicates a stylistic issue, while the second variant usually indicates a more severe problem in the code. During our case study, we encountered one function block where both types of warnings for constant variables were triggered. The respective variables were declared as follows: CLOCK : time := T#1m; COMPARE : int := 5; The rst variable CLOCK is a rather typical constant containing the value 1 minute and is used as a parameter for, e. g., timers. Compact Control Builder o ers the possibility to declare constants as so-called project constants , such that they are no longer variables. For projects that make use of this feature, this warning could identify other candidates that should be moved into the project constants. However, during our case study we learned that this is often not done intentionally to adjust certain values during commissioning of a system. For the other variable COMPARE , the warning was triggered that this variable contains a constant value, but is also written. It is only written in the following statement: COMPARE :=max(COMPARE,2); SinceCOMPARE is initialized to 5, the call to max will return 5, which, in turn, will not change the value of the variable. The above example illustrates how the result of static analyses can interact to implement further checks. The information about the constant value of COMPARE is combined with the information thatCOMPARE is used in an assignment statement. Furthermore, the example also demonstrates that the software engineering practices used for the development of control applications, e. g.,using variables to store constants which can be ne-tuned during commissioning, has a signi cant impact on the usefulness of certain static analyses. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:41:16 UTC from IEEE Xplore. Restrictions apply. Program #loc #FBs time #W 1 #W 2 #FP App1 / Program1 233 3<1s 6 0 0 App2 / Program2 2776 100 11 s 0 8 0 App2 / Program3 169 5 3 s 0 0 0 App2 / Program4 2684 100 146 s 0 301 0 App2 / Program5 206 12<1s 0 0 0 App3 / Program6 344 12<1s 3 0 0 App4 / Program7 3339 18 40 s 9 50 9 TABLE I. P art of the case study with anonymized program names V. C aseStudy After adapting Arcade.PLC, we were able to successfully apply it to a real-world control project comprising multiple networked PLCs. This project consisted of roughly 20 applica- tions and about 50,000 lines Structured Text (ST) code. The applications are further partitioned into programs, which share access to the same set of global variables. The programs and function blocks had between 100 and 3500 lines of ST and the programs contained up to 100 function block instances. Each of the applications had about 1000 global variables. Thus, analyzing the possible value ranges for all variables in the project was particularly challenging. Nonetheless, the complete runtime of the static analysis and the check engine on the entire project was only about 10 minutes. The anonymized results of a sample application from this case study are shown in Tab. I. The table shows the program we checked, the lines of ST code of the program (not including functions and function blocks used in the program), the numberof function blocks used (#FBs), the time for running the static analysis, the number of warnings in the main program (#W 1), the number of warning in other organization units (e. g., functionblocks) of the program (#W 2), and the number of false positives (#FP) in #W 1. All our checks were con gured in such a way that they could trigger in every location of the program including the function blocks that are used in the program. This, however, triggered warnings in these function blocks (summarized in #W 2). These warnings were raised for conditions that were always true/false and resulting in unreachable code in the function block instance. They arise because not every functionality of a function block is necessarily used in the main program. A function block might, e. g., have an input Enable to control the activation of some function. If the main program always needs this function, this input is hard-wired to true resulting in the warning condition is always true at the corresponding IF Enable THEN statement in the function block due to our context-sensitive analysis. Therefore we disabled these warnings for the function block instances used in the main program. We also disabled the warning for constant variables and only raised warnings for constant variables that are also written. After this ne-tuning, it turned out that the number of warnings and the number of false-positives was reasonably low. The remaining warnings were stylistic issues, e. g., redundant compares and disabled code, which had to be inspectedmanually. We also found a copy&paste error in Program6, in which a wrong variable name was used in one place causing unreachable code. In Program7, we got false positives for out- of-bounds accesses inside a loop. These false positives could be eliminated by introducing relational domains to our analysis,meaning also tracking the dependencies between variables. This is planned to be added in the future.VI. Related Work To the best of our knowledge, Bornot et al. [6] were the rst to describe static analysis techniques for PLC programs using an abstract interpretation framework which is similar to the one used in Arcade.PLC. Their approach, however, is limited to small programs written in Instruction List. Prahofer et al. [3] give an overview about di erent static code analysis techniques and their bene ts for IEC 61131-3 programs. Their approach is concerned with detecting bad programming practices (naming conventions, program complexity, code smells, dead locks) while our approach infers the possible values of all program variables to detect semantic programming errors. In their paper, they also give an assessment of the available commercial tools for static PLC code analysis, which, at the moment, seem to focus on syntactic checks only, e. g., the complicance with certain naming convention for variables. VII. Conclusion This paper reported on the adaption of an academic tool for static code analysis to a development environment for real- world control applications. After overcoming a multitude of challenges, both technical and non-technical, we were ableto apply static code analysis on a large software project foran industrial control system. What we learned is that when putting theory to practice, results will not always be as expected. Not every analysis which looks useful in theory can ful ll this promise in practice. On the other hand, looking at real- world code can inspire new analyses and triggers the need to optimize existing analysis techniques. We therefore believe that applying static analysis tools on large real-world projects helps tremendously in improving these tools. Whenever possible, information about the application domain should be considered. This includes considering the end user of an analysis tool. An ideal static analysis should be useful for someone who doesnot understand the underlying theories. Ultimately, practical usefulness trumps ideas which only exist on paper or can only be used by an expert in the eld. Acknowledgements This work was supported, in part, by the DFG research training group 1298 Algorithmic Synthesis of Reactive and Discrete-Continuous Systems and by the DFG Cluster of Ex- cellence on Ultra-high Speed Information and Communication,German Research Foundation grant DFG EXC 89. Further, the work of Sebastian Biallas was supported by the DFG. References [1] S. Biallas, J. Brauer, and S. Kowalewski, Arcade.PLC: A veri cation platform for programmable logic controllers, in ASE, ser. ASE 2012. ACM, 2012, pp. 338 341. [2] International Electrotechnical Commission (IEC), IEC 61131-3 Programmable Controllers Part 3: Programming languages, 2003. [3] H. Prahofer, F. Angerer, R. Ramler, H. Lacheiner, and F. Grillenberger, Opportunities and challenges of static code analysis of IEC 61131-3 programs, in ETF A, 2012. [4] P . Cousot and R. Cousot, Abstract interpretation: A uni ed lattice model for static analysis of programs by construction or approximation of xpoints, in POPL. ACM, 1977, pp. 238 252. [5] S. Biallas, S. Kowalewski, S. Stattelmann, and B. Schlich, E cient handling of states in abstract interpretation of industrial programmable logic controller code, in WODES. Cachan, France: IFAC, 2014. [6] S. Bornot, R. Huuck, B. Lukoschus, and Y . Lakhnech, Utilizing static analysis for programmable logic controllers, in ADPM, 2000, pp. 183 187. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:41:16 UTC from IEEE Xplore. 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Applying_Model_Checking_to_Industrial-Sized_PLC_Programs.pdf
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Programmable logic controllers (PLCs) are embed- ded computers widely used in industrial control systems. Ensuringthat a PLC software complies with its speci cation is a challeng-ing task. Formal veri cation has become a recommended practiceto ensure the correctness of safety-critical software, but is stillunderused in industry due to the complexity of building and man-aging formal models of real applications. In this paper, we proposea general methodology to perform automated model checking ofcomplex properties expressed in temporal logics [e.g., computa-tion tree logic (CTL) and linear temporal logic (LTL)] on PLCprograms. This methodology is based on an intermediate model(IM) meant to transform PLC programs written in various stan-dard languages [structured text (ST), sequential function chart(SFC), etc.] to different modeling languages of veri cation tools. We present the syntax and semantics of the IM, and the transfor- mation rules of the ST and SFC languages to the nuXmv modelchecker passing through the IM. Finally, two real cases studies ofthe European Organization for Nuclear Research (CERN) PLCprograms, written mainly in the ST language, are presented toillustrate and validate the proposed approach. Index T erms Automata, IEC 61131, model checking, modeling, nuXmv, programmable logic controller (PLC), veri cation. I. I NTRODUCTION DEVELOPING safe and robust programmable logic con- troller (PLC)-based control systems is a challenging task for control system engineers. One of the biggest dif culties is to ensure that the PLC program ful lls the system speci cation. Some standards, such as IEC 61508 [1], give some guidelinesand good practices, but this task remains challenging. Many dif- ferent techniques are widely applied in industry meant to check PLC programs, e.g., manual and automated testing or simu-lation facilities. However, they still present some signi cant problems, like the dif culty to check safety or liveness prop- erties, e.g., ensuring that a forbidden output value combinationnever occurs. Formal veri cation techniques can handle these Manuscript received June 30, 2014; revised June 29, 2015; accepted September 28, 2015. Date of publication October 08, 2015; date of current version December 02, 2015. Paper no. TII-15-0081. B. Fern ndez Adiego, D. Darvas, E. Blanco Vi uela, and J.-C. Tournier are with the European Organization for Nuclear Research (CERN), Geneva 1211, Switzerland (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). S. Bliudze is with the Ecole polytechnique f d rale de Lausanne, Lausanne 1015, Switzerland (e-mail: simon.bliudze@ep .ch). J. O. Blech is with Royal Melbourne Institute of Technology (RMIT) University, Melbourne, VIC 3000, Australia (e-mail: janolaf.blech@rmit. edu.au). V . M. Gonz lez Su rez is with the University of Oviedo, Oviedo 33003, Spain (e-mail: [email protected]). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identi er 10.1109/TII.2015.2489184problems, but bring other challenges to the control engineers such as the construction of the formal models and the state space explosion when applied to real-life software applications. A. Contribution Our motivation is to nd software faults (bugs) by apply- ing automated formal veri cation of complex properties expressed in temporal logic to real-life PLC control systems developed at CERN, the European Organization for Nuclear Research. We provide a general methodology for automatic cre- ation and veri cation of formal models from code written in different PLC languages, which also handles the state spaceexplosion problem. Although the main focus of this paper is on the transformation of PLC programs into formal models, we provide a description of the full methodology and illustrate it ontwo real-life examples. The speci c contributions of this paper are as follows. 1) We present the formal transformation rules from Structured Text (ST) and Sequential Function Chart (SFC) the two most used languages in CERN PLC control systems to intermediate model (IM) and givean overview of the transformation from IM to one of the selected model checker modeling languages: nuXmv. This is presented in Section IV. 2) The methods proposed in our previous work are extended to be applicable to large, industrial-size PLC programs. The methodology has been applied to real-life systems at CERN. The experimental results are discussed in Section V. This paper presents an extension of a previous work meant to bring formal veri cation to the industrial automation commu- nity. A rst method [2] was proposed to model various softwarecomponents of PLC programs developed at CERN, using the BIP framework exclusively. A rst version of the transforma- tion rules from ST code to the NuSMV modeling language isdescribed in [3]. Compared to this previous work, this paper: 1) extends and re nes the rules presented previously; 2) encom- passes other languages than ST; and 3) presents an applicationof the approach to a real-life case study. The model reduction techniques and the representation of time-related behavior is not in the main scope of this paper, but the methods used in [4]and [5] can be applied here as well. B. Related Work Although application of formal methods to PLC software has been extensively studied in the existing literature [6] [25], none of the described methods achieves the goals stated above. 1551-3203 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. FERN NDEZ ADIEGO et al. : APPLYING MODEL CHECKING TO INDUSTRIAL-SIZED PLC PROGRAMS 1401 In [6], one can nd a fairly complete survey and classi cation of PLC veri cation methods. Using this classi cation, our method is in the M-A-M group, meaning that it is a model- based approach, and relies on automata and model checking. A recent survey [26] introduces different classi cations formodel-checking methods applied to the PLC domain. Our method covers many different classes, e.g., it covers multiple PLC languages and multiple system sizes. Furthermore, it aimsto be fully automated. The application area is also broad, as PLCs are used for many purposes at CERN. Some commercial tools, e.g., SCADE from Esterel Technologies, 1provide solutions for the generation of safe PLC programs, where certi ed PLC code is automatically gener- ated from a formal speci cation. This approach does not t thepractical industrial requirements, as often already existing PLC programs have to be veri ed. In the academic literature, some of the work only targets the modeling of PLCs without providing a veri cation solu- tion [7]. Other authors apply formal veri cation, but only for small examples, without discussing the reduction in the models that are inevitable for verifying industrial-sized programs [8] [16]. Many papers do not address the generation of the modelfrom the PLC program or limit themselves to explaining the high-level principles [10] [20]. Finally, most of the work tar- gets a single PLC language, with just a few approaches handlingmultiple ones (e.g., [21] and [22]). In [18], counterexample-guided abstraction re nement (CEGAR) is applied to models of PLC programs, but onlyACTL (computation tree logic with only universal path quan- ti ers) formalism is supported for property speci cations. The work in [24] uses CEGAR too, but only for reachability analy-sis. In [23], the authors introduce powerful reduction methods applied to Instruction List (IL) code. Although this approach could be extended to other languages, reliance on satis abil-ity modulo theories (SMT) solvers restricts its applicability to safety requirements. Some work targets speci cally the veri cation of ST pro- grams [21], [22]. However, the methods described in [21] restrict the requirements to assertions, which have smallerexpressiveness than linear temporal logic (LTL) or computa- tion tree logic (CTL). Although powerful reduction techniques are proposed in [22], they also have strong limitations. Forinstance, programs can only contain non-Boolean variables and no loops. Applicability of this method for industrial-sized appli- cations at CERN is questionable, since these would containhighly complex Boolean expressions. The approach based on IM, proposed in this paper, is new in the PLC domain; however, approaches using similar veri ca-tion techniques have been applied in other domains [27], [28]. This paper is organized as follows. Section II presents a general description of PLCs. Section III is dedicated to anoverview of the methodology and the applied IM. Section IV discusses the transformation from the ST and SFC languages to IM and gives a high-level overview of the transformationsfrom IM to nuXmv and of the reduction techniques applied to IM. Section V presents experimental results obtained by applying our methodology to CERN control systems. Finally, 1[Online]. Available: http://www.esterel-technologies.com/products/scade- suite/in Section VI, we discuss the presented results and possible directions for future work. II. P ROGRAMMABLE LOGIC CONTROLLERS This section presents the PLC concepts necessary to jus- tify the proposed modeling strategy. PLC is a widely used programmable electronic device designed for controlling indus-trial processes. It mainly consists of a processing unit and input/output modules to acquire and act with sensors and actuators of the process. Even though the architecture and pro-gramming of PLCs is de ned in the IEC 61131 standard [29], there are minor differences in the implementation of differ- ent manufacturers. In this work, we focus on Siemens PLCs,since these are among the most widely used in the industry and, in particular, at CERN. However, the proposed methodology can be applied to PLCs produced by other manufacturers withonly minor adaptation of the transformation rules, necessary to accommodate the variations of PLC programming languages. A. Execution Scheme The main particularity of the PLC is its cyclic execution scheme. It consists of three main steps: 1) reading the input from periphery to the memory; 2) executing the user program that reads and modi es the memory contents; and 3) writing the values to the output periphery. The cyclic execution can be interrupted if an event (e.g., timer, hardware event, andhardware error) triggers the execution of an interrupt handler. Interrupts are preemptive; they are assigned to priority classes at compilation time. B. Program Blocks In Siemens PLCs, several kinds of program blocks are de ned for various purposes [30]. 1) A function (FC) is a piece of executable code with input, output, and temporary variables. The variables are dynamically stored on a stack and they are not retained after the execution of the function. 2) An organization block (OB) is a special function called by the system. OBs are the entry points of the user code. The main program and the interrupt handlers are implementedas OBs. 3) A data block (DB) is a group of static variables that can be accessed globally in the program. These vari- ables are stored permanently. A DB does not contain any executable code. 4) A function block (FB) is a piece of executable code with input, output, static, and temporary variables. An FB can have several instances and each instance has a separateinstance DB that stores its nontemporary variables. Thus, these variables can be accessed globally, even before or after the execution of the FB. The temporary variables arestored on a stack, as the variables of an FC. C. Programming PLCs provide several standard programming languages. Five languages are de ned in the IEC 61131-3 standard [29]: ST, Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. 1402 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 SFC, Ladder, Function Block Diagram (FBD), and IL. A PLC programmer can chose one or several of these languages, depending on the characteristics of the application, to build the PLC code. The prevalent language at CERN is ST. However, SFC and IL are also used. ILis a low-level language, syntactically similar to assembly. SFC is a graphical programing language based on nite-state machines (FSMs), described using steps (states) and transitions . Two different kinds of branches are de ned: alter- native branches (where at most one of the branches can contain active steps) and simultaneous branches (where each branch contains an active step, or none of them). This formalism is similar to the safe Petri nets, but the semantics is different: the enabled transitions are evaluated once per call and then onlythese transitions can re. If a transition becomes enabled due to a ring, it can re only on the next call of the SFC. Also, steps can have associated actions, such as variable assignments. Thislanguage is useful when part of the PLC program can be rep- resented conveniently as an FSM. STis a high-level language that is syntactically similar to Pascal. In this paper, we target ST and SFC as source languages, more precisely the languages corresponding to them in theSiemens implementations: Structured Control Language (SCL) and S7-GRAPH/SFC. The Siemens implementation follows the IEC 61131 standard as stated by the PLCOpen organization 2 and [31], but there are small syntactic differences between the standard languages and their implementation. SCL language can be used to describe all kinds of program blocks mentionedpreviously, while SFC can only represent an FB. Programs written in any of the above languages are compiled into a common byte-code representation, called MC7, whichis then transferred to the PLC. Based on our experience, we assume that the MC7 instructions are atomic and they cannot be interrupted. A single ST or SFC statement may correspondto several MC7 instructions; thus, it is possible to interrupt an ST or SFC statement. III. M ODELING AND VERIFICATION APPROACH A. Methodology Overview We propose a general methodology for applying automated formal veri cation to any PLC program written in one of the PLC languages. To support multiple PLC languages, a validsolution could be to rst translate them to IL or to machine code, and then only this single, low-level language has to be targeted by veri cation. While this method can be general, itcan cause some information loss. For example, evaluation of an arithmetic expression that could be represented both in the high-level PLC language and in the model checker input lan-guage will be split into several instructions in IL, making the reductions more dif cult and the model checkers less ef cient. Instead, the methodology presented here is based on the IM formalism designed for veri cation purposes (not for machine execution as IL). Each language is translated individually to IM. In this way we can bene t from the higher level inputs (ST vs. IL) that generally provide more information and can be reduced 2[Online]. Available: http://www.plcopen.org/pages/tc3_certi cation/certi ed_products/Fig. 1. Overview of our approach. more ef ciently. The methodology contains a set of rules which can transform automatically PLC code in different modeling languages passing through IM. Furthermore, this intermediate step allows us to compare the different model-checking tools in terms of veri cation perfor- mance, simulation facilities, and properties speci cation. More importantly, as each veri cation tool has different strengths andpurposes, we can use the appropriate tool based on our current needs. Currently, translations to the NuSMV/nuXmv, UPPAAL, and BIP veri cation tools are included in our methodology. IMis based on automata and allows us to extend our methodol- ogy with any veri cation tool which has a similar modeling language (e.g., SAL, Cadence SMV , and LTSmin). The proposed approach consists of the following steps (see Fig. 1). 1) The starting point is the source code of the PLC program and the formalized requirements coming from an informal speci cation. Using the knowledge of the PLC executionscheme, the PLC code is automatically transformed to IM. This transformation is de ned by a set of formal rules presented in Section IV. 2) Several automatic reduction and abstraction techniques are then applied to the generated model, depending on the requirement to be veri ed. 3) The reduced model is automatically translated to external modeling languages, used by the veri cation tools. 4) The resulting external models can be formally veri ed using such tools as nuXmv or UPPAAL. Other tools (e.g., BIP) provide simulation and code generation facilities, which can be useful for PLC developers. 5) Counterexamples produced by model checkers allow PLC developers to analyze the results in order to con rm thepresence of bugs in the system or re ne the models. B. Intermediate Model This section describes brie y the syntax and semantics of IM our automata-based formalism used to represent the PLC programs. We de ne a simple automata network model consist- ing of synchronized automata. Anetwork of automata is a tuple N=(A,I), whereAis a nite set of automata and Iis a nite set of synchronizations. An automaton is a structure a=(L,T,l 0,Va,Val0) A, whereL={l0,l1,...}is a nite set of locations, Tis a nite set of guarded transitions, l0 Lis the initial location of the automaton, Va={v1,...,v m}is a nite set of vari- ables, and Val0=(Val 1,0,...,Val m,0)is the initial value of the variables. Let Vbe the set of all variables in the network of automata N, i.e., V=/uniontext a AVa( a,b A:Va Vb= ifa/negationslash=b).Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. FERN NDEZ ADIEGO et al. : APPLYING MODEL CHECKING TO INDUSTRIAL-SIZED PLC PROGRAMS 1403 Atransition is a tuplet=(l,g,amt,i,l/prime), wherel Lis the source location, gis a logical expression on variables of Vthat is the guard, amt is the memory change (variable assignment, i.e., a function that de nes the new values of the variables in V), i I {NONE}is a synchronization attached to the transition, andl/prime Lis the target location. Asynchronization is a pair i=(t,t/prime), wheret Tand t/prime T/primeare two synchronized transitions in different automata. The variable assignments attached to the transitions tandt/prime should not use the same variables. This composition opera- tion is restrictive, but suf cient to model PLC programs, as synchronizations will only represent function calls. The operational semantics of this automata-based formal- ism can be informally explained as follows: a transition t= (l,g,amt,i,l/prime)from the current location lof an automaton is enabled if gis satis ed and either thas no synchronization attached, i.e., i=NONE, or i=(t,t/prime)and the transition t/primeis also enabled. In the former case, tcan re alone; in the latter case, both tandt/primehave to re simultaneously. Each execution step consists in ring one transition or simultaneous ring of two synchronized ones. Upon ring of a transition tas above, l/prime becomes the new current location of the corresponding automa- ton and the new values of variables Vare set using the previous values and the variable assignment amt. IV. M ODEL TRANSFORMATIONS This section describes in detail the most relevant transfor- mation rules from SCL and SFC to IM.3Some of these rules are generic and apply to all PLC languages; the rest are spe-ci c to SCL or SFC. In addition, a high-level description of the reduction techniques applied to IM models and the transfor- mation from IM to nuXmv are presented. Also, the main ideas of the tool implementing the methodology and some examples are discussed. This section extends and generalizes the previouswork [3]. A. General PLC to IM Transformation The transformation rules are presented hierarchically from high-level to low-level rules. Rule PLC 1 (multiple concurrent code blocks): PLC pro- grams are composed by the main program (i.e., OB1 in Siemens PLCs), which is executed cyclically, and the interrupt handlers. Assumption 1: Interrupting blocks and the interrupted blocks should use disjoint set of variables. This is a reasonable assump- tion, and it can be validated by existing static analysis tech- niques. According to our experience, different OBs usually use different variables. Furthermore, a high level of concurrency israre in PLC programs. Having this assumption, instead of modeling the interrupts in a preemptive manner, we model them with nonpreemptivesemantics: the model of the PLC scheduler consists in the main 3In the case of SCL, we have focused on the representation of the key con- structions, and we have omitted the description of, e.g., CASE blocks, REPEAT loops, and FOR loops. The handling of expressions, structure, and array initial-izations, and some Siemens-speci c constructs (e.g., shared DBs) are also not discussed, but we have implemented them following the same principles. In the case of SFC, only the action representations are omitted here.program being executed at every cycle, whereas one or several interrupts can be executed nondeterministically at the end of the PLC cycle. Rule PLC 2 (FC): This rule translates functions into IM. An OB can be considered as a special FC that is invoked by theoperating system, thus this rule also applies to OBs. Assumption 2: Recursion is not allowed, i.e., no FC or FB can directly or indirectly generate a call to itself. This assump-tion is consistent with the IEC 61131 standard [29]. However, Siemens PLCs allows the use of recursion with some restric- tions even if it is not recommended. Recursion can be staticallydetected by building the call graph of a program and checking whether it contains cycles. Thus, we can assume that variables of a function are stored at most once on the stack. For each function Func , we create an automaton A F unc .T h e locations, transitions, and initial location of this automaton are generated using the rules presented below. For each variablede ned in Func , we create a corresponding variable in A F unc . If the return type of the function is different from void ,a special output variable called RET_VAL is also added to the automaton. AF unc contains at least the initial location init,t h e nal location end, and the transition tendfrom endtoinit. Rule PLC 3 (FB instance): This rule translates FB instances into IM. Assumption 2 also applies here. For each instance inst of each FB FBlock , we create an automaton AF Block,inst . The locations, transitions, and ini- tial location of this automaton are generated using the rules presented below. For each variable in FBlock , we create a corresponding variable in all the corresponding AF Block,inst automata. Each automaton contains at least the initial location init, the nal location end, and the transition tendfrom endto initwithout any guard. Rule PLC 4 (V ariables): This rule maps program variables to variables in the IM model. Assumption 3: All variables, except system inputs, that do not have uniquely de ned initial values on the PLC platform (e.g., temporary variables, output variables of FCs) are written before they are read. This means that we do not have to model such variables as nondeterministic variables in the IM model,which allows us to limit the state space growth of the generated model. For each variable vin the program block, there is exactly one corresponding variable F V(v)in the corresponding automa- ton. If the variable represents a system input (i.e., variables representing signals coming from the eld), it is assignednondeterministically at the beginning of each PLC cycle. B. SCL to IM Transformation This section presents the rules speci c to the SCL to IM transformation. Rule SCL 1 (SCL statement): A statement is the smallest standalone element of an SCL program. It can contain other components (e.g., expressions). There are different kinds ofstatements such as conditional branches, loops, and variable assignments. In this section, we de ne the representation of a single code block consisting of these statements in our IM. For each statement stmt ,l e tn(stmt )be the next statement afterstmt . Furthermore, for a statement list sl,l e tfirst (sl) Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. 1404 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 be the rst statement of the list. Assumption 1 also applies here. For each SCL statement stmt in the program block, we generate a corresponding location marked as FL(stmt )in the corresponding automaton. If stmt is the last statement in the program block, FL(n(stmt ))is the location end of the corre- sponding automaton. This general rule is applied to any state- ment, then more speci c rules presented in the following are applied too. Rule SCL 2 (variable assignment): This rule translates SCL variable assignments to IM. Assumption 4: For each variable access the variable to be accessed can be determined at transformation time. In partic- ular, this means that pointers are not supported. However, we do support compound variables (arrays and user-de ned struc-tures). Typically, this is not a restriction as the usage of pointers is not recommended in PLC programs. For each variable assignment stmt =/angbracketleftv:=Expr/angbracketright, we add to the corresponding automaton a transition t=(F L(stmt ),TRUE,/angbracketleftFV(v):=Expr/angbracketright,NONE,FL(n(stmt ))), going from FL(stmt )toFL(n(stmt ))with no guard and no synchronization. The assignment associated with the transition updates only the variable FV(v). Rule SCL 3 (conditional statement): For each conditional statement stmt =/angbracketleftIF c THEN sl 1ELSE sl 2END _IF/angbracketright,w e add two transitions to the corresponding automaton. 1)t1=(FL(stmt ),c,/angbracketleft/angbracketright,NONE,FL(first (sl1))) goes fromFL(stmt )toFL(first (sl1)), it has no assignments and no synchronizations, and it has a guard c. 2)t2=(FL(stmt ), c,/angbracketleft/angbracketright,NONE,FL(first (sl2))) goes fromFL(stmt )toFL(first (sl2)), it has no assignments, no synchronizations and the guard c. Rule SCL 4 (while loop): For each while loop stmt = /angbracketleftWHILE c DO sl END _WHILE/angbracketright, we add two transitions to the corresponding automaton. 1)t1=(FL(stmt ),c,/angbracketleft/angbracketright,NONE,FL(first (sl)))goes from FL(stmt )toFL(first (sl)), it has no assignments and no synchronizations, and it has a guard c. 2)t2=(FL(stmt ), c,/angbracketleft/angbracketright,NONE,FL(n(stmt )))goes from FL(stmt )toFL(n(stmt ))), it has no assignments, no synchronizations, and the guard c. This transition cor- responds to exiting loop. Note that if stmt is a while loop, n(stmt )will denote the next statement after the loop . If the last statement of the loop body isstmt/prime, thenn(stmt/prime)=stmt , as after executing the last statement of the loop body, the next step is to check thecondition again. The for and repeat loops can be expressed based on the rules for conditional branches and while loops. Rule SCL 5 (FC or FB call): Assumption 5: All the input variables are assigned in the caller, and all the output variables are assigned in the callee toavoid the accessing of uninitialized variables that could con- tain unpredictable values. Therefore, they are not modeled as nondeterministic variables, which allows us to limit the statespace growth of the generated model. For every function (block) call stmt =/angbracketleft[r:=]Func (p 1:= Expr1,p2:=Expr2,...)/angbracketrightin a code block represented by an automaton Acaller, we add the following elements. ( Func can bea function or an instance of an FB, represented by an automaton Acallee.I f Func is an FB or a void function, the r:= part is omitted.) 1) A new location lwaitis added to Acaller. It represents the state when the caller block is waiting for the end of thefunction call. (For every function call, we add a separate l waitlocation.) 2) A transition t1is added to Acaller, which has no guard and goes from FL(stmt )tolwait. It assigns the function call parameters to the corresponding variables in Acallee.( I t assignsExpr1toFV(p1), etc.) 3) A transition t2is added to Acaller, which has no guard and goes from lwaittoFL(n(stmt )). It assigns RET_VAL of the callee to the corresponding variable (variable FV(r)) inAcaller,i f RET_VAL exists. It also assigns the corre- sponding values to the output variables. 4) A synchronization i1is added to the automata network, connecting transition t1with the rst transition of Acallee. 5) A synchronization i2is added to the automata network, connecting transition tendofAcallee with transition t2. C. SFC to IM Transformation This section presents a high-level overview of the rules speci c to the SFC to IM transformation. In the following discussion, we do not target the actions that can be assigned to the SFC steps. However, based on the SCL and SFC transformation rules, they can be incorporated easily. The main idea of the following transformation is that for each SFC step s, we create two variables: the step ag variable a variable that indicates if the current step is active,denoted as s.xin the standard and in the Siemens implemen- tation; and another variable that will store a copy of the s.x variables at the beginning of the SFC s call (denoted by s.x /prime in the following example). The conditions of the transitions will be evaluated on this copy, thus ring of a transition cannot make new transitions enabled. Rule SFC 1 (SFC step): For each step /angbracketleftSTEP stepName :END _STEP/angbracketright, we create a Boolean variable FV(stepName )(representing the variable referenced as step- Name .x in the PLC programs or in the standard [29]) and a variableF/prime V(stepName )for internal purposes, both initialized to FALSE. Rule SFC 2 (SFC initial step): For the initial step /angbracketleftINITIAL _STEP initStep :END _STEP/angbracketright, variables are cre- ated according to the previous rule. We also add a loca- tionl0, and a transition tIM=(l0,g,amt, NONE,end ), where g=( FV(stepName1) FV(stepName2) ...),amt = /angbracketleftFV(initStep ): =TRUE/angbracketright. It means that if no steps are active, then the initial step should become active. Before discussing the representation of transitions, we de ne as e tW={w1,w2,...}. Each item of Wis a pair wi= (Si,Ti)whereSiis a possible transition input (step or set of steps occurring in one of the transition s FROM part) andT iis the set of SFC transitions outgoing from Si. The union ofTisets inWshould contain all the transitions of the SFC. A transition input ( Si) is typically one single SFC step, but for the transitions closing simultaneous branches, it can be Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. FERN NDEZ ADIEGO et al. : APPLYING MODEL CHECKING TO INDUSTRIAL-SIZED PLC PROGRAMS 1405 composed of multiple SFC steps. These latter transitions have multiple from steps and one to step. (In the following, let l|W|+1=end.) Rule SFC 3 (SFC transitions): Assumption 6: Based on our experiments with the SFC editor of Siemens, we assume that transitions are de ned in ascending order of priority in the textual representation4that is our input. Also, if there is a transition that is leaving multiple steps at thesame time (thus closing a simultaneous branch), there should not be any other transition leaving any of these steps. If this is not respected, the SFC is regarded as syntactically incorrect inthe Siemens tools. For eachw i=(Si,Ti)=({s1,s2,...},{t1,t2,...})inW, we create the following IM representation: We create a location li. For each tj=/angbracketleftTRANSITION tName FROM s 1,s2,... TOs/prime j1,s/prime j2,... C O ND ITIO N := CE N D _TRANSITION /angbracketright, we create a transition tIM=(li,gIM, amt, NONE,li+1). The guard gIMoftIMis a Boolean expres- sion that is only true if Cis true,F/prime V(s1),F/prime V(s2),... are true, and all the guards of transitions t1,...,t j 1are false. In other words, the condition of the SFC transition should be satis ed, the input SFC step(s) should be active, andno higher priority event leaving the same SFC step(s) can re. The assignment is amt =/angbracketleftF V(s1): = FALSE ;FV(s2): = FALSE ;...;FV(s/prime j1): = TRUE ;FV(s/prime j2): = TRUE ;.../angbracketright.( W e assume that t1,t2,... are indexed in descending order of priority.) Also, for each wi, we add a transition t/prime IM= (li,g/prime,/angbracketleft/angbracketright,NONE,li+1)whereg/primeis true if no other li li+1 IM transitions are enabled. If no SFC transitions are allowed fromSi(orSiis not active), this transition allows to proceed to other transitions. Rule SFC 4 (SFC block): This rule adds the needed extra information for SFC blocks to the IM. We add a transition tIMfrominit tol0that will do a F/prime V(s): =FV(s)assignment for all SFC step s. The guard of transition tIMis true if any of the steps is active. D. Reductions on the IM The transformation described above allows us to create an IM representation of a PLC program. However, veri cation ofthe models produced from real-life programs is still not fea- sible with the available tools. In order to address this issue, we apply property-preserving reductions to the IM model. Thisemphasizes the advantage of using an IM: the reductions are only performed once and propagate automatically to the models generated for the various veri cation tools. 1) The cone of in uence (COI) reduction eliminates all the variables that do not in uence those that contribute to therequirement under analysis. 2)General rule-based reductions simplify the model by merging states or variables, eliminate unnecessary con-ditional branches, simplify the Boolean expressions, etc. 3) Using the mode selection , certain inputs (representing parameters) of the modeled system can be xed. By intro-ducing these constraints in the IM model instead of in 4The rst transition in the textual representation has the lowest priority.Fig. 2. Variable dependency graph of an example PLC program. the requirement, the other reduction methods can bene t from this knowledge. These reductions are presented in more detail in [4].In addition to the reductions above, we have developed a new method called variable abstraction . This technique is an iterative method focused on the veri cation of simple safetyrequirements, e.g., if is true, then shall be true ( AG( )in CTL), where and denote Boolean expressions on vari- ables. This technique builds the abstract models automaticallyusing the variable-dependency graph of . These models are built by replacing the selected variables with nondeterministic values (similar to the input variables). Since these variables donot depend on any others, the COI algorithm can eliminate more variables from the model. Fig. 2 shows a simple variable dependency graph for the requirement AG(a b)(so ={a}, ={b}in this exam- ple). In this graph, nodes represent variables. The gray variablesare part of the requirement ( aandb) and the edges represent dependencies (e.g., an assignment or a conditional statement). We de ned a distance metric for each variable of the graph. Its value is the smallest distance from a variable in .I nt h eith iteration, the variables with =iare replaced by nondetermin- istic values and the variables with >i are deleted. If for any a , (a)>i, thenais replaced by a nondeterministic value instead of deleting it. In the rst iteration of the example, the variables to be replaced by nondeterministic values are: a,y, andx.I ft h e veri cation result is true, then the safety requirement is sat- is ed on the original model, as the abstract model is anover-approximation of the original one. If the veri cation result is false and it cannot be determined if the counterexample is real or spurious, a new iteration is needed. More precisely, in order to abstract a set of variables V,w e perform the following steps on the abstract syntax tree of thePLC code, for each v V. 1) All assignments of the variable vare removed. 2) An assignment v:= unde ned is added at the begin- ning of the scan cycle, meaning that the value of vwill be unde ned and it will take any value from its domain. This technique is sound, i.e., if a safety property holds after variable abstraction, it holds in the original system. However, it is not complete, meaning that spurious safety violations can be detected, since variable abstraction generates behaviors notpresent in the original system. Such spurious violations can be detected by analyzing the counterexamples. Variable abstrac- tion is illustrated in Section V and its implications on theveri cation process are discussed in Section VI. E. IM nuXmv Transformation The IM model representing the PLC code has to be transformed into the concrete syntax of one or more Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. 1406 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 Fig. 3. Example SCL IM nuXmv translation. model checking tools to verify the given requirements. Our methodology is general and can be applied for any model checker with an input language based on automata or transitionsystems. Here, we brie y introduce the transformation from IM to the input language of nuXmv [32] as an example. For each automaton Ain the IM model, we create a mod- uleM Ain the nuXmv model with exactly one instance. Each variable in Ais represented by a variable in the module MA. Furthermore, a variable locis added to each module MAthat represents the current location of the automaton A. A module main is also created in the nuXmv model contain- ing a variable synch enumerating all possible synchronizations and the value NONE. At each cycle, this variable encodes the synchronization to be performed. F. Transformation Examples The following shows two examples of the transformations described in this section. Fig. 3 shows an example transformation from SCL code (1) through IM model (2) to nuXmv model (3). The SCL codecontains a conditional statement, a while loop and three vari- able assignments to Boolean and integer variables. In Part 2 of Fig. 3, one can observe the true and false branches of theconditional statement ( l 1 l2 andl1 l3 ) and the representation of the while loop ( l3 l4). The key ideas of the transformation to nuXmv can be seen in the Part 3. The variableloc de ned in line 3 represents the locations of the automaton. The transitions and guards are de ned by the case statement in lines 9 21 (e.g., line 13 represents the transition l 1 l2 with guard [ia > 0]). The variable updates are given separately in lines 23 38 (e.g., loc =l4:(IB+0sd16 _1) in line 30 for the variable update ib:=ib+1of transition l4 l5). The global structure (e.g., main module, instances, random value handling) of the generated nuXmv model can also be observed. Part 1 of Fig. 4 shows an example SFC program.5The steps are represented by gray boxes (S1, S2, etc.), and the transitions 5Note that it is a directed graph, but in Siemens notation, the arrows are only shown if direction is not top to bottom.Fig. 4. Example SFC IM translation. are represented by black rectangles. The transition T1 opens a simultaneous branch (denoted by double line), thus after ringT1, both S2 and S3 will be active. On the contrary, S3 is fol- lowed by an alternative branch: either T2 or T3 can re. If T2 res, S4 will be active; if T3 res, S5 can be active. T6 will only re if both S2 and S6 are active. Each transition can only re if its condition is evaluated to true. The conditions are not shown in the gure, but for each T i the corresponding condition (guard) is the Boolean variable C i. The corresponding IM model is shown in Part 2 of Fig. 4. For each step S i, the corresponding FV(Si)variable is denoted by si.x, the corresponding F/prime V(Si)variable is denoted by s i.x/prime.T h e reason for using both xandx/primeis to avoid transition chaining , i.e., when the ring of the transition enables another transitionthat res too. For example, ring T6 can enable T7 (provid- ing thatC 7is true), but according to the semantics of Siemens SFCs, this ring can only performed when the SFC is called for the next time. The parallel activation of S2 and S3 can be observed in the variable updates of the l1 l2IM transition. The alternative activation of S4 and S5 is visible in the l2 l3 IM transitions. The set W de ned for the transformation (cf., rule SFC3) is given in the following example: W= {({S1},{T1}),({S2,S6},{T6}),({S3},{T2,T3}),({S4}, {T4}),({S5},{T5}),({S7},{T7})}. The rst and the last transitions of the IM model contain the synchronizations with other automata. These synchronizations represent the FB call of the SFC block. G. Implementation of the Methodology The methods presented above are implemented in a proof- of-concept tool called PLCverif . The PLC input parser is implemented using Xtext.6The provided abstract syntax tree is the input of the transformation and reduction algorithms 6[Online]. Available: http://eclipse.org/Xtext/ Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. FERN NDEZ ADIEGO et al. : APPLYING MODEL CHECKING TO INDUSTRIAL-SIZED PLC PROGRAMS 1407 implemented in Java. The whole procedure is implemented in an Eclipse-based tool that allows the user to import the PLC code and de ne the requirement to be veri ed. It also performs the model transformations, the automated model reductions, and calls the model checker tools. The feedback provided tothe user is a veri cation report containing the result of the veri- cation and the eventual counterexample. The de nition of the code and requirement to be veri ed is the only task of the user,all the rest is automated and hidden. PLCverif is not available yet, but our plan is to make it production-ready and downloadable from our website. 7 V. E XPERIMENTAL RESULTS This section provides experimental veri cation results on CERN PLC programs and real requirements. Most of the con- trol systems used at CERN are developed using the Uni ed Industrial Control System (UNICOS) framework. This frame-work provides a common development process and a library of reusable base objects representing frequently used indus- trial control instrumentation (e.g., sensors and actuators). Wepresent two typical formal veri cation use cases. In the rst example, we check requirements on the model of a single base object from the UNICOS library consisting mainly ofa single FB with some function calls. The second example shows the veri cation of a requirement on a complete UNICOS application controlling a cryogenics subsystem. This applica-tion consists of hundreds of base object instances and a large application-speci c logic. A. V eri cation of a UNICOS Base Object In this section, we present the veri cation of the UNICOS base object OnOff , which represents an actuator driven by digi- tal signals (e.g., valve, heater, and motor). This object can run in different con gurations with different parameters and in various modes; it can handle various errors. In the PLC code, the OnOff object is implemented by an FB written in SCL. This FB has 600 lines of code, 60 input vari- ables, and 62 output variables. The data types used in this blockare Booleans, integers, arrays, oats, and structures, e.g., an array composed of these data types. The FB has several function calls to three different functions. The following is a real requirement expressed informally by the UNICOS developers: if the object is controlled locally (is in the so-called hardware mode) and there is no interlock, norexplicit output change request valid in this mode, the output keeps its value . To help developers to express real requirements and to facili- tate the cooperation between developers and formal veri cation experts, we de ned a set of easy-to-use requirement patterns(for details, see [33]). Using this patterns, a developer was able to formalize the requirement using variables and Boolean expressions as follows: If OutOnOV=false & TStopI=false & FuStopI=false & StartI=false is true at the end of cycle N and HLD=true & HOnR=false & HOffR=false & TStopI=false 7[Online]. Available: http://cern.ch/plcverif/TABLE I METRICS OF THE MODELS OF ONOFF & FuStopI=false & StartI=false is true at the end of cycle N+1, then OutOnOV=false is always true at the end of cycle N+1. Requirements expressed using our patterns can be automatically formalized in LTL as G((EoC OutOnOV T StopI F uStopI StartI HLD X( EoC U(EoC HLD HOnR HOffR T StopI F uStopI StartI ))) X( EoC U(EoC OutOnOV ))). In this formula, EoC is a Boolean symbol, which evaluates to true at the end of each PLC cycle and only then. Table I summarizes the performance metrics of the approach.8Before the reductions, the size of the potential state space (PSS) is 1.6 10218. After the general and requirement- dependent reductions, the PSS has 4.3 1026states, whereof 4.9 1014are reachable. Evaluation of the requirement takes 6.1 s using nuXmv without counterexample generation. Thisshowed that the requirement is not satis ed. If the counterex- ample is generated too, the run time is 19.4 s. The generation of the model including all the reductions takes 0.6 s. We used the counterexample generated by nuXmv to prove that the bug detected in our model is, indeed, a real bug. To this end, we have analyzed the counterexample and automat-ically generated a PLC program, exhibiting the bug on real hardware using the real code of the base object. This generated PLC code drives the module under veri cation to a state where the requirement is violated by feeding it with appropriate input values extracted from the counterexample. Thus, the discoveredbug was not a result of our model generation technique, but was also con rmed in the real PLC code. This methodology has been found very useful for the controls engineer. We have veri ed 52 different requirements provided by UNICOS developers for the OnOff object. Our experiments identi ed 11 cases when the requirement was not satis edon this well-tested object used in numerous CERN applica- tions. In four cases, the PLC program had to be modi ed. In seven cases, the problem was due to incomplete or badspeci cation. B. V eri cation of a Full UNICOS PLC Application We have chosen the so-called QSDN application 9as a sec- ond case study. This application controls one of the cryogenicssubsystems of the Large Hadron Collider, illustrated in Fig. 5. 8The measurements were performed on a PC with Intel Core i7-3770 3.4 GHz CPU, 8 GB RAM, on Windows 7 x64. 9QSDN stands for Cryogenics Surface Liquid Nitrogen Storage System. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. 1408 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 TABLE II METRICS OF THE MODELS OF QSDN The size of QSDN is representative of medium size UNICOS applications. It contains 110 functions and FBs, and con- sists of approximately 17 500 lines of code. Before reductions, this results in a huge generated model: the IM contains 302automata, and the PSS size is 10 31985(seeM1in Table II). Veri cation of a full UNICOS application may rely on speci- cations of base objects of the UNICOS library, instead of theirimplementation. The correctness of these objects is addressed separately (cf., Section V-A). Thus, we speedup the veri ca- tion process and focus the analysis on the potential integration errors without compromising its soundness. This is in contrast with testing, where a faulty base object could potentially hideintegration errors. Thus, the goal is to check the application-speci c logic implemented in SCL and SFC. This logic is described in theUNICOS functional analysis document, which is a semi-formal textual speci cation. Application-speci c functional require- ments are also extracted from this speci cation. Table II presents metrics relevant to the generated models. The original state space is huge and the original model obvi- ously cannot be veri ed (see M 1in Table II). Based on the requirement to be veri ed, both the general and requirement- speci c reductions can be used to reduce the model. Although these techniques have shown their ef ciency and lead to a con-siderable state space reduction, the reduced model is still huge and impossible to verify. The requirements extracted from the functional analysis are typically simple safety requirements, e.g., if is true, then is true (in CTL, AG( )), where and denote Boolean expressions on variables. The example requirement to be checked is the follow- ing: If QSDN _4_DN1CT _SEQ_DB.Stop.xis true (at the end of a scan cycle), QSDN _4_1EH4001Ok .AuOffR should be true also. Fig. 6 shows the relevant part of the QSDN PLC code. Satisfaction of the requirement cannot be shown by inspec-tion of this code part and requires additional information from the rest of the application. After the COI reduction, 3757 vari- ables are kept in the reduced model (see model M 2in Table II). Formal veri cation is still not possible. In this example, four iterations of the variables abstraction were needed to prove that the requirement is satis ed on theformal model. Using this technique, less than a minute was necessary to check this requirement (see M 3in Table II). As can be seen, our veri cation method can be used for isolatedveri cation of modules or for veri cation of complete PLC applications. Approximately 30 different requirements were extracted from the QSDN functional analysis document, all of which were proven to be satis ed using the above method.Fig. 5. QSDN process. Fig. 6. Excerpt of QSDN code relevant to the case study. VI. A NALYSIS AND DISCUSSION The proposed methodology allows the generation and anal- ysis of formal models for real-life systems. Using these tech- niques, we have identi ed bugs in real-life systems deployed at CERN. Veri cation is made possible by the reduction techniques applied to the IM representation of such systems. Among the techniques discussed in this paper, COI, general rule-basedreductions, and mode selection preserve the meaning of the model as relevant to a speci c property: the property is satis ed in the reduced model if and only if it is satis ed in the original one. The variable abstraction technique adds spurious system behaviors by introducing nondeterminism. If a safety prop- erty holds in the reduced model, it holds in the original one. However, spurious counterexamples may occur. If the propertydoes not hold in the abstract model and a counterexample is pro- duced, further analysis must be performed to determine whether it represents a real bug. Such analysis requires the expertise ofa developer and knowledge of the application. If the counterex- ample represents a possible behavior of the system, a real bug is identi ed and the veri cation process terminates. If this analy-sis cannot prove that the counterexample is spurious, the model needs to be re ned to reduce abstraction. In particular, appli- cation developers can re ne a model by providing invariants,i.e., properties that are known to be satis ed in all reachable states of the model. For example, the statement two steps of an SFC program cannot be both active at the end of the samePLC cycle is an invariant satis ed by all SFC programs that do not contain parallel branches. The above process is applied iteratively until the requirement is shown to be satis ed or a bug is identi ed. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. FERN NDEZ ADIEGO et al. : APPLYING MODEL CHECKING TO INDUSTRIAL-SIZED PLC PROGRAMS 1409 In the current state of the methodology, we cannot prove mathematically the correctness of all our model transforma- tions. However, when a discrepancy between the speci cation and the formal model is detected, we can prove that this bug exists in the real PLC program. A small piece of code called PLC demonstrator can be automatically generated out of the counterexample given by the model checker. This code repro- duces the combination of input variable values that provoke thediscrepancy and the monitor will check if the bug is reproduced also in the real PLC program. A. Correctness of Our Approach Apart from the combinatorial explosion of the state space, a fundamental limitation of all veri cation methodologies lies in the fact that requirements to be satis ed by the system are usually expressed informally. Moreover, they may be inconsis-tent [34] or fail to re ect the precise behavior expected by the designers [35]. To address this problem, we have de ned a set of easy-to-use requirement patterns [33]. Our approach is sim- ilar to the one widely adopted in the industry, where simpli ed formal languages are used by developers to de ne requirements[36] [38]. The second limitation comes from the correctness of the model-checking tools and of the result interpretation by thedevelopers. Although several model checkers are used in a variety of projects, none of the well-established model check- ers have been formally veri ed themselves. Furthermore, mostpractical veri cation methodologies involve abstraction, lead- ing to the possibility of spurious counterexamples. As with compilation warnings, developers tend to dismiss counterex-amples as spurious, whenever they cannot be easily con rmed. Although the latter problem can be partially addressed by mak- ing counterexample analysis part of the automated process (e.g.,[18]), the former is likely to persist. Thus, model checking can- not be the sole basis for system certi cation. However, we have shown that many bugs can be identi ed by formal veri ca- tion, which escape the usual testing procedures, considerably increasing the con dence one can put into industrial controlapplications. A mathematically sound correctness proof requires the estab- lishment of formal semantics for all involved languages. Usingoperational semantics for the model checker languages, our intermediate representation (cf., [3]) and the languages of the IEC 61131-3 standard (cf., [39] for IL and FBD), we can estab-lish a simulation relation between the original and transformed models: states in the original model are related with semanti- cally equivalent states in the transformed model. The simulationrelation must preserve the properties to be veri ed (the choice of the employed abstractions in uences the classes of proper- ties that are preserved [27]). One such complete proof of thecorrectness of abstraction rules that we used can be found in [5]. VII. C ONCLUSION AND FUTURE WORK We have presented a general automated methodology for for- mal veri cation of PLC programs. The methodology is based on an IM, used as a pivot between all the PLC and formalmodeling languages that we use. This approach potentially cov- ers all PLC languages. Current implementation supports SCL and SFC; the support for IL is under development. The IM model is automatically reduced, following which models for different veri cation tools are automatically generated. Thisallows us to bene t from the combined strengths of the dif- ferent veri cation tools. Current implementation allows the generation of nuXmv, UPPAAL, and BIP models. We have pre-sented the most relevant transformation rules from SCL and SFC to IM. The reduction and abstraction techniques presented in this paper are applied to the IM. On one hand, this makesthem independent from the source language, allowing veri - cation of heterogeneous PLC applications. On the other hand, this approach decouples these techniques from the choice ofthe model checker, allowing greater exibility and coherence of veri cation results. Finally, we have applied the presented methodology to real-life PLC control systems developed atCERN, demonstrating the feasibility of our approach. Formal veri cation using the presented methodology has allowed us to identify bugs in these systems, which have escaped the standard testing procedures. There are two main directions for the future work on this project. First is the improvement of the speci cation methods for control systems. Such a language must be formal, unam- biguous, and easy-to-understand. Second is the improvementof the abstraction techniques with the goal of automatizing the variable abstraction. R EFERENCES [1] Functional Safety of Electrical/Electronic/Programmable Electronic Safety-Related Systems , IEC Standard 61508, 2010. [2] B. Fern ndez Adiego, E. Blanco Vi uela, J.-C. Tournier, V . M. Gonz lez Su rez, and S. Bliudze, Model-based automated testing of critical PLCprograms, in Proc. 11th IEEE Int. Conf. Ind. Informat. , 2013, pp. 722 727. [3] B. Fern ndez Adiego, D. Darvas, J.-C. Tournier, E. Blanco Vi uela, J. O. Blech, and V . M. Gonz lez Su rez, Automated generation offormal models from ST control programs for veri cation purposes, CERN, Geneva, Switzerland, Internal Note CERN-ACC-NOTE-2014- 0037, 2014 [Online]. Available: http://cds.cern.ch/record/1708853/ les/Internal%20Note.pdf [4] D. Darvas, B. Fern ndez Adiego, A. V r s, T. Bartha, E. Blanco Vi uela, and V . M. Gonz lez Su rez, Formal veri cation of complex properties on PLC programs, in F ormal Techniques for Distributed Objects, Components, and Systems . New York, NY , USA: Springer, 2014, pp. 284 299. [5] B. Fern ndez Adiego, D. Darvas, E. Blanco Vi uela, J.-C. Tournier, V . M. Gonz lez Su rez, and J. O. Blech, Modelling and formal veri -cation of timing aspects in large PLC programs, in Proc. 19th Int. Fed. Autom. Control World Congr . , 2014, pp. 3333 3339. [6] G. Frey and L. Litz, Formal methods in PLC programming, in Proc. IEEE Int. Conf. Syst. Man Cybern. , 2000, vol. 4, pp. 2431 2436. [7] A. Mader and H. Wupper, Timed automaton models for simple pro- grammable logic controllers, in Proc. IEEE 11th Euromicro Conf. Real-Time Syst. , 1999, pp. 106 113. [8] A. S l ow and R. Drechsler, Veri cation of PLC programs using for- mal proof techniques, in F ormal Methods for Automation and Safety in Railway and Automotive Systems . Budapest, Hungary: L Harmattan, 2008, pp. 43 50. [9] D. Soliman, K. Thramboulidis, and G. Frey, Transformation of function block diagrams to UPPAAL timed automata for the veri cation of safety applications, Annu. Rev. Control , vol. 36, no. 2, pp. 338 345, 2012. [10] M. Perin and J.-M. Faure, Building meaningful timed models of closed- loop DES for veri cation purposes, Control Eng. Practice , vol. 21, no. 11, pp. 1620 1639, 2013. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply. 1410 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 [11] H. B. Mokadem, B. B rard, V . Gourcuff, O. De Smet, and J.-M. Roussel, Veri cation of a timed multitask system with UPPAAL, IEEE Trans. Autom. Sci. Eng. , vol. 7, no. 4, pp. 921 932, Oct. 2010. [12] C. A. Sarmento, J. R. Silva, P. E. Miyagi, and D. J. Santos Filho, Modeling of programs and its veri cation for programmable logic con- trollers, in Proc. 17th Int. Fed. Autom. Control World Congr . , 2008, pp. 10 546 10 551. [13] O. Pavlovi c and H.-D. Ehrich, Model checking PLC software written in function block diagram, in Proc. Int. Conf. Softw. Test. V erif. V alid. , 2010, pp. 439 448. [14] D. Soliman and G. Frey, Veri cation and validation of safety applica- tions based on PLCopen safety function blocks, Control Eng. Pract. , vol. 19, no. 9, pp. 929 946, 2011. [15] G. Canet, S. Couf n, J.-J. Lesage, A. Petit, and P. Schnoebelen, Towards the automatic veri cation of PLC programs written in instruction list, inProc. IEEE Int. Conf. Syst. Man Cybern. , 2000, vol. 4, pp. 2449 2454. [16] T. Bartha, A. V r s, A. J mbor, and D. Darvas, Veri cation of an indus- trial safety function using coloured Petri nets and model checking, inProc. 14th Int. Conf. Mod. Inf. Technol. Innov. Processes Ind. Entrep. (MITIP) , 2012, pp. 472 485. [17] N. Bauer et al. , Veri cation of PLC programs given as sequential function charts, in Integration of Software Speci cation Techniques for Applications in Engineering . New York, NY , USA: Springer, 2004, pp. 517 540. [18] S. Biallas, J. Brauer, and S. Kowalewski, Counterexample-guided abstraction re nement for PLCs, in Proc. 5th Int. Conf. Syst. Softw. , 2010, pp. 10 18. [19] J. Yoo, S. Cha, and E. Jee, A veri cation framework for FBD based software in nuclear power plants, in Proc. 15th Asia-Pac. Softw. Eng. Conf. , 2008, pp. 385 392. [20] R. Gl ck and F. Krebs, Towards interactive veri cation of programmable logic controllers using modal Kleene algebra and KIV, in Relational and Algebraic Methods in Computer Science . New York, NY , USA: Springer, 2015, pp. 241 256. [21] J. Sadolewski, Conversion of ST control programs to ANSI C for veri cation purposes, e-Informatica , vol. 5, no. 1, pp. 65 76, 2011. [22] V . Gourcuff, O. de Smet, and J.-M. Faure, Improving large-sized PLC programs veri cation using abstractions, in Proc. 17th Int. Fed. Autom. Control World Congr . , 2008, pp. 5101 5106. [23] T. Lange, M. R. Neuh u er, and T. Noll, Speeding up the safety veri ca- tion of programmable logic controller code, in Hardware and Software: V eri cation and Testing . New York, NY , USA: Springer, 2013, pp. 44 60. [24] J. Nellen, E. brah m, and B. Wolters, A CEGAR tool for the reach- ability analysis of PLC-controlled plants using hybrid automata, inF ormalisms for Reuse and Systems Integration . New York, NY , USA, 2015, pp. 55 78. [25] E. Kuzmin and V . Sokolov, Modeling, speci cation and construction of PLC-programs, Autom. Control Comput. Sci. , vol. 48, no. 7, pp. 554 563, 2014. [26] T. Ovatman, A. Aral, D. Polat, and A. O. nver, An overview of model checking practices on veri cation of PLC software, Softw. Syst. Model. , 2014, doi: 10.1007/s10270-014-0448-7. [27] M. Bozga, S. Graf, L. Mounier, and I. Ober, Modeling and veri cation of real time systems using the IF toolbox, in Real Time Systems 1: Modeling and V eri cation Techniques . Cachan, France: Hermes/Lavoisier, 2008, vol. 1, ch. 9. [28] M. Bozga, S. Graf, L. Mounier, and I. Ober, IF validation environment tutorial, in Model Checking Software . New York, NY , USA: Springer, 2004, pp. 306 307. [29] Programmable controllers , IEC Standard 61131, 2013.[30] Siemens, SIMATIC Programming With STEP7 Manual , 2010, A5E02789666-01 [Online]. Available: https://support.industry.siemens. com/cs/document/45531107/simatic-programming-with-step-7-v55 [31] Siemens, Standards Compliance According to IEC 61131-3 , 2011 [Online]. Available: http://support.automation.siemens.com/WW/view/ en/50204938 [32] R. Cavada et al. , The nuXmv symbolic model checker, in Computer Aided V eri cation . New York, NY , USA: Springer, 2014, pp. 334 342. [33] B. Fern ndez Adiego, D. Darvas, J.-C. Tournier, E. Blanco Vi uela, and V . M. Gonz lez Su rez, Bringing automated model checking to PLCprogram development A CERN case study, in Proc. 12th Int. Workshop Discr . Event Syst. , 2014, pp. 394 399. [34] R. Alur et al. , Formal speci cations and analysis of the computer- assisted resuscitation algorithm (CARA) infusion pump control system, Int. J. Softw. Tools Technol. Transfer , vol. 5, no. 4, pp. 308 319, 2004. [35] G. Klein et al. , seL4: Formal veri cation of an OS kernel, inProc. ACM SIGOPS 22nd Symp. Oper . Syst. Principles , 2009, pp. 207 220. [36] M. Dwyer, G. Avrunin, and J. Corbett, Patterns in property speci cations for nite-state veri cation, in Proc. 21st Int. Conf. Softw. Eng. , 1999, pp. 411 420. [37] I. Beer, S. Ben-David, C. Eisner, D. Fisman, A. Gringauze, and Y . Rodeh, The temporal logic Sugar, in Computer Aided V eri cation .N e wY o r k , NY , USA: Springer, 2001, pp. 363 367. [38] R. Armoni et al. , The ForSpec temporal logic: A new temporal property- speci cation language, in Tools and Algorithms for the Construction and Analysis of Systems . New York, NY , USA: Springer, 2002, pp. 296 311. [39] J. O. Blech and S. O. Biha, Veri cation of PLC properties based on formal semantics in Coq, in Software Engineering and F ormal Methods . New York, NY , USA: Springer, 2011, pp. 58 73. Borja Fern ndez Adiego , photograph and biography not available at the time of publication. D niel Darvas , photograph and biography not available at the time of publication. Enrique Blanco Vi uela , photograph and biography not available at the time of publication. Jean-Charles Tournier , (M 09) photograph and biography not available at the time of publication. Simon Bliudze , photograph and biography not available at the time of publication. Jan Olaf Blech , (M 05) photograph and biography not available at the time of publication. V ctor Manuel Gonz lez Su rez , photograph and biography not available at the time of publication. Authorized licensed use limited to: Air Force Institute of Technology. Downloaded on February 11,2025 at 16:42:56 UTC from IEEE Xplore. Restrictions apply.
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1400 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 6, DECEMBER 2015 Applying Model Checking to Industrial-Sized PLC Programs Borja Fern ndez Adiego, D niel Darvas, Enrique Blanco Vi uela, Jean-Charles Tournier, Member , IEEE , Simon Bliudze, Jan Olaf Blech, Member , IEEE , and V ctor Manuel Gonz lez Su rez
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