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{"category": "Physics", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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{"category": "Human Necessities", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.051758 | 0.01001 | 0.023315 | 0.006104 | 0.324219 | 0.02478 |
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{"category": "Physics", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Performing Operations; Transporting"}
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Does the patent belong in this category?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.337891 | 0.014038 | 0.496094 | 0.051758 | 0.746094 | 0.112793 |
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Physics"}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Chemistry; Metallurgy"}
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Is the categorization of this patent accurate?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.008057 | 0.001648 | 0.035156 | 0.025513 | 0.070801 | 0.019165 |
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{"category": "Physics", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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{"category": "Textiles; Paper", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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Does the patent belong in this category?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.333984 | 0.054199 | 0.496094 | 0.006683 | 0.734375 | 0.148438 |
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{"category": "Physics", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Fixed Constructions"}
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Does the patent belong in this category?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.333984 | 0.00885 | 0.496094 | 0.04541 | 0.746094 | 0.08252 |
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{"category": "Physics", "patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention ."}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Does the patent belong in this category?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.353516 | 0.014954 | 0.496094 | 0.02063 | 0.734375 | 0.038574 |
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Physics"}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Electricity"}
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Is the patent correctly categorized?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.00885 | 0.000607 | 0.032471 | 0.005066 | 0.079102 | 0.005554 |
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "Physics"}
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{"patent": "without being bound by theory , fig2 shows the general configuration of data for hybrid exposure . exposure data d 1 is divided into data for eb exposure d 2 and data for reticle exposure d 3 . the data for reticle exposure 33 is data to expose the center portion of the exposure data d 1 , and the data for eb exposure d 2 is data to expose the periphery of the exposure data d 1 . when eb exposure is performed by the data for eb exposure d 2 , and reticle exposure is performed by the data for reticle exposure d 3 , an exposure pattern p is exposed . specifically , by reticle exposure using the data for reticle exposure d 3 , the center portion of the exposure pattern p is exposed at a low accuracy ; and by eb exposure using the data for eb exposure d 2 , the peripheral portion of the exposure pattern p is exposed at a high accuracy . without being bound by theory , fig2 a to 21d show defects produced by low - accuracy reticle exposure using a krf light source ( krf exposure ). when data for reticle exposure d 6 is prepared inside exposure data d 5 , whether or not the data d 6 satisfies the design rule of the pattern for krf exposure is judged . then , as shown in fig2 a , when the violating portion v 1 wherein the pattern width does not satisfy the reference value is produced in the data d 6 , as shown in fig2 b , the violating portion v 1 is removed , and the data d 6 is divided into data for reticle exposure d 7 and d 8 . then , a fine step wherein pattern distance does not satisfy the reference value is produced as a violation site v 2 between data d 7 and d 8 . consequently , as shown in fig2 c , if treatment to enlarge the distance of the violation site v 2 is performed to prepare data d 9 and d 10 , a fine step that does not satisfy the reference value is produced as a violation site v 3 in the data d 9 and d 10 . in order to remove the violation site v 2 between data d 7 and d 8 , if data d 11 and d 12 are prepared so as to separate the data d 7 and d 8 in the height direction , as shown in fig2 d , a fine step that does not satisfy the reference value is produced as a violation site v 4 in the data d 12 . since the violation site detecting treatment and the data correcting treatment as described above are performed by image processing wherein the coordinate of each image data is compared with the reference value and the coordinate of the violation site is changed to satisfy the reference value , additional time is required for the correcting treatment . then , any new violation site produced by the correcting treatment requires further time for treatment . hereafter , an embodiment in accordance with aspects of the present invention will be described referring to the drawings . fig1 is a flow chart showing procedures for preparing data for hybrid exposure according to aspects of the present embodiment . in step 1 , the size and the disposing distance of a plurality of square rectangular patterns a are obtained from the reticle preparing standards . in the pattern data for reticle preparation , the minimum pattern width w , the minimum pattern distance d , and the minimum pattern step g shown in fig2 are set up as the preparation rule . as shown in fig3 , the rectangular size s of the rectangular patterns a are made to be : minimum pattern step g = rectangular size s + disposing distance da minimum pattern width w = rectangular size s \u00d7 n + disposing distance da \u00d7( n \u2212 1 ) where n is the number of rectangular patterns a obtained from minimum pattern width w \u00f7 minimum pattern step g , and when there is a remainder , n + 1 is used . the minimum pattern distance d is set up as a value obtained by adding a reticle preparation margin m 1 to the minimum distance wx specified by the design rule of the exposure pattern as shown in fig4 , and can be optionally changed by adjusting the reticle preparation margin m 1 . the reticle preparation margin m 1 is generally required for hybrid exposure , when reticle exposure and eb exposure are performed ; the margin is set up so as to maintain the pattern of exposure within the margin even if displacement occurs in reticle exposure . in fig4 , ar 1 represents the eb exposure region , and ar 2 inside ar 1 represents the reticle exposure region . an overlapping margin m 2 where the eb exposure region ar 1 overlaps the reticle exposure region ar 2 is set up . aspects of this embodiment will be described on the basis of these specific preparation rules . as shown in fig8 , when the minimum pattern width w is set up to be 300 nm and the minimum pattern step g is set up to be 90 nm , the rectangular size is 30 nm , the disposing distance da is 60 nm , and the disposing number n is 4 from the above equations . next , in step 2 , as shown in fig5 , exposure pattern data rd for performing hybrid exposure is retrieved as an input pattern , and the exposure pattern data rd is contracted by the reticle preparing margin m 1 to prepare an object pattern pa . the object pattern pa is the region subjected to reticle exposure . next , in step 3 , as shown in fig6 , the object pattern pa is lined with the rectangular patterns a calculated in step 1 . next , in step 4 , the centers of regions lined with n \u00d7 n rectangular patterns a ( illustrated as regions having 4 \u00d7 4 rectangular patterns ) obtained . each of these regions may be partially overlapped . then in fig6 , centers c 1 to c 7 are obtained . next , in step 5 , the n \u00d7 n regions corresponding to each of centers c 1 to c 7 are set up as rectangular patterns b 1 to b 7 . then , in step 6 , the presence of any violation to the minimum pattern width w and the minimum pattern distance d is detected on the basis of the x - y coordinate of each of centers c 1 to c 7 . here , the principle of detecting the presence of a violation to the minimum pattern width w and the minimum pattern distance d , and the principle of the correcting treatment will be described referring to fig7 . as shown 4 n fig7 a , the width of the rectangular pattern b is the minimum pattern width w , and the sum of the rectangular size s and the disposing distance da , ( soda ), is the minimum pattern step g . here , the rectangular pattern b is described in the case of n = 3 . as shown in fig7 b and 7c , when the x - y coordinate of the rectangular pattern ba is x 1 , y 1 , and the x - y coordinate of the rectangular pattern bb is x 2 , y 2 , the minimum pattern width w between the rectangular patterns ba and bb is violated under the following conditions . specifically , as shown in fig7 b , when the value of | x 1 \u2212 2 | is the minimum pattern width w or less , and the value of y 1 \u2212 y 2 | is the minimum pattern width w or less , the minimum pattern width w between rectangular patterns ba and bb has been violated . in this case , if either one of | x 1 \u2212 x 2 | or | y 1 \u2212 y 2 | is 0 , the reticle exposure pattern is not violated . as shown in fig7 c , when | x 1 \u2212 x 2 |\u2212 w is less than the minimum pattern distance d , and | y 1 \u2212 y 2 |\u2212 w is less than the minimum pattern distance d , the minimum pattern distance d between the rectangular patterns ba and bb are violated . in this case , the coordinate distance is made to be the minimum pattern width w or more . when the centers ca and cb of rectangular patterns ba and bb are located in the diagonal direction to x - axis and y - axis , since the distance between the centers ca and cb is larger than the distances in the x - axis direction and y - axis direction , any violations are judged with consideration for the increase in the distance . when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| x 2 \u2212 x 1 |\u00f7 r is calculated , the number of rectangular patterns a in the x direction in the region of the rectangular patterns b that is in violation to the minimum pattern width w can be obtained . similarly , when the sum of the rectangular size s and the disposing distance da is r , and n \u2212| y 2 \u2212 y 1 |\u00f7 r is calculated , the number of rectangular patterns a in the y direction in the region of the rectangular patterns b that are in violation to the minimum pattern width w can be obtained . also when (| x 2 \u2212 x 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the x direction can be obtained . similarly , when (| y 2 \u2212 y 1 |\u2212 w )\u00f7 r is calculated , the number of rectangular patterns a that violate the minimum pattern distance d in the region of the rectangular patterns b in the y direction can be obtained . when the direction between two center points ca and cb is considered , the violation of rectangular patterns a in rectangular patterns b can be specified . on the basis of the violation detection principle for the minimum pattern width w and the minimum pattern distance d , the treatment of step 6 is performed . specifically , in fig9 , rectangular patterns al overlapping in rectangular patterns b 4 and b 6 are detected to be subjected to the minimum pattern width w . in the object pattern pa shown in fig9 , violation to the minimum pattern distance d is assumed not to occur . next , in step 7 , the presence of a violation is judged . if a violation is present , the rectangular patterns a related to the violation site are deleted . therefore , in fig9 , since rectangular pattern a 1 violates the rule , rectangular pattern a 1 is deleted . next , the treatments of steps 4 and 5 are performed again . then , as shown in fig1 and 11 , centers c 4 and c 5 are deleted from the state shown in fig6 , and rectangular patterns b 4 and b 5 are deleted . next , the treatment of step 6 is performed again . since no violation sites are found in fig1 , steps 7 to are conducted . in step 9 , the rectangular patterns b 1 , b 2 , and b 3 shown in fig1 are combined to form a reticle exposure pattern rp 1 shown in fig1 . a reticle exposure pattern rp 2 is formed from the rectangular pattern b 6 , and a reticle exposure pattern rp 3 is formed from the rectangular pattern b 7 . then , each of the reticle exposure patterns rp 1 to rp 3 is contracted by the overlapping margin m 2 with eb exposure to form patterns pe 1 to pe 3 for preparing eb exposure data . next , in step 10 , as shown in fig1 , the pattern wherein the patterns pe 1 to pe 3 for preparing eb exposure data are removed from the exposure pattern data rd ls formed as eb exposure pattern ebp . then , as shown in fig1 , from the exposure pattern data rd for hybrid exposure retrieved in step 2 , reticle exposure patterns rp 1 to rp 3 and the eb exposure pattern ebp are formed . next , in step 11 , the correcting treatment of overlapping margins m 2 in the corner portions of reticle exposure patterns rp 1 to rp 3 are performed . for example , if hybrid exposure is performed using the reticle exposure pattern rp 4 and the bb exposure pattern ebp 1 as shown in fig1 a , the accuracy of reticle exposure is poor . therefore , actually exposed pattern rp 4 a is rounded at the corner portion x in the convex direction of the reticle exposure pattern rp 4 as shown in fig1 b . as a result , overlapping margins m 2 may be insufficient as shown in fig1 c . therefore , as shown in fig1 a , rectangular portions y having a height of \u03b1 are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , specifically , the corner portions facing the corner portion x of the reticle exposure pattern rp 4 . the value of \u03b1 is optionally determined so as to compensate the insufficiency of the overlapping margins m 2 . by performing hybrid exposure using such a reticle exposure pattern ebp 2 , the overlapping margins m 2 on the corner portions x of the reticle exposure pattern fp 4 can be secured . thus , the corner portions of the pattern can be accurately exposed . fig1 and 18 show other examples of methods for laying the rectangular patterns a . if the largest possible number of rectangular patterns a are laid on an object pattern pa , the region that can be exposed by reticle exposure may be expanded . if the reticle exposure region is expanded , the throughput of hybrid exposure can be improved . specifically , compared with the case wherein rectangular patterns a are laid so as not to contact the contour lines of the object pattern pa as shown in fig1 , if rectangular patterns a are laid so as to contact the inside of the contour lines of the object pattern pa as shown in fig1 , the number of rectangular patterns a that can be laid on the object pattern pa can be increased . therefore , by laying a larger number of rectangular patterns a in the object pattern pa , the number of rectangular patterns b in the object pattern pa can be increased , and in turn , by increasing the number of rectangular patterns b the reticle exposure region can be enlarged . fig1 shows the case where object pattern pa are laid out by the contour line diagonal to the x - axis and the y - axis . as shown in fig1 a , when rectangular patterns a are laid on an object pattern pa in the diagonal direction , and the treatment as described above to form a reticle exposure pattern is performed , as shown in fig1 b , the contour line of the formed reticle exposure pattern rp 5 becomes stair - like steps ga . then , the length of a side of the steps ga is the sum of the size of the rectangular patterns a and the disposing distance da . the steps ga may become a simulated error in the reticle test . in such a case , as shown in fig1 c , steps ga are extracted , and as shown in fig1 d , rectangular patterns ax a side of which equals a step ga are inserted in each step ga . then , as shown in fig1 e , the diagonal of the rectangular patterns ax that overlaps the contour line of the object pattern pa is made to be the contour line of the reticle exposure pattern , and combined with the reticle exposure pattern rp 5 to form the reticle exposure pattern rp 6 . by providing such treatments , simulated errors in the reticle test can be prevented , and the reticle exposure region can be widened . according to aspects of the method for preparing data for exposure as described above , the following effects can be obtained . ( 1 ) the object pattern pa can be lined with rectangular patterns a formed by the reticle preparation rule ; rectangular patterns b can be formed from the rectangular patterns a ; the pattern width and the pattern distance of the reticle exposure pattern can be verified from the center location of the rectangular patterns b ; and violation sites can be corrected . therefore , since the verification of the pattern width and the pattern distance using the coordinate of the object pattern pa is not required , the verifying process can be easily conducted . ( 2 ) the size s and the disposing distance da of the rectangular patterns a can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 3 ) the number n of the rectangular patterns a disposed on the sides of the rectangular patterns b can be easily calculated from the minimum pattern width w and the minimum pattern step g in the reticle preparation rule . ( 4 ) the sites that violate the minimum pattern width w and the minimum pattern distance d can be easily detected on the basis of the center location of the rectangular patterns b . ( 5 ) by deleting rectangular patterns a in the sites that violate the minimum pattern width w and the minimum pattern distance d to reform the rectangular patterns b , and detecting whether the sites that violate the minimum pattern width w and the minimum pattern distance d are present or not , on the basis of the distance between the center locations of the reformed rectangular patterns b , the correcting treatment of the violation sites can be easily performed . ( 6 ) whether a violation of the minimum pattern width w is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 | is the minimum pattern width w or less ; and whether or not the value | y 1 \u2212 y 2 | is the minimum pattern width w or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 7 ) whether a violation of the minimum pattern distance d is present or not can be detected by calculating whether or not the value | x 1 \u2212 x 2 |\u2212 w is the minimum pattern distance d or less ; and whether or not the value | y 1 \u2212 y 2 |\u2212 w is the minimum pattern distance d or less ; on the basis of the x - y coordinate of the center of the rectangular patterns b . ( 8 ) when a hypotenuse is present in the object pattern pa , rectangular patterns ax can be inserted in the stair - like step ga formed as the reticle exposure patterns , and the diagonals of the rectangular patterns ax can be used as the reticle exposure patterns . therefore , simulated error in the reticle test can be prevented , and the reticle exposure region can be widened . the above - described embodiment in accordance with aspects of the present invention can also be executed in the aspect described below . rectangular locations can be set up by grids ( points ) in place of the rectangular patterns a . in this case , the distance between grids can be set up to be the minimum step g in the reticle preparation rule . in the process shown in fig1 , although rectangular portions y having a height of a are formed on the corner portions in the concave direction of the eb exposure pattern ebp 1 , stair - shape other than rectangular , or triangular patterns can also be formed . although the embodiment is described as a method for preparing reticle exposure pattern data , the method can be conducted as a method for preparing pattern data of the mask used in the exposure process , and the mask pattern can be formed on the mask substrate . all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions , nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention . although the embodiment ( s ) of the present invention ( s ) has ( have ) been described in detail , it should be understood that the various changes , substitutions , and alterations could be made hereto without departing from the spirit and scope of the invention .", "category": "General tagging of new or cross-sectional technology"}
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Is the patent correctly categorized?
| 0.25 |
0cc06d77880b51281b2a9ed7f9dbd59497dd7c3d6b86ddf4df6b737fdc7fa1f2
| 0.009155 | 0.030273 | 0.032471 | 0.169922 | 0.079102 | 0.08252 |
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{"category": "Electricity", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
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{"category": "Human Necessities", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
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Is the patent correctly categorized?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.765625 | 0.003937 | 0.886719 | 0.015869 | 0.929688 | 0.009399 |
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{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Electricity"}
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{"category": "Performing Operations; Transporting", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
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Does the category match the content of the patent?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.425781 | 0.006104 | 0.291016 | 0.008057 | 0.275391 | 0.332031 |
null |
{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Electricity"}
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{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Chemistry; Metallurgy"}
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Is the patent correctly categorized?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.047363 | 0.002045 | 0.109863 | 0.005737 | 0.172852 | 0.012451 |
null |
{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Electricity"}
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{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Textiles; Paper"}
|
Is the patent correctly categorized?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.047363 | 0.001648 | 0.109863 | 0.002396 | 0.172852 | 0.00885 |
null |
{"category": "Electricity", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
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{"category": "Fixed Constructions", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
|
Is the patent correctly categorized?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.765625 | 0.037842 | 0.886719 | 0.400391 | 0.929688 | 0.539063 |
null |
{"category": "Electricity", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
|
{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
|
Does the category match the content of the patent?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.699219 | 0.005219 | 0.746094 | 0.017944 | 0.835938 | 0.037354 |
null |
{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Electricity"}
|
{"patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material .", "category": "Physics"}
|
Does the category match the content of the patent?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.425781 | 0.050293 | 0.291016 | 0.033203 | 0.275391 | 0.195313 |
null |
{"category": "Electricity", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
|
{"category": "General tagging of new or cross-sectional technology", "patent": "before entering into a description of the embodiment , a prior art dram will be described with reference to fig1 to 4 . fig2 and 3 are sectional views of the conventional dram of fig1 taken along the lines ii -- ii and iii -- iii . fig4 shows the circuit structure of the device of fig1 . reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 a silicon dioxide ( sio 2 ) dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer ; 5 an n + type region as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) address lines ( gate electrodes ) of a second polycrystalline silicon layer , respectively ; 9 an n + type drain region ; 10 a phosphosilicate glass ( psg ) insulating interlayer ; 11 a contact hole ; 12 a contact pad ; and 19 ( 1 ), 19 ( 2 ), 19 ( 3 ), and 19 ( 4 ) data lines of a single aluminum film . the transistor regions t , the capacitance region c , the word lines , and a bit line in fig1 are shown correspondingly in the circuit structure of fig4 . in the prior art dram shown in fig1 to 4 , the parallel data lines 19 ( 1 ) to 19 ( 4 ) are constituted by a single aluminum film . however , in the structure wherein the data lines 19 ( 1 ) to 19 ( 4 ) are constituted by the single wiring material layer , e . g ., the aluminum film in this example , the interval of the data lines 19 ( 1 ) to 19 ( 4 ) is decreased , and the width of each of the data lines 19 ( 1 ) to 19 ( 4 ) must be decreased accordingly upon further micropatterning of the memory cells . in the structure shown in fig1 to 4 , when the wiring pitch is given as 3 . 5 \u03bcm and a width of the contact pad 12 is increased to be larger by , for example , 0 . 5 \u03bcm than that of the wiring width , the wiring width and the wiring interval are given as 1 . 5 \u03bcm . this width has been used in conventional 256 kbit or 1 mbit dram &# 39 ; s . when the dram is highly integrated and the wiring pitch is decreased to about 2 . 0 to 1 . 5 \u03bcm , the wiring width and the wiring interval must be decreased to 0 . 75 to 0 . 5 \u03bcm when the margin of the contact pad is given as described above . a semiconductor memory device according to an embodiment of the present invention is illustrated in fig5 to 8 . fig5 is a plan view of a dram , and fig6 is a sectional view thereof taken along the line vi -- vi of fig5 . a wiring portion of the prior art dram and that of the dram of fig5 are illustrated in fig9 a and 9b . fig8 shows the circuit structure of the device of fig5 . fig9 shows a modification of the wiring pattern . referring to fig5 to 8 , reference numeral 1 denotes a p type silicon substrate ; 2 an element isolation oxide film ; 3 an sio 2 dielectric film ; 4 a capacitor electrode of a first polycrystalline silicon layer pa ; 5 an n + type region serving as one electrode of the capacitor ; 6 a gate oxide film ; 7 an sio 2 insulating film ; 8 ( 1 ), 8 ( 2 ), 8 ( 3 ), and 8 ( 4 ) gate electrodes serving as address lines made of a second polycrystalline silicon layer pb , respectively ; 9 an n + type drain region ; 10 a first psg insulating interlayer ; 13 a contact hole between a lower wiring layer and the drain region 9 ; 14 a second psg insulating interlayer ; and 15 a contact hole between the upper wiring layer and the drain region 9 . reference numerals 17 ( 2 ) and 17 ( 1 ) are lower data lines made of a lower aluminum film , respectively ; 18 ( 2 ) and 18 ( 1 ) are upper data lines made of an upper aluminum film . each memory cell includes one transistor t and one capacitor c as in the prior art device . in the dram shown in fig5 the plurality of parallel data lines sequentially constituted by a wiring layer of a single wiring material such as aluminum are alternately formed by the upper and lower aluminum films insulated through the second insulating interlayer 14 in an order of 17 ( 2 ), 18 ( 2 ), 17 ( 1 ), and 18 ( 1 ). further , the data lines 18 ( 2 ) and 18 ( 1 ) formed by the upper aluminum film overlap the adjacent data lines of the lower aluminum film , respectively . as shown in fig9 a , a prior art structure has data lines of a single layer . assume that parallel data lines 19 ( 1 ), 19 ( 2 ), . . . 19 ( 7 ) are formed in a wiring region at a wiring width of 1d and a wiring interval of 1d . however , as shown in fig9 b , the data lines 18 ( 1 ), 17 ( 2 ), 18 ( 2 ), 17 ( 3 ), 18 ( 3 ), 17 ( 4 ), and 18 ( 4 ) can be formed in the same wiring area as that of the conventional dram at a wiring width of 3d and a wiring interval of 1d . therefore , the wiring width of the data line of the dram of this embodiment can be increased to three times that of the prior art dram . as shown in fig1 , for example , recesses 16 may be formed in the lower data lines 17 ( 2 ) and 17 ( 3 ) to detour the contact hole 15 formed between the upper data lines 18 ( 2 ) and 18 ( 3 ). in this case , the width of the lower data lines 17 ( 2 ) and 17 ( 3 ) can be larger than that shown in fig5 up to that defined by a maximum interval defined by insulation and connection of the wirings of an identical layer . however , the upper data lines 18 ( 2 ) and 18 ( 3 ) do not have the limits described above , so the wiring interval can be maximized in association with a minimum wiring interval . a preferred circuit diagram applicable to the device according to the present invention in connection with sense amplifiers is shown in fig1 . the circuit arrangement shown in fig1 requires a slight modification of the layout structure of fig5 but has an advantage of a superior symmetrization of electrical characteristic between data line pair associated with a sense amplifier , which is desirable in drams . data lines dl 0 and dl 0 connected with the first sense amplifier are located in the upper layer . data lines dl 1 and dl 1 connected with the second sense amplifier are located in the lower layer . in the circuit arrangement of fig1 , where the data lines are divided into a first group of data lines dl and a second group of data lines dl , the characteristic of symmetry between the data lines is attained satisfactorily . the present invention is exemplified by a dram . however , the present invention can also be applied to other semiconductor memory devices such as static ram &# 39 ; s and static rom &# 39 ; s . the wiring material is not limited to aluminum , but can be extended to any other proper material ."}
|
Is the categorization of this patent accurate?
| 0.25 |
1f77d3a1a04a4e771dddd95efa4da6507f13a24380f003ddef8e7a01af37536f
| 0.691406 | 0.1875 | 0.777344 | 0.667969 | 0.792969 | 0.382813 |
null |
{"category": "Chemistry; Metallurgy", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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{"category": "Human Necessities", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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Is the patent correctly categorized?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.083984 | 0.033203 | 0.566406 | 0.026001 | 0.34375 | 0.021973 |
null |
{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Chemistry; Metallurgy"}
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{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Performing Operations; Transporting"}
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Does the patent belong in this category?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.007355 | 0.003082 | 0.178711 | 0.002182 | 0.167969 | 0.016968 |
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{"category": "Chemistry; Metallurgy", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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{"category": "Textiles; Paper", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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Does the patent belong in this category?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.081543 | 0.010315 | 0.792969 | 0.00007 | 0.371094 | 0.002884 |
null |
{"category": "Chemistry; Metallurgy", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
|
{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Fixed Constructions"}
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Does the category match the content of the patent?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.027588 | 0.169922 | 0.609375 | 0.066406 | 0.253906 | 0.133789 |
null |
{"category": "Chemistry; Metallurgy", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
|
{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
|
Is the category the most suitable category for the given patent?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.009399 | 0.00004 | 0.08252 | 0.000246 | 0.114258 | 0.007111 |
null |
{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Chemistry; Metallurgy"}
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{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Physics"}
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Is the patent correctly categorized?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.005371 | 0.00885 | 0.081543 | 0.022339 | 0.131836 | 0.069336 |
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{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "Chemistry; Metallurgy"}
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{"category": "Electricity", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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Does the category match the content of the patent?
| 0.25 |
ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.024048 | 0.004211 | 0.246094 | 0.001755 | 0.183594 | 0.006104 |
null |
{"category": "Chemistry; Metallurgy", "patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein ."}
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{"patent": "embodiments of the invention are directed to processes for formulating a glucose oxidase enzyme with a particular desired property , such as , for example , an improved resistance to peroxide . embodiments of the invention employ forced mutations that yield glucose oxidase enzymes that may or may not have an improved characteristic , such as an improved resistance to peroxide . screening and / or testing procedures may be employed to assist in identifying mutated enzymes that might have desired qualities , such as peroxide resistant qualities . an enzyme derived from embodiments of the invention may be suitable for use , for example , in a biosensor . an enzyme derived from these embodiments may improve the performance and stability of a sensor . various biosensor configurations employ active enzymes as part of the sensor structure . embodiments of the invention may be employed to produce active enzymes for various types of sensors . however , in one example embodiment , a process produces an enzyme for use in a sensor as described in co - pending u . s . patent application \u201c method for formulating and immobilizing a matrix protein and a matrix protein for use in a sensor ,\u201d filed dec . 27 , 2001 , ( attorney docket number 047711 - 0288 ). [ 0027 ] fig2 shows a flowchart diagram of a process for utilizing a directed evolution procedure to formulate an enzyme having an improved resistance to peroxide , according to an embodiment of the invention . initially , the embodiment illustrated in fig2 involves selecting or obtaining several glucose oxidase genes . the glucose oxidase genes can be taken from , for example , a yeast or a bacteria . in an example embodiment , the glucose oxidase genes are taken from aspergillus niger (\u201c a . niger \u201d ). however , in other embodiments , the genes could be derived from any member of a group including , but not limited to , a . niger , penecillium funiculosum , saccharomyces cerevisiae , escherichia coli ( e . coli ), and the like . those skilled in the art will appreciate that the glucose oxidase genes could also be derived from other similar yeasts or bacteria . next in the example embodiment illustrated in fig2 a library of mutant genes or variants may be created . in this context , a mutation refers to a random change in a gene or chromosome resulting in a new trait or characteristic that can be inherited . the process of creating a library of mutants represents a change in the enzyme . mutation can be a source of beneficial genetic variation , or it can be neutral or harmful in effect . in these embodiments , the library of mutants may be created without necessarily knowing in advance whether any of the mutants will have the desired characteristics . the library of mutants or variants may be created in any of a number of ways . for example , the library of mutants could be created by procedures such as , but not limited to , error - prone polymerase chain reaction (\u201c error - prone pcr \u201d), gene shuffling , and other like procedures . in one embodiment , error - prone pcr may be employed to create the library of mutant genes . error - prone pcr , as compared to pcr , has a relatively high rate of mutation . in other embodiments , the library of mutants may be created by a gene shuffling process . in the case of gene shuffling , a library of variants is created by recombining two or more parent genes . the recombined gene sequences may or may not yield functional enzymes . however , the functionality of the enzymes will be tested during the screening procedure . more importantly , the gene - shuffled library of variants will yield a suitable genetic diversity . fig5 shows a flow diagram of a directed evolution procedure employing a gene - shuffling process for creating a library of mutants . after at least a portion of the library of mutants has been created or assembled , the example embodiment in fig2 involves inserting each of the mutated genes of the library of mutants into separate expression vectors . generally , a gene may not be transferred directly from its original or source organism to a host organism . one way , however , to introduce a mutated gene into a host organism is to first introduce a gene into a vector . a vector is able to carry the gene into a host organism . accordingly , at this point in the process of an example embodiment , each of the mutated genes may be inserted into an expression vector . in the example embodiment of fig2 each of the library of mutated genes which have been inserted into separate expression vectors are inserted into separate host organisms . the host organisms may be , for example , rapidly reproducing microorganisms which might be able to duplicate the recombined or mutated gene in large quantities . some examples of suitable host organisms include e . coli , a . niger , and the like . those skilled in the art will understand that other suitable host organisms are also available . in an example embodiment , e . coli may be employed as the host bacteria . in the example embodiment , once each of the library of mutants ( in expression vectors ) have been introduced into host organisms or bacteria , then each of the host organisms or bacteria may be placed into separate cells of a plate or tray . within these separate cells , colonies of each of the host organisms or bacteria may be grown using any conventional growth medium . while a plate or tray with separate cells is used in the example embodiment , any other suitable holder or receptacle in which the host organisms or bacteria could grow would also work . for example , in another embodiment , each of the host organisms or bacteria could be placed in their own separate plates or trays . once colonies of the host organisms or bacteria have grown , a screening procedure is employed in the example embodiment . in the example embodiment , the screening procedure is illustrated in fig3 . initially , the screening procedure involves testing for glucose oxidase . a given colony may not necessarily yield active glucose oxidase following the gene mutation , the injection into the bacteria , and the growth process . accordingly , the example embodiment includes determining whether the mutated genes that have been growing in the host organisms or bacteria yield active glucose oxidase . the test to determine whether a given colony contains active glucose oxidase may be conducted in any of a variety of ways . in one embodiment , the test for whether active glucose oxidase is present in a given colony comprises an assay which tests the production of peroxide . peroxide is generated upon glucose oxidase reaction with glucose . in one embodiment , leuco - crystal - violet , a substrate that changes color in the presence of active peroxide , is employed . however , in other embodiments , other substances may also be used such as , but not limited to , aminoantipyrine , and the like . in other embodiments , other methods can be used to test for the presence of active glucose oxidase . for example , the presence or absence of active glucose oxidase may be ascertainable by checking for fluorescence . the more fluorescent a given colony is , the more likely it is that it contains active glucose oxidase . those skilled in the art will appreciate that further methods to test for the presence of glucose oxidase can be employed in other embodiments without deviating from the scope or spirit of the invention . as illustrated in fig3 if it is determined that a given colony does not contain active glucose oxidase , then the sample in that colony will not be acceptable because a goal of the process is to formulate a peroxide resistant glucose oxidase . accordingly , in the example embodiment , for colonies in which active glucose oxidase is present , then the process proceeds to the next step in the screening procedure . for those colonies in which active glucose oxidase is not present , the process in concluded . as illustrated in fig2 the screening procedure in the example embodiment next involves determining whether the active glucose oxidase in the colonies that passed the first test in the screening procedure has peroxide - resistant properties . in the example embodiment , this portion of the screening procedure involves first incubating each remaining colony in peroxide . this may be done , for example , by placing a suitable amount of peroxide into the cells of the tray in which the colonies were grown . other embodiments may introduce suitable amounts of peroxide to the various colonies other ways . for example , the peroxide may be introduced to the various colonies in separate trays or other receptacles . after each of the remaining colonies has been incubated sufficiently with peroxide , the screening process then involves checking again for glucose oxidase activity . specifically , after the peroxide incubation process , each colony may be tested for active glucose oxidase in similar ways as described above . accordingly , after each of the remaining colonies has been incubated in peroxide , they may again be tested for glucose oxidase by , for example , using leuco - crystal - violet , a substrate which changes color in the presence of glucose oxidase . other embodiments could use a different means for testing for active glucose oxidase without straying from the scope or spirit of the invention . similarly , in other embodiments , the colonies could be incubated in peroxide and then tested for glucose oxidase activity one colony at a time or more than one colony at a time . in other words , it is not important to the invention that all colonies first be incubated in peroxide before any of the them can be tested for glucose oxidase . in the example embodiment , if any of the remaining colonies tested negative for active glucose oxidase after the peroxide incubation process , then they may be deemed not acceptable . the colonies that still have active glucose oxidase , after being incubated in peroxide , may exhibit a desirable peroxide - resistive characteristic . as illustrated in fig2 for the colonies that may exhibit the desirable peroxide - resistive characteristics , the screening procedure proceeds to the next step of testing functionality . the screening procedure next involves determining whether a given glucose oxidase enzyme possesses the desired functionality . thus , in embodiments in which the enzyme is being prepared for a biosensor , the procedure may involve testing whether a given glucose oxidase enzyme will work in a sensing device . in the example embodiment , this part of the screening procedure generally requires that the glucose oxidase be extracted from each of the remaining colonies . in the example embodiment , glucose oxidase may be extracted from the colonies using a purification column . those skilled in the art will appreciate that there are other procedures available for extracting the glucose oxidase from the colonies for other embodiments of the invention . in another embodiment , the process of assessing a given glucose oxidase enzyme &# 39 ; s functionality may proceed as follows . first , cell lysis , or the removal of the protein from the source , may be achieved by a gentle grinding in a homogenizer . it can also be done by gentle disruption via sonication . other embodiments might employ other means for removing the protein from the source . next , the cell components may be subject to fractionation using centrifugation techniques and then differential solubility . the protein may subsequently be purified using standard chromatography methods . next , the extracted protein may be characterized . this may be done by measuring the activity and concentration of the extract . once the enzyme has been sufficiently isolated and sufficiently concentrated , then it may be immobilized and placed into a sensor . the sensor may then be introduced into an accelerated test environment to determine whether the particular enzyme is indeed functional or is suitable for use in a sensing device . if the results of the test with the enzyme in the sensor are satisfactory , then the testing can stop . this test may be repeated with every colony that exhibited peroxide resistant glucose oxidase after the incubation period . in other embodiments , this test could be done on a subset of those colonies depending on other factors or characteristics . if a satisfactory glucose oxidase enzyme has not been identified after the screening procedure , then , in the embodiment illustrated in fig2 the process may continue by creating another generation of mutated genes . in the example embodiment in fig2 the entire cycle may be repeated as many times as desired . another embodiment of the process of formulating an enzyme with peroxide - resistive properties is illustrated at fig4 . the example embodiment illustrated at fig4 employs a forced mutation process . in this embodiment , instead of utilizing pcr or gene shuffling , mutations may be created by exposing organisms to harsh environments . the embodiment in fig4 first involves obtaining an organism , such as a . niger , penecillium , e . coli , or any other suitable organism . since this embodiment will ultimately create a library of mutants as discussed above , the organism may be placed in multiple cells of a plate or tray . other embodiments could employ other kinds of holders or receptacles in which to grow the organisms so long as the organisms are placed in separate colonies . another embodiment of the invention may use only a single cell or colony . next , this embodiment involves introducing a growth medium to each cell holding some of the organism . the growth medium may be any conventional growth medium such that the organisms may be sustained . the embodiment in fig4 next involves altering the environments of each of the separated organisms . in an embodiment in which the goal is to formulate a glucose oxidase enzyme with an enhanced peroxide resistance , the organisms &# 39 ; environments may be altered by adding a suitable amount of peroxide to each colony . in the example embodiment , the introduction of peroxide to the organisms &# 39 ; environments is done very gradually . in other embodiments , the introduction of peroxide to the organism &# 39 ; s environment may be more abrupt . the embodiment in fig4 next involves a screening procedure . after peroxide has been added to the environments of the various colonies , the screening procedure may be employed to determine which of the colonies are still active . in this embodiment , the test discussed above may be employed for determining whether glucose oxidase in each of the colonies remains active . other embodiments may employ other tests for determining whether a given colony contains active glucose oxidase . at this point in the process , an assessment may be made as to whether the number of colonies with active glucose oxidase is such that the process may proceed to testing the glucose oxidase in sensing devices . whether the number of remaining colonies is workable may depend on many factors and will vary for different embodiments of the invention . if a determination is made that there are too many remaining colonies to proceed to testing in sensing devices , then the environment may be made harsher by gradually adding more peroxide . in this embodiment , by repeating this cycle as many times as necessary , the environment may be continually and gradually made harsher until only a workable number of viable or active colonies remain . in the example embodiment in fig4 once the process yields a workable number of remaining colonies with active glucose oxidase , then the process may proceed to testing the glucose oxidase in sensing devices to assess functionality . the remaining colonies , which may possess the desirable peroxide resistant properties , may be tested for functionality as discussed above . in the example embodiment , this testing may be done by extracting glucose oxidase from the enzymes , incorporating the glucose oxidase in a sensor , and then effecting an accelerated test on the sensor to ascertain the functionality of the enzyme . the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive of the invention . the scope of the invention is indicated by the appended claims , rather than the foregoing description . all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .", "category": "General tagging of new or cross-sectional technology"}
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Does the patent belong in this category?
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ae3ff012c49ee98223f96614a8c900c754b0e3e61acc7f720dfc4e4c3ab492b9
| 0.087402 | 0.055908 | 0.792969 | 0.117676 | 0.371094 | 0.038574 |
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Chemistry; Metallurgy"}
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{"category": "Human Necessities", "patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system ."}
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Does the category match the content of the patent?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.028442 | 0.001137 | 0.098145 | 0.000805 | 0.074707 | 0.002182 |
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Chemistry; Metallurgy"}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Performing Operations; Transporting"}
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Is the categorization of this patent accurate?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.002884 | 0.00383 | 0.103516 | 0.049561 | 0.08252 | 0.038574 |
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{"category": "Chemistry; Metallurgy", "patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system ."}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Textiles; Paper"}
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Is the patent correctly categorized?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.066406 | 0.000418 | 0.457031 | 0.010315 | 0.355469 | 0.010986 |
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Chemistry; Metallurgy"}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Fixed Constructions"}
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Is the categorization of this patent accurate?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.002884 | 0.00885 | 0.103516 | 0.028442 | 0.08252 | 0.057373 |
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Chemistry; Metallurgy"}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Does the category match the content of the patent?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.031982 | 0.000203 | 0.098145 | 0.000778 | 0.074707 | 0.003281 |
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{"category": "Chemistry; Metallurgy", "patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system ."}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Physics"}
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Does the category match the content of the patent?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.024414 | 0.037842 | 0.22168 | 0.060059 | 0.175781 | 0.083984 |
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Chemistry; Metallurgy"}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "Electricity"}
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Is the patent correctly categorized?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.002884 | 0.000607 | 0.115723 | 0.008057 | 0.079102 | 0.013611 |
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{"category": "Chemistry; Metallurgy", "patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system ."}
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{"patent": "the method for improving productivity and process stability in a styrene preparation process system using multiple reactors connected in series according to the present invention , is characterized in that the feed containing steam and ethylbenzene , and ultrahigh temperature steam diverge and then are separately injected into a point after an adiabatic reactor of the front part of the system or a point before an adiabatic reactor of the rear part of the system . in the styrene monomer manufacturing system according to the present invention , the additional adiabatic reactor at the rear part of the system generally has a volume 2 - 5 times greater than that of the adiabatic reactor of the front part of the system , in order to maximize the productivity . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the feed containing ethylbenzene and steam , based on the total amount of being fed to the reaction system , diverge . in the styrene monomer manufacturing system according to the present invention , 15 - 20 vol % of the ultrahigh temperature steam , based on the total amount of being fed to the reaction system , diverge . the flow rate for divergence of the feed is not specifically limited , however the degree of effect obtained may be varied according to an increase or decrease in the flow rate of divergence . further , in view of the prevention of fluidization of catalyst particles filled in an adiabatic reactor and the reactor capacity , the range of 15 - 20 vol % is preferred . the method for improving productivity and process stability in styrene manufacturing process according to the present invention is further illustrated with reference to the drawings . hereinafter , the present invention is illustrated in detail with an embodiment of a conventional reaction system wherein 3 reactors are connected in series after extension of the system in view of the cost - effectiveness of the reaction system , as shown in the attached drawings , however the system illustrated in the drawings is only a preferred example of the present invention , and does not limit the scope of the present invention . therefore , the present invention may be applied to any systems having multiple reactors connected in series without being limited to the system having 3 reactors connected in series . one embodiment of the method for improving productivity and process stability in a styrene manufacturing system having multiple adiabatic reactors connected in series according to the present invention is disclosed in fig2 a - 2 e , in which divergence and injection of the feed material in a conventional styrene manufacturing system as shown in fig1 are carried out at the point as indicated in fig2 a - 2 e so as to manufacture styrene monomers . fig1 shows a conventional styrene manufacturing system in which two adiabatic reactors r - 1 and r - 2 are connected in series and an additional reactor r - 3 which has a volume 2 - 5 times greater than that of r - 1 and r - 2 is further added to the rear part of the system , without any divergence of the feed . in fig1 , the feed containing ethylbenzene and steam is fed to the heat exchanger hx - 3 at 200 - 250 \u00b0 c ., and vaporized in hx - 3 as a gas having a temperature of about 400 - 500 \u00b0 c . the feed with an elevated temperature is mixed with ultrahigh temperature steam heated in the furnace f - 1 , resulting in further temperature elevation to about 600 - 650 , and then injected to the reactor r - 1 . since the styrene manufacturing process is a great endothermic reaction , the temperature of the reactants is dropped to around 540 - 590 \u00b0 c . as passing through the reactor r - 1 . the temperature of the reactants discharged from the reactor r - 1 is elevated to about 600 - 650 \u00b0 c . in hx - 1 through heat exchange with ultrahigh temperature steam heated in the furnace f - 2 , and injected into the reactor r - 2 . based on the same principle , the temperature of the reactants discharged from the reactor r - 2 is again elevated to about 600 - 650 \u00b0 c . in hx - 2 through heat exchange with the ultrahigh temperature steam heated in the furnace f - 3 , and injected to the reactor r - 3 , finally resulting in a hot styrene product having a temperature of about 540 \u02dc 590 \u00b0 c . the hot styrene product is subjected to heat exchange with the feed containing ethylbenzene and steam in hx - 3 , and thus the temperature drops to around 350 - 400 \u00b0 c . the raw materials , i . e . ethylbenzene and steam fed to hx - 3 , as shown in fig2 a - 2 e which show the improved process according to the present invention , may diverge at the point a or point b . the amount ( flow rate ) of divergence is 15 - 20 vol % of the total amount of the raw materials fed to the system . the ultrahigh temperature steam obtained from the furnace f - 2 may diverge at the point c , d or e , and the divergence amount thereof is 15 - 20 vol % of the total amount of steam fed to the furnace f - 2 . the diverged feed containing ethylbenzene and steam , and the diverged ultrahigh temperature steam are mixed together and injected at the point p ( after the reactor of the front part of the system ) or the point q ( before the reactor of the rear part of the system ) into the reaction system . although the divergence of the feed containing ethylbenzene and steam may be carried out at the point a or b , the point a is preferred . since the temperature at the point b ( around 150 - 250 \u00b0 c .) is around 300 - 350 \u00b0 c . lower than the temperature at the point a ( around 450 \u02dc 550 \u00b0 c . ), when using the point b , hpt of f - 3 is significantly increased to around 200 - 230 \u00b0 c . the divergence amount of the feed is not specifically limited according to the present invention , however the degree of effect obtained may be varied according to an increase or decrease in the divergence amount . however , when the flow rate fed to the reactor r - 1 is reduced by 15 - 20 vol %, fluidization of catalyst particles may be significantly reduced in r - 1 and r - 2 reactors which have a small capacity as well as the inner wall surface area , therefore the above range is preferably used . in the meantime , in the reactor r - 3 , which has greater capacity than the reactor r - 1 or r - 2 , as well as greater inner all surface area , the fluidization of catalyst particles related with the total flow rate is not a big problem . the divergence of ultrahigh temperature steam discharged from the furnaces ( f - 1 , f - 2 and f - 3 ) may be carried out at the point c , d or e . assuming the effect is constant , the point c only directly affects hpt of f - 1 ; the point d directly affects hpt of f - 1 and f - 3 ; and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . therefore , the point c is the best for the divergence point . in the above , the expression \u2018 directly affects \u2019 means a reduction in heat supply or heat exchange capability due to reduction in the flow rate caused by the divergence . such reduced capability results in direct increase in hpt . the ratio of each divergence amount of the ultrahigh temperature steam and the feed containing ethylbenezene and steam is not specifically limited , however for maintaining the suitable catalyst activity and preventing the polymerization of the resulted product styrene monomers , the same ratio , for example 15 - 20 vol % may be used . the diverged feed containing ethylbenzene and steam and the diverged ultrahigh temperature steam may be injected at the point p or point q into the reaction system as shown in fig2 a - 2 e . at this time , the diverged ultrahigh temperature steam and the diverged feed containing ethylbenzene and steam should be mixed together and injected at one point of the system . when they are injected separately to other points of the system , significant change in steam hydrocarbon ratio ( shr ), i . e . the ratio between the amount of steam and hydrocarbon occurs , which may cause styrene polymerization , resulting in decrease in selectivity , and further steam and hydrocarbon may not be suitably mixed together . since injection at the point q have a small influence on hpt of the furnaces ( f - 1 , f - 2 and f - 3 ), it is preferred as compared to the injection at the point p . however , when the hpt of f - 3 is sufficiently lower , for example more than 30 \u00b0 c ., than the limitation temperature , i . e . interlock temperature , the point p may be used . in this case , the selection of the point p or q may be determined by workability in view of space , position or material of the system . fig3 shows the structure of an adiabatic reactor used in a styrene manufacturing system . fig4 shows the catalyst bed inside the adiabatic reactor of fig3 , wherein the catalyst bed is charged inside the adiabatic reactor in the form of a cylinder and supported by a metal screen in the form of a net . as shown in fig3 , reactants for the styrene manufacture flow into the bottom of the adiabatic reactor , pass inside the reactor contacting and reacting with the inner wall of the catalyst bed , and are discharged to the top of the reactor . as the gas flow passes by the inner wall of the catalyst bed at a high speed , it pressurizes the catalyst bed and the screen . when the pressure is more than a certain degree , fluidization of catalyst particles occurs , which causes abrasion and destruction of the catalyst particles , resulting in a decrease in catalyst performance . further , the pressure gradient is increased in the catalyst bed , leading to a further increase in the load to the compressor at the end part . the resulting increase in overall reaction pressure consequently has disadvantageous effects on the reaction system . moreover , the pressure applied to the catalyst bed also affects the screen , causing bending thereof and thus decrease in the life of the catalyst bed . since the pressure applied to the catalyst bed is in proportion with the linear velocity of fluid , it is necessary to reduce the linear velocity of fluid , which can be achieved by reducing the amount fed to the system or increasing the inner side wall area of the catalyst bed as shown in fig4 . since it is not possible to modify the catalyst bed once filled in a reactor , the only possible effective method for reducing the pressure by adjusting the operation condition may be a reduction of the amount fed to the system . however , by installing an additional reactor in order to increase productivity , an increase in the total flow rate occurs which may cause problems such as decrease in catalyst performance , increase in reaction pressure and screen bending . moreover , when the amount of ethylbenzene fed to the reactor is increased , the reaction performance , i . e . the ethylbenzene conversion rate is accordingly decreased . therefore , changes in the styrene production amount which is estimated by the equation ( flow rate of ethylbenzene )\u00d7( conversion rate ) should be taken into consideration . according to the method of the present invention , it is possible to prevent problems such as decrease in catalyst performance , increase in reaction pressure and bending of a screen , thereby significantly improving productivity and process stability in styrene monomer manufacturing system , in spite of increase in flow rate of the feed and steam according to further establishment of a reactor , by divergence of the feed and steam fed to the system and injection thereof again into the system . fig1 schematically represents a reaction system of a conventional styrene manufacturing process in which 3 adiabatic reactors are connected in series , in which each r - 1 , r - 2 and r - 3 is an adiabatic reactor ; each hx - 1 , hx - 2 and hx - 3 is a heat exchanger ; f - 1 , f - 2 and f - 3 is a furnace . fig2 a - 2 e show improved styrene manufacturing process proposed by the present invention , wherein the dotted lines represent the portion modified by the present invention . in the figures , each point a and point b is a point where the raw material ethylbenzene and steam may diverge ; each point c , point d and point e is a point where the ultrahigh temperature steam discharged from the furnace may diverge ; and each point p and point q is a point where the raw materials and the ultrahigh temperature steam diverged above may be injected . fig2 a shows divergence at the point a and point c and then injection at the point q ; fig2 b shows divergence at the point b and point c and then injection at the point q ; fig2 c shows divergence at the point a and point c and then injection at the point p ; fig2 d show based on the total amount of being fed to the reaction systems divergence at the point a and the point e and then injection at the point q ; fig2 e shows divergence at the point a and point d and then injection at the point q . fig3 shows an adiabatic reactor conventionally used in styrene manufacturing , together with the stream of reactants flowing to the direction of the arrows . the shaded rectangles inside the reactor represent the catalyst beds which are filled in a screen having a cylindrical form . fig4 shows the structure of the catalyst bed constructed in the form of a cylinder . the inner wall surface area of the catalyst bed is the surface of the wall inside the cylinder which contacts with the reactants fed into the reactor . hereinafter , the effect of the present invention is illustrated through the following examples . in all of the following examples , the amount of divergence and the amount of styrene produced are constantly maintained , thus only fact to be considered is hpt . although a problem related with fluidization of catalyst particles is improved and a problem related with hpt do not occur according to the method of the present invention which includes divergence of the feed and injection thereof at a certain point of the system , it cannot be regarded to be significant if the method involves a decrease in production amount . therefore , comparison of the effects between the examples should be made on the premise of the same production amount and thus the examples are estimated based on the same amount of divergence and production . since such estimation of the production amount cannot be tested in the real plant , a simulator ( 1 st principle model ) was used for the estimation in the present examples . further , hpt value was also obtained by the simulator . the estimation obtained by the simulator was made by adjusting parameters according to operation data practiced in the real plant , and thus had superior precision in estimation . for obtaining the constant production amount of styrene with a given amount of divergence , the inlet temperature of a reactor should be modified so as to further modify the reaction performance , i . e . the conversion rate of ethylbenzene . for this purpose of obtaining the constant production amount of styrene , only the inlet temperature of the reactor r - 3 was modified in the following examples . the modification in inlet temperature of r - 3 directly affects to hpt of f - 3 , after all . therefore , the temperature change in hpt may be a proper indicator reflecting the effects of the divergence and injection of the feed according to the present invention , in which the effects related to energy balance as well as reaction performance . in the examples , the reactor r - 3 is selected only because of its greater volume , and although other reactor is selected for changing the conversion rate , the same tendency in results is expected . general operation conditions used in conventional styrene manufacturing plant were used . the feed containing ethylbenzene and steam diverged at the point a and the amount thereof was 17 . 0 vol % of the total amount of the feed being fed . the ultrahigh temperature steam was possible to diverge at the point c , d or e as shown in fig2 a - 2 b , with the amount of 17 . 0 vol %. the divergence at the point c is considered to be most advantageous in theory , since the point c directly affects hpt of f - 1 with same degree of effect , although the point d directly affects hpt of f - 1 and f - 3 , and the point e directly affects hpt of f - 1 , f - 2 and f - 3 . in the above , the \u2018 directly affects \u2019 means reduction in heat supply or heat exchange capability due to reduction in the feed amount caused by the divergence . such reduced capability results in direct increase in hpt . the tendency and the degree of temperature change was estimated and compared through simulation . the case 1 in which only ultrahigh temperature steam diverged at the amount of 17 vol %, and the case 2 in which the feed containing ethylbenzene and steam diverged at the amount of 17 vol % were analyzed , in which the changes in hpt of f - 1 , f - 2 and f - 3 according to 3 different point of divergence were shown in the following table 1 . as seen from the simulation results of the above table 1 , although the 3 different divergence points did not showed big difference in the effects on hpt of f - 1 , the point c showed the least effect on hpt of f - 2 and f - 3 . therefore , it was confirmed that the point c was the optimal position for divergence of ultrahigh temperature steam . the point p or point q in fig2 a - 2 e is the point for possibly injecting the ultrahigh temperature steam , and the raw materials , i . e . ethylbenzene and steam diverged . it is difficult to determine which point between the point p and point q is more advantageous , theoretically . for selecting the more preferred injection point , the different effects of the injection point p and point q on hpt of f - 1 , f - 2 and f - 3 ( i . e ., by the equation of ( hpt at the position p - hpt at the position q )) were simulated and compared , with a given divergence point of the point c for ultrahigh temperature steam . the results were summarized in the following table 2 . from the results of table 2 , although the injection point of the point p or point q only had small influence on hpt of f - 3 , the point q was more preferred . however , as seen from the above table 2 , since just small difference in hpt of f - 3 is present , it can be determined that the divergence point has more influence than the injection point , and since the difference between the point p and point q is not so much , the point p may be used , when hpt of f - 3 is sufficiently low as compared to the interlock temperature of the system . according to the present invention , it is possible to improve productivity and process stability in styrene monomer manufacturing system having multiple reactors connected in series due to the improved method including divergence of the feed and injection thereof to the reaction system . the method according to the present invention is particularly effective when the reactors in the latter part of the system have larger volume than the reactors in the front part of the system .", "category": "General tagging of new or cross-sectional technology"}
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Is the categorization of this patent accurate?
| 0.25 |
b396b8f02e076ce4ae931abf1957b0a948b0d0ebe1931a0f66a160703b9275eb
| 0.037354 | 0.035645 | 0.212891 | 0.167969 | 0.200195 | 0.111328 |
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{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Human Necessities"}
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{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Performing Operations; Transporting"}
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Is the categorization of this patent accurate?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.000473 | 0.026001 | 0.026001 | 0.235352 | 0.053467 | 0.177734 |
null |
{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Human Necessities"}
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{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Chemistry; Metallurgy"}
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Is the patent correctly categorized?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.000881 | 0.001205 | 0.007355 | 0.030273 | 0.053467 | 0.034668 |
null |
{"category": "Human Necessities", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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{"category": "Textiles; Paper", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.006104 | 0.007355 | 0.00592 | 0.001503 | 0.021606 | 0.027588 |
null |
{"category": "Human Necessities", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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{"category": "Fixed Constructions", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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Does the category match the content of the patent?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.02124 | 0.04541 | 0.005737 | 0.245117 | 0.020386 | 0.05835 |
null |
{"category": "Human Necessities", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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{"category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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Is the categorization of this patent accurate?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.013611 | 0.012024 | 0.011353 | 0.00592 | 0.006104 | 0.062988 |
null |
{"category": "Human Necessities", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Physics"}
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Is the categorization of this patent accurate?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.013611 | 0.004333 | 0.011353 | 0.039063 | 0.0065 | 0.117676 |
null |
{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Human Necessities"}
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{"category": "Electricity", "patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims ."}
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Is the patent correctly categorized?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.000881 | 0.004059 | 0.007355 | 0.001701 | 0.053467 | 0.005371 |
null |
{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "Human Necessities"}
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{"patent": "the present invention is described in the following so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention . the present invention may also be implemented and applied according to other embodiments , and the details may be modified based on different views and applications without departing from the spirit of the invention . fig3 a to 3 d depict a first preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the kneaded batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into an oval - shaped batter 300 as depicted in fig3 a . thereafter , an edible type of oil is applied to the surface of the center portion of the oval - shaped batter to form an oil - layer region 310 . filtered water is then sprayed by a spray nozzle on the surface of the periphery of the oval - shaped batter surface 300 to form an even water - moisturizing region 330 as shown by fig3 b . subsequently , the oval - shaped batter is folded by turning the oil layer region inwardly to form a folded batter layer 300 \u2032 having a hemispherical shape . then , referring to fig3 c , the folded batter layer 300 \u2032 is kneaded by machinery along the edge shown by the vertical arrows a , avoiding the center portion having an oil layer region 310 , to form an edge having a water - moisturizing region 330 , thereby forming a semi - finished flour - yeasted packaging container . then , the semi - finished flour - yeasted packaging container is placed into a yeast tank to undergo a yeast fermentation process for twenty to forty minutes , followed by placement in a steaming cage to steam for about fifteen minutes at a temperature of about 90 degrees . lastly , as shown by fig3 d , the packaging container is cut along the folding line 350 to form an opening 370 . in that the center portion of the folded batter layer 300 \u2032 is formed with an oil layer region and is not pressed during kneading after the batter is folded , the center portion of the folded batter layer 300 \u2032 having an oil layer region is not combined and thus has a hollow gap between the upper layer and the lower layer thereof after cooking the semi - finished packaging container by steam . on the other hand , the edge of the folded batter layer between the upper layer and the lower layer thereof is formed with a water - moisturizing area by spraying filtered water thereon and is combined by kneading by machinery , therefore , after cooking the semi - finished packaging container by steam , the edge of the folded batter layer having a water - moisturizing region is combined to form a sealed side 390 as shown in fig4 a . thereafter , after cutting along the folded side , a pocket - shaped container is formed that has only one side thereof formed with an opening 370 , while the remaining edges are sealed to form a hollow portion for packaging fillings therein as shown by fig4 b . in this embodiment , the pocket - shaped container is used as a cover for making a chinese - hamburger , wherein the fillings to be filled into the central hollow portion of the chinese - hamburger such as meat slices , pickled cabbage , peanut powder and the like - can be inserted into the pocket container through the opening 370 . compared to the known batter cover used for making a chinese - hamburger that typically has one closed side with the remaining sides open , the edible pocket container disclosed by the invention is provided with a hollow pocket to contain the fillings therein , making it more convenient to eat or carry . moreover , the pocket container is characterized in that an oil - layer region and a water - moisturizing region are respectively formed at predetermined positions of the batter surface , thereby overcoming the drawback of the prior art that the edible container is not readily applicable to mechanized mass production . fig5 a to 5 d depict a second preferred embodiment of the present invention ; which is made by first kneading a combination of mixed ingredients that includes wheat flour , sugar , oil , powder , yeast , water and likely others to form a smooth and even batter having an appropriate elasticity . next , the batter is put aside and left for about ten to twenty minutes to become loose . then , the batter is cut into a plurality of small batters and each of the plurality of small batters is rolled into a hemisphere - shaped batter 400 , as depicted in fig5 a . thereafter , referring to fig5 b and 5c , an edible type of oil is applied to the surface of the center portion and the non - arc - shaped ( linear ) side 450 of the hemisphere - shaped batters to form an oil - layer region 410 , and filtered water is sprayed by a spray nozzle on the surface 400 of the arc - shaped edges of the hemisphere - shaped batters to form an even water - moisturizing region 430 . subsequently , two identical hemisphere - shaped batters are placed together by facing the oil layer regions thereof to form a superposed batter layer 400 \u2032 retaining the hemispherical shape , as shown in fig5 c . then , the superposed batter layer 400 \u2032 is kneaded by machinery along the arc - shaped edge as indicated by the vertical arrows a , avoiding pressing the center portion having an oil layer region 410 , to form an edge having a water - moisturizing region 430 , thereby forming a semi - finished yeasted flour packaging container . then , the semi - finished yeasted flour packaging container is placed into a yeast tank to undergo a yeast process for twenty to forty minutes , followed by placement of the yeasted flour container in a steaming cage to steam at a temperature of about 90 degrees for about fifteen minutes reviewing , an oil layer region is respectively formed on the inner center portion and the edges of the non - arc - shaped ( linear ) side of the superposed batter layer 400 \u2032 and a water - moisturizing region is formed on the arc - shaped edges thereof . the center portion thereof having an oil - layer is not pressed to combine after the superposed batters are folded by machinery . consequently , after cooking the semi - finished packaging container by steam , the center portion having an oil layer region and the non - arc - shaped side of the superposed batter layer 400 \u2032 are not combined and thus a hollow gap exists between the upper layer and the lower layer thereof . on the other hand , the arc - shaped edge of the superposed batter layer having a water - moisturizing area between the upper layer and the lower layer thereof is kneaded to combine by machinery to form a sealed side 490 as indicated by fig5 d . note that only the periphery of the arc - shaped edge is formed with a water - moisturizing region in this embodiment . also , in addition to the center portion that has an oil - layer region , the non - arc - shaped ( linear ) edges of the hemisphere - shaped superposed batter layers are also formed with an oil - layer region . therefore , after kneading by machinery to combine the hemisphere - shaped superposed batter layers , a yeast fermentation process , and cooking by steam , an edible hemisphere - shaped container is formed with a center hollow pocket that has only one edge formed with an opening 470 without requiring a cutting process while the remaining edges are sealed . besides the hemisphere - shaped pocket container , the method of producing an edible container disclosed by the invention can also produce other pocket containers in a variety of shapes depending on the preferences and applications , such as folding one or superposing two rectangular batter covers to form a square - shaped pocket container , and folding one diamond shaped or superposing two triangular batter covers to form an edible triangular pocket container , and so on . having thus described preferred embodiments of the invention in sufficient detail to enable those skilled in the art to make and use the invention , it will nevertheless be appreciated that numerous variations and modifications of the illustrated embodiment may be made without departing from the spirit of the invention , and it is intended that the invention not be limited by the above description or accompanying drawings , but that it be defined solely in accordance with the appended claims .", "category": "General tagging of new or cross-sectional technology"}
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Is the categorization of this patent accurate?
| 0.25 |
18efe5877cd824b808b9711737406316f14f9dea4b5e4de00104789f66341bb3
| 0.000473 | 0.126953 | 0.026001 | 0.353516 | 0.053467 | 0.195313 |
null |
{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Physics"}
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Human Necessities"}
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Does the category match the content of the patent?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.003281 | 0.001282 | 0.041992 | 0.005737 | 0.095215 | 0.016968 |
null |
{"category": "Physics", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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{"category": "Performing Operations; Transporting", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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Is the patent correctly categorized?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.090332 | 0.539063 | 0.055908 | 0.445313 | 0.167969 | 0.828125 |
null |
{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Physics"}
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{"category": "Chemistry; Metallurgy", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
|
Does the category match the content of the patent?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.003281 | 0.000999 | 0.041992 | 0.002182 | 0.095215 | 0.003479 |
null |
{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Physics"}
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Textiles; Paper"}
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Does the patent belong in this category?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.002884 | 0.004456 | 0.036865 | 0.001244 | 0.109863 | 0.002121 |
null |
{"category": "Physics", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Fixed Constructions"}
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Is the patent correctly categorized?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.087402 | 0.06543 | 0.053467 | 0.10498 | 0.167969 | 0.535156 |
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Physics"}
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
|
Is the category the most suitable category for the given patent?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.000881 | 0.000216 | 0.007568 | 0.000553 | 0.195313 | 0.057373 |
null |
{"category": "Physics", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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{"category": "Electricity", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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Is the patent correctly categorized?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.090332 | 0.013611 | 0.055908 | 0.003601 | 0.167969 | 0.031738 |
null |
{"category": "Physics", "patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein ."}
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{"patent": "[ 0027 ] fig1 shows the steps of a method according to an embodiment for comparing the addresses of potential recipients of goods with at least part of the denied parties listing ( dpl ). the method is performed by the system shown in fig2 . the system of fig2 comprises an order management system 100 , such as the smarts system , including a database 110 for storing shipping and / or billing addresses of individuals and / or companies which have placed orders or which are due to receive orders , and a data input device 120 for entering data using pin yin characters into the database 110 . only one data input device 120 is shown , but in practice there may be multiple such units . the system further includes a second database 130 for storing the english - language dpl . the system further includes a first conversion unit 140 for converting the simplified mandarin data items in the first database 110 into pin yin data items to form a first pin yin database 150 . this process does not erase the database 120 . the system further includes a second conversion unit 160 for converting the english language data in the second database 130 into pin yin data items in a second pin yin database 170 . this process does not erase the second database 130 . finally , the system includes a comparison unit 180 for comparing the pin yin items in the first and second databases 150 , 170 , and an output unit 190 for notifying an operator of the system of any matches between items in the first and second pin yin databases 150 , 170 which are discovered by the comparison unit 180 . the first two steps of the method of fig1 ( i . e . the ones above the dashed line in fig1 ) are the known steps of entering data into the first database 110 of the order management system 100 . specifically , in step 10 users such as inside sales representatives use the data input devices 120 to enter data such as billing and shipping addresses into the order management system 100 . a window presented to the user by the order management system 100 is shown in fig3 . using this window , in step 20 , and helped by user intervention , the order management system 100 converts the input data into simplified mandarin double byte characters , to form items in the first database 110 . when items from the first database 110 are printed out they are in simplified mandarin , as is generally required for use on shipping and invoice documents . fig4 shows an element from the second database , having the whole of the billing and mailing addresses written in double byte simplified mandarin characters . note that the database 110 may contain further items which are not chinese - related , and which are not relevant to the present disclosure . such items , if they are already in the english language , may be compared directly with items ( e . g . non - chinese items ) in the database 130 by known methods . in step 30 , the billing and shipping data which resides in the first database 110 in simplified mandarin double byte form is converted by the first conversion unit 140 into pin yin characters , to form items in the first pin yin database 150 . as noted above , a single simplified mandarin character may correspond to multiple sets of pin yin characters , and these sets of pin yin characters will have different meanings . hence , the first conversion unit 140 generates , for each simplified mandarin item in the first database 110 , all the possible sets of pin yin characters which can be derived from that item , and each of these sets of pin yin characters forms an item in the database 150 . we have determined that this \u201c simplistic \u201d process does not , however , compromise the integrity of the screening process . specifically , the conversion carried out in step 30 by the conversion unit 140 may be performed using a conversion file such as the default copy of the loaded microsoft windows 98 simplified chinese operating system . the default file system location for each install can be found at c :\\ windows \\ system \\ winpy . com of each pc into which this operating system is installed . [ 0037 ] fig5 shows an example of the process of step 30 . the address displayed in the window of fig4 is order no . 4602249011 in the first database , as shown in fig5 ( a ). fig5 ( b ) shows the various ways in which each of the simplified mandarin characters can be converted into pin yin . most only have one pin yin version , but three of them have two pin yin transliterations , of which one is shown shaded . using the table of fig5 ( b ), the string of simplified mandarin characters in converted into a string of pin yin characters . each simplified mandarin character with multiple pin yin representations is converted as one representation followed by the other representation ( s ). this string is shown in fig5 ( c ) by indicating a first pin yin representation for each such mandarin character followed by the other pin yin representation shaded . in step 40 , the chinese addresses in the second database 130 are converted into pin yin by the second conversion unit 160 to form the items of the second pin yin database 160 . note that this conversion process must normally be performed manually by a chinese speaking operator , though the process may in principle also be automated or semi - automated . [ 0040 ] fig6 illustrates the conversion operation . each row corresponds to an entity on the dpl ( labelled pin_yin \u2014 1 up to pin_yin \u2014 9 ). for example , the entity pin_yin \u2014 2 is the \u201c beijing institute of structure and environmental engineering \u201d. the us government dpl includes an address for this entity of \u201c no . 36 wanyuan road beijin china ( prc )\u201d ( this address is labelled \u201c bxa dpl address \u201d in fig6 ). note that the address is a mixture of conventional english words ( e . g . \u201c road \u201d) and pin yin ( e . g . \u201c wanyuan \u201d). in step 40 , the bxa dpl address is converted ( e . g . by an operator ) into a wholly pin yin address . for reference , the corresponding simplified chinese address is shown in the right hand column of fig6 though the generation of this column is not necessary to the present disclosure . while in principle it would be possible to convert all the items in the dpl into pin yin , the present embodiment only converts the addresses of the chinese items in the dpl . for example , \u201c chinese \u201d in this context may be defined as the items which are addresses in the people &# 39 ; s republic of china and optionally other territories . by taking this \u201c simplistic \u201d approach , the number of conversions ( and thus of subsequent comparisons ) is much reduced . in general , this does not reduce the integrity of the screening , since the screening process is based on addresses , and addresses by their nature are not \u201c mobile \u201d. in step 50 , a comparison is performed of the first and second pin yin databases 150 , 170 to determine matches . this done by automatically extracting matches between the pin yin strings in the first database ( e . g . the string shown in fig5 ( c )), and the pin yin strings in the second database ( the \u201c pin yin addresses \u201d column of fig6 . [ 0043 ] fig7 shows a window optionally presented to the user by comparison unit 180 for the user to decide how the match is to be treated . as shown , a possible match has been found between order number 402211081 ( shown in fig4 and 5 , and in the upper part of fig7 ) and entity pin - yin \u2014 4 in the list of fig6 ( shown in the lower part of fig7 ). note that the entity name in the dpl (\u201c beijing aerospace automatic control limited \u201d) is different from the name (\u201c dali furniture ( china ) ltd .\u201d) in which the order was made ; the embodiment has found the match based on the addresses alone . by entering ticks in appropriate option boxes in the window of fig7 and then clicking on \u201c ok \u201d, the user can indicate how the match is to be treated . step 50 may if desired be performed by a dpl compliance department of the organization operating the order management system . the matches can be incorporated into a local dpl , i . e . a list of parties ( not necessarily the same as those on the us government &# 39 ; s dpl ) with which the organization operating the order management system refuses to transact business , at least without a screening operation . the local dpl may be subsequently used to add to an export management system for export compliance screening purposes as well as for the generation of export / shipping documents . thus , steps 30 and 40 have resulted in a common platform ( pin yin ), enabling in step 50 the compliance screening of addresses of china orders . the embodiment may be operated in a batch mode in which a plurality of items in the first database 110 ( e . g . all the chinese items in the first database 110 ) are converted into pin yin items one after another ( e . g . as a continuous sequence ) to form the database 150 , and later each of the converted items in the database 150 are compared ( e . g . one after another ) with the converted items of the second database 170 . alternatively , step 30 may be performed for the items of the first database 110 individually ( for example , whenever a new item is added to the first database 110 ), and step 50 may be performed for the resultant items in the database 150 by comparing the individual converted items with all the converted items of the second pin yin database 170 . if no matches are found , the contents of the database 150 may be discarded . in other words , in this variant of the embodiment , the first pin yin database 150 need not contain at any time more than the number of pin yin items which are derived from a single one of the simplified mandarin items in the database 110 . the comparison in step 50 may be performed as described above . if any matches are found , the output unit 190 is used to notify an operator of the system , who may cancel the corresponding order . alternatively , though less preferably , the order may be cancelled automatically . although illustrative embodiments have been shown and described , a wide range of modification , change and substitution is contemplated in the foregoing disclosure and in some instances , some features of the embodiments may be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein .", "category": "General tagging of new or cross-sectional technology"}
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Is the patent correctly categorized?
| 0.25 |
9974f78ca183947d89999347909747298994f152ea90e75499e799702305103f
| 0.090332 | 0.043945 | 0.055908 | 0.117676 | 0.167969 | 0.148438 |
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Physics"}
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{"category": "Human Necessities", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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Does the patent belong in this category?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.765625 | 0.355469 | 0.945313 | 0.447266 | 0.890625 | 0.597656 |
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Physics"}
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Performing Operations; Transporting"}
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Does the patent belong in this category?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.761719 | 0.753906 | 0.945313 | 0.929688 | 0.890625 | 0.886719 |
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{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Chemistry; Metallurgy"}
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Does the category match the content of the patent?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.878906 | 0.550781 | 0.980469 | 0.855469 | 0.992188 | 0.628906 |
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{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"category": "Textiles; Paper", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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Is the categorization of this patent accurate?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.808594 | 0.621094 | 0.933594 | 0.396484 | 0.84375 | 0.601563 |
null |
{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"category": "Fixed Constructions", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.925781 | 0.621094 | 0.875 | 0.726563 | 0.972656 | 0.597656 |
null |
{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Is the categorization of this patent accurate?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.808594 | 0.302734 | 0.933594 | 0.357422 | 0.84375 | 0.460938 |
null |
{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "Electricity"}
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Is the category the most suitable category for the given patent?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.925781 | 0.636719 | 0.875 | 0.746094 | 0.972656 | 0.675781 |
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{"category": "Physics", "patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power ."}
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{"patent": "the present invention will be described in detail hereinafter with reference to the illustrated embodiments . fig1 is a sectional view showing the arrangement of a principal part of a camera when a line of sight detection apparatus is applied to a single - lens reflex camera according to the first embodiment of the present invention , and fig3 shows the finder field of the single - lens reflex camera shown in fig1 . referring to fig1 a phototaking lens 1 is constituted by two lenses 1a and 1b for the sake of simplicity . however , in practice , the lens 1 is constituted by a larger number of lenses . a main mirror 2 is obliquely inserted into or retracted from a phototaking optical path in correspondence with the observation state and the phototaking state . a sub mirror 3 reflects downward a light beam transmitted through the main mirror 2 . a shutter 4 is arranged behind these mirrors . a photosensitive member 5 comprises a silver halide film or a solid - state image pick - up element such as a ccd , a mos type element , or the like . a focus detection device 6 adopts a known phase difference method , and is constituted by a field lens 6a disposed in the vicinity of the imaging surface , reflection mirrors 6b and 6b , a secondary imaging lens 6d , an aperture 6e , a line sensor 6f consisting of a plurality of ccds ( to be described later ), and the like . the focus detection device 6 shown in fig1 can perform focus detection on a plurality of areas ( three distance measurement point marks 200 to 202 ) in a finder field ( observation screen ) 213 , as shown in fig3 . a focusing plate 7 is disposed on a prospective imaging surface of the phototaking lens 1 , and a pentagonal prism 8 is used for bending the finder optical path . an imaging lens 9 and a photometric sensor 10 are used for measuring the object luminance in the observation screen . the imaging lens 9 defines a conjugate relationship between the focusing plate 7 and the photometric sensor 10 via the reflection optical path in the pentagonal prism 8 . an eyepiece lens 11 is disposed behind the exit surface of the pentagonal prism 8 , and is used for observing the focusing plate 7 by an eye 15 of a photographer . the eyepiece lens 11 comprises , e . g ., a beam splitter 11a comprising a dichroic mirror which transmits visible light therethrough and reflects infrared light . a light - receiving lens 12 is arranged above the eyepiece lens 11 . an area sensor 14 is constituted by two - dimensionally arranging photoelectric conversion element arrays such as ccds . the area sensor 14 is disposed to be conjugate with a position in the vicinity of the iris of the eye 15 of the photographer , which is located at a predetermined position , with respect to the light - receiving lens . the detailed circuit arrangement of the area sensor 14 will be described later . ireds 13 ( 13a to 13d = ired1 to ired4 ) serve as illumination light sources for illuminating the eyeball 15 of the photographer . high - luminance superimposed leds 21 can be visually confirmed even in a bright object . light emitted by each superimposed led 21 is reflected by the main mirror 2 via a light projection prism 22 , and is bent in the vertical direction by micro - prism arrays 7a formed on a display portion of the focusing plate 7 . then , the light reaches the eye 15 of the photographer via the pentagonal roof prism 8 and the eyepiece lens 11 . thus , the micro - prism arrays 7a are formed in frame patterns at positions corresponding to the focus detection areas on the focusing plate 7 , and are respectively illuminated with the corresponding superimposed leds 21 ( led - l1 , led - l2 , led - c , led - r1 , and led - r2 ). as can be seen from the finder field shown in fig3 the distance measurement point marks 200 , 201 , and 202 shine in the finder field 213 to display the focus detection areas ( distance measurement points ) ( this display will be referred to as a superimposed display hereinafter ). a field mask 23 forms the finder field area . an lcd 24 in the finder is used for displaying phototaking information on a portion outside the finder field , and is illuminated with an illumination led ( f - led ) 25 . light transmitted through the lcd 24 in the finder is guided into the finder via a triangular prism 26 , and is displayed on a portion 207 outside the finder field shown in fig3 . the photographer can observe the displayed phototaking information . the phototaking lens 1 includes an aperture 31 , an aperture driving device 32 including an aperture driving circuit 114 ( to be described later ), a lens driving motor 33 , and a lens driving member 34 consisting of , e . g ., a driving gear and - the like . a photocoupler 35 detects the rotation of a pulse plate 36 interlocked with the lens driving member 34 , and supplies the rotation information to a lens focus adjustment circuit 113 . the lens focus adjustment circuit 113 drives the lens driving motor 33 by a predetermined amount on the basis of this rotation information and information of a lens driving amount supplied from the camera side , thereby moving a focusing lens la of the phototaking lens 1 to an in - focus position . mount contacts 37 serve as a known interface between the camera and the lens . fig2 is a block diagram showing the electrical arrangement of the single - lens reflex camera with the above - mentioned arrangement , and the same reference numerals in fig2 denote the same parts as in fig1 . a central processing device ( to be referred to as an mpu hereinafter ) 100 comprises a microcomputer serving as a built - in camera control means of the camera main body . the mpu 100 performs its internal operations on the basis of clocks generated by an oscillator 101 . a clock control circuit 100a determines the operation frequency of the mpu 100 by &# 34 ; not frequency - dividing &# 34 ;, &# 34 ; frequency - dividing to 1 / 2 &# 34 ;, or &# 34 ; frequency - dividing to 1 / 16 &# 34 ; the original oscillation frequency generated by the oscillator 101 in accordance with an internal signal of the mpu 100 . an eeprom 100b is a memory which can store a film counter and other phototaking information . an a / d converter 100c a / d - converts analog signals from a line of sight detection circuit 104 , a focus detection circuit 105 , and the multi - split photometric sensor 10 ( photometric circuit 106 ), as will be described later . the mpu 100 is connected to an led driving circuit 102 , an ired driving circuit 103 , the line of sight detection circuit 104 , the focus detection circuit 105 , the photometric circuit 106 , a shutter control circuit 107 , a motor control circuit 108 , a film running detection circuit 109 , a switch sense circuit 110 , and a liquid crystal display circuit 111 . the mpu 100 exchanges signals with a lens control circuit 112 arranged in the phototaking lens via the mount contacts 37 shown in fig1 . the led driving circuit 102 turns on the superimposed leds 21 in accordance with a signal from the mpu 100 . the ired driving circuit 102 turns on the ireds 13 in accordance with a signal from the mpu 100 . the line of sight detection circuit 104 performs an accumulation operation and a read operation of the area sensor 14 in accordance with a signal from the mpu 100 , and supplies picture element output analog signals of respective picture elements to the mpu 100 . note that the line of sight detection circuit 104 will be described in detail later . the mpu 100 a / d - converts these analog signals using the a / d converter 100c , extracts the respective feature points of the eyeball image required for line of sight detection in accordance with a predetermined algorithm on the basis of each picture element information , as will be described later , and calculates the rotation angle of the eyeball of the photographer on the basis of the positions of the feature points . in the single - lens reflex camera to which this embodiment is applied , the line of sight ( gazing point ), on the finder , of the photographer is extracted by the calculations , one of the three distance measurement points 200 to 202 is selected , and automatic focus detection is performed using the selected distance measurement point . a regulator 115 supplies a power supply voltage to the line of sight detection circuit 104 in accordance with a signal from the mpu 100 , and is controlled to supply the power supply voltage only when the line of sight detection operation is performed . the line sensor 6f comprises a ccd line sensor constituted by three line sensors line - l , line - c , and line - r corresponding to the three distance measurement points 200 to 202 in the screen , as described above . the focus detection circuit 105 performs accumulation control and read control of these sensor portions of the line sensor 6f , and outputs each picture element information to the mpu 100 . the mpu 100 a / d - converts this information , and performs focus detection based on the phase difference detection method . then , the mpu 100 performs focus adjustment of the lens by exchanging signals with the lens control circuit 112 . the photometric circuit 106 outputs the output signal from the photometric sensor 10 to the mpu 100 as a luminance signal in each area in the screen . the mpu 100 a / d - converts the luminance signal , and adjusts an exposure amount of a phototaking operation . the shutter control circuit 107 runs forward and rearward shutter curtains ( mg - 1 and mg - 2 ) in accordance with a signal from the mpu 100 , thus performing an exposure operation . the motor control circuit 108 controls a motor in accordance with a signal from the mpu 100 , thus performing an up / down operation of the main mirror 2 , a shutter charging operation , and a film feeding operation . the film running detection circuit 109 detects if the film is wound up by one frame in a film feeding operation , and supplies a signal to the mpu 100 . a switch sw1 is turned on at the first stroke position of a release button ( not shown ), and is used for starting photometric , af , and line of sight detection operations . a switch sw2 is turned on at the second stroke position of the release button , and is used for starting an exposure operation . signals from these switches sw1 and sw2 , and other operation members ( not shown ) of the camera are detected by the switch sense circuit 110 , and are then supplied to the mpu 100 . the liquid crystal display circuit 111 controls the lcd 24 in the finder and a monitor lcd 42 in accordance with a signal from the mpu 100 . the lens control circuit 112 communicates with the mpu 100 via the lens mount contacts 37 to operate the lens focus detection circuit 113 and the aperture control circuit 114 , thereby controlling the focus adjustment and aperture of the lens . the detailed circuit arrangement and operation of the line of sight detection circuit 104 will be described below with reference to fig4 . the area sensor is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . however , for the sake of simplicity in the description of the circuit , the area sensor illustrated in fig4 has a size of four picture elements in the horizontal direction \u00d7 four picture elements in the vertical direction . in addition to a function of reading the respective picture element outputs of the sensor , the line of sight detection circuit has a function of reading a picture element output maximum value ( peak output ) of a block as one horizontal line of the sensor , and a function of analyzing image information by performing analog processing of the peak output . one photoelectric conversion element comprises a bipolar transistor 203 which accumulates a light charge on its base , and has double emitters . the first emitter of the bipolar transistor is connected to an output line 201 , and the second emitter is connected to an output line 202 . in each element , a capacitor 204 controls the base potential of the bipolar transistor 203 , and a pmos transistor 205 resets the base . mos transistors 206 are used for connecting the corresponding vertical output lines 201 to the ground potential , and a terminal 207 is used for applying a pulse to the gates of the mos transistors 206 . horizontal driving lines 208 control the base potentials of the bipolar transistors 203 via the capacitors 204 to perform a reset / read operation of the picture elements . buffer mos transistors 209 are enabled when an output from a vertical shift register 232 is applied to their gates , and select picture element rows to be driven . a terminal 210 is used for applying a picture element driving pulse . a wiring line 211 is connected to the drains of the pmos transistors 205 at the right and left ends . an emitter follower circuit 212 has an output connected to the wiring line 211 . amos transistor 213 controls the base potential of the emitter follower circuit 212 . a power supply terminal 214 is connected to the drain terminal of the mos transistor 213 . a terminal 215 is used for applying a pulse to the gate of the mos transistor 213 . each of pmos transistors 216 has a drain fixed at a positive potential . a terminal 217 is used for applying a pulse to the gates of the transistors 216 . capacitors c11 , c21 , . . . , c14 , c24 accumulate picture element output potentials output via the vertical output lines 201 , and mos transistors m11 , m21 , . . . , m14 , m24 are used for performing switching operations between the output lines 201 and the capacitors c11 , c21 , . . . , c14 , c24 . terminals 234 and 235 are used for applying pulses to the gates of the transistors m11 , m21 , . . . , m14 , m24 . a horizontal output line 221 has a parasitic capacitance c2 . switch mos transistors m41 , . . . , m44 electrically connect the capacitors c11 , c21 , . . . , c14 , c24 to the horizontal output line 221 when they are selected by an output from a horizontal shift register 231 . a mos transistor m5 is used for connecting the horizontal output line 221 to the ground potential . a terminal 222 is used for applying a pulse to the gate of the transistor m5 . the transistor m5 is connected to a ground level 223 . an amplifier 224 receives the potential on the output line 221 , and has an output terminal 220 . capacitors 225 accumulate picture element output potentials output via the output lines 202 . mos transistors 226 are used for performing switching operations between the output lines 202 and the capacitors 225 . a terminal 227 is used for applying a pulse to the gates of the transistors 226 . an output line 228 supplies the potentials from the capacitors 225 , and has an output terminal 229 . switch mos transistors 230 are selected by an output from a vertical shift register 233 , and sequentially electrically connect the capacitors 225 and the output line 228 . the vertical shift register 232 receives a driving pulse via a terminal 238 . the vertical shift register 233 receives a driving pulse via a terminal 239 . the horizontal shift register 231 receives a driving pulse via a terminal 237 . mos transistors m31 , . . . , m16 directly connect the capacitors c11 , c21 , . . . , c14 , c24 in units of blocks , and a terminal 236 is used for applying a pulse to the gates of these mos transistors . a comparator 241 compares the output from the amplifier 224 with a reference potential vref1 , and the output from the comparator 241 is output from an output terminal 242 . a mos transistor m6 is used for clamping the input to a comparator 243 to the output from the amplifier 224 in response to a pulse signal 240 input to its gate . after application of the pulse signal 240 , a capacitor c3 inputs the potential difference between the clamped output potential of amplifier 224 and that after clamping to the comparator 243 . the potential difference is compared with a reference voltage vref2 , and a comparison result is output from a terminal 244 . the operation of the single - lens reflex camera according to the embodiment of the present invention will be described below with reference to fig5 a to 9 . referring to fig5 a and 5b , when the operation of the camera is started , the mpu 100 detects the state of the switch sw1 , which is turned on at the first stroke position of the release button , in step (# 01 ). as a result , if the switch sw1 is on , the operation frequency of the mpu 100 is set to be 1 / 1 in step (# 02 ), and a &# 34 ; line of sight detection &# 34 ; subroutine is called to the line of sight detection circuit 104 in step (# 03 ). at this time , since the operation frequency is 1 / 1 , the consumption current becomes maximum . the &# 34 ; line of sight detection &# 34 ; subroutine will be described below with reference to fig7 . when the line of sight detection operation is started in step (# 000 ), data are initialized in step (# 001 ). a variable edgcnt is used for counting the number of extracted edges of the boundary between the iris and pupil . variables ip1 , ip2 , jp1 , and jp2 represent the positions of cornea reflection images ( p images ) of the ireds 13a to 13d , and two p images are present in an area of an eyeball reflection image surrounded by a range from ip1 to ip2 in the horizontal direction ( x - axis ) and a range from jp1 to jp2 in the vertical direction ( y - axis ). the area sensor 14 is assumed to have a size of 150 picture elements in the horizontal direction \u00d7 100 picture elements in the vertical direction . thus , the variables ip1 , ip2 , jp1 , and jp2 respectively store central positions ( 75 , 50 ) of the entire sensor as initial values . in step (# 002 ), the ireds 13 for illuminating the eye of the photographer are turned on , and the accumulation operation of the area sensor 14 is performed . fig1 and 11 are timing charts showing the operation of the line of sight detection circuit 104 including the area sensor 14 . the accumulation operation of the area sensor 14 in step (# 002 ) will be described below with reference to fig1 . first , a pulse \u03c6p ( 215 ) changes to low level to set the emitter follower circuit 212 to have a positive output potential . at this time , the potential of the driving line 208 connected to the bases of the pmos transistors 205 is at low level , and the pmos transistors 205 are turned on , thus setting the base potentials of the bipolar transistors 203 in all the picture elements to be equal to the output potential of the emitter follower circuit 212 . the pulse \u03c6p ( 215 ) changes to high level to set the emitter follower circuit 212 to have a gnd ( ground ) output potential , and thereafter , a pulse \u03c6vc ( 207 ) changes to high level to ground the vertical output lines 201 . with this operation , the emitter potentials of the first emitters are supplied to the bipolar transistors 203 of the respective picture elements , thereby lowering their base potentials . furthermore , the vertical shift register 232 is activated by a driving pulse \u03c6v1 ( 238 ) to apply a pulse \u03c6r ( 210 ) to the horizontal driving lines 208 in units of rows . the base potential of each picture element in a row corresponding to the driving line 208 which changes to high level is temporarily raised by capacitor coupling of the capacitor 204 , but lowers since the emitter current of the first emitter flows . when the potential of the line 208 goes low , the base potential of each picture element becomes a minus potential due to the capacitor coupling , and the first emitter - base path is set in a reverse bias state . at the time of the reverse bias state , the ireds 13 are turned on , and the eyeball image of the photographer is projected onto the area sensor 14 . in each picture element , a charge generated by incident light is accumulated on its base , and the base potential rises in correspondence with the accumulated charge amount . after an elapse of a predetermined accumulation time , the ireds 13 are turned off , thus completing the accumulation . referring back to fig7 upon completion of sensor accumulation in step (# 002 ), the flow advances to step (# 003 ) to perform a pre - read operation . the pre - read operation is the important point of this embodiment , and will be described below in two embodiments . the pre - read operation according to the first embodiment of the present invention will be described below with reference to the timing chart of fig1 showing the operation of the line of sight detection circuit 104 . a pulse \u03c6rc ( 217 ) changes to low level to turn on the pmos transistors 216 , thus setting all the horizontal driving lines 208 at high level . at this time , the base potential of each picture element is raised by the capacitor coupling , and its base - emitter potential is set in a forward bias state . as a result , the output values from maximum output picture elements in the respective row appear on the corresponding output lines 202 , and the potentials on the output lines 202 are accumulated on the accumulation capacitors 225 via the mos transistors 226 in response to a pulse \u03c6vt ( 227 ). then , the vertical shift register 233 is activated in response to a pulse \u03c6v2 ( 239 ) to sequentially output the potentials on the capacitors 225 from the output terminal 229 . these signals are a / d - converted by the internal a / d converter 100c of the mpu 100 , and the mpu 100 compares the a / d - converted output values of the maximum output picture elements in the respective horizontal lines with a predetermined discrimination level . referring back to fig7 if at least one a / d - converted value exceeds the predetermined level , it is determined in step (# 004 ) that p images based on the eyeball images of the photographer are present on the area sensor 14 , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if none of the a / d - converted values exceed the predetermined level , no eyeball image is present on the area sensor 14 . that is , it is determined that the photographer does not look into the finder , and the flow advances to step (# 018 ), thus ending the line of sight detection operation . in step (# 009 ), so - called &# 34 ; loop processing &# 34 ; is executed , i . e ., the processing steps in the frame are executed while counting up a loop variable j from 0 to 99 . if it is determined in step (# 010 ) that the y - coordinate falls outside the range from 0 to 99 , it is determined that the loop processing in step (# 009 ) ends , and the flow advances to step (# 015 ). on the other hand , if the y - coordinate falls within the range from 0 to 99 , the flow advances to step (# 011 ), and photoelectric conversion signals in one line in the horizontal direction ( x - axis ) of the area sensor 14 are read . the read operation ( main read ) will be described below with reference to the timing chart in fig1 . the vertical shift register 232 is activated in response to a driving pulse \u03c6v1 ( 238 ), and the first horizontal driving line 208 ( v1 ) changes to high level in response to a pulse \u03c6r ( 210 ). at the same time , the respective picture element outputs of the first line are accumulated on the capacitors c11 , . . . , c14 via the transistors m11 , . . . , m14 in response to a pulse \u03c6t1 ( 234 ). the horizontal shift register 231 is activated by a driving pulse \u03c6h ( 237 ), and the respective picture element outputs of the first line accumulated on the capacitors c11 , . . . , c14 are read from the output terminal 220 by the mpu 100 via the amplifier 224 . upon completion of the processing for the first line , the second horizontal driving line 208 ( v2 ) changes to high level in response to a driving pulse \u03c61 ( 238 ), and respective picture element outputs of the second line are read by the mpu 100 by the similar operations . the same applies to the third and fourth lines . the one - line read operation is executed in the form of a subroutine , and fig8 is a flow chart showing the &# 34 ; one - line read &# 34 ; subroutine . referring to fig8 when this &# 34 ; one - line read &# 34 ; subroutine is called in step (# 100 ), step (# 101 ) is executed . step (# 101 ) and step (# 102 ) in the frame of step (# 101 ) execute the same loop processing as that in step (# 006 ) described above . processing in the frame is executed in step (# 101 ) while counting up a variable k from 0 to 3 , and processing in the frame is executed in step (# 102 ) while counting up a variable i from 0 to 149 . therefore , steps (# 101 ) and (# 102 ) execute so - called &# 34 ; nested &# 34 ; loop processing of the variables k and i . in step (# 103 ) in the loop processing in step (# 102 ), a re - storage operation of array variables im ( i , k ) is performed . in this embodiment , the mpu 100 executes signal processing . in general , the storage capacity of an internal ram ( random access memory ) of a microcomputer is not large enough to simultaneously store all the pieces of picture element information from the area sensor . thus , in this embodiment , only the latest image signals corresponding to five lines in the horizontal direction ( x - axis ) are stored in the internal ram of the microcomputer , and processing for line of sight detection is executed each time signals for one line are read . the execution contents of the double loop processing from steps (# 101 ) to (# 103 ) include an operation for the updating stored image signal data for last five lines so as to read image signals for one new line . more specifically , of the array variables im ( i , k ), the variables im ( i , 0 ) i = 0 to 149 ! represent image data for the oldest line , and the variables im ( i , 4 ) i = 0 to 149 ! represent image data for the latest line . then , data are updated as follows to prepare for storing image signals for a new line in the variables im ( i , 4 ) i = 0 to 149 !. upon completion of the loop processing for updating data in steps (# 101 ) to (# 103 ), loop processing in step (# 104 ) is executed . in the loop processing in step (# 104 ), only signals in a limited area are a / d - converted and stored in the ram , and a minimum value of these image signals is detected while outputting image signals for one line ( 150 picture elements ) in the horizontal direction ( x - axis ) of the area sensor . if it is determined in step (# 105 ) that the value i ( x - coordinate ) falls outside the range from 0 to 149 , the loop processing in step (# 104 ) ends . on the other hand , when the value of the variable i falls within the range from 0 to 149 , the flow advances to step (# 106 ), and the mpu 100 temporarily stores an a / d - converted value adc of each image signal in a variable eyedt . in step (# 107 ), the value eyedt is stored in the corresponding array variable im ( i , 4 ). the variable i is counted up from 0 to 149 in outer loop processing step (# 104 ). steps (# 108 ) and (# 109 ) execute minimum value detection processing of image signals . a variable eyemin holds a minimum value of image signals . if it is determined in step (# 108 ) that eyedt is smaller than eyemin , the flow branches to step (# 109 ), and eyemin is updated by the smaller value eyedt . upon completion of the loop processing in steps (# 104 ) to (# 109 ), i . e ., upon completion of the storage operation of image signals for one new line and the detection operation of the minimum value , the control returns from the &# 34 ; one - line read &# 34 ; subroutine to the main routine in step (# 110 ). referring back to the flow chart in fig7 when the &# 34 ; one - line read &# 34 ; subroutine ends in step (# 011 ), the flow advances to step (# 012 ) to check if the loop variable j in the outer loop processing step (# 009 ) is equal to or larger than 5 . the loop variable j represents the picture element line in the vertical direction ( y - axis ) of the area sensor . in this embodiment , since the number of picture elements of the area sensor is assumed to be &# 34 ; 150 \u00d7 100 &# 34 ;, j is counted up from 0 to 99 . if it is determined in step (# 012 ) that the loop variable j is equal to or larger than 5 , the flow branches to step (# 013 ). this is because when the number of lines of the read image signals becomes equal to or larger than 5 , processing in the vertical direction ( y - axis ) of the area sensor is allowed . in step (# 013 ) as the branch destination , a &# 34 ; p image detection &# 34 ; subroutine is executed . the &# 34 ; p image detection &# 34 ; subroutine is the above - mentioned processing for detecting the positions of the p images , and is executed each time one line in the horizontal direction ( x - axis ) of the area sensor is read . fig9 is a flow chart showing the &# 34 ; p image detection &# 34 ; subroutine . referring to fig9 when the &# 34 ; p image detection &# 34 ; subroutine is called in step (# 200 ), loop processing in step (# 201 ) is executed . in this step , loop processing is performed within the range from i = 0 to 149 . in the loop processing , the position of a p image in image data stored in the array variables im ( i , k )! is searched . if the position of a p image is found , the position on the area sensor is stored . in this embodiment , since two p images are generated , two pieces of position information are stored . in first step (# 202 ) in the loop , it is checked if image data at a predetermined position satisfies a condition as a p image . the condition is as follows : the condition is defined in two directions , i . e ., the horizontal and vertical directions ( x - and y - axes ) while paying attention to the fact that the p image is like a spot image , as has been described above with reference to fig1 . if this condition is satisfied , it is determined that a p image is present at a position ( i , 2 ). as described above , the array variables im ( i , k ) are updated each time one line in the horizontal direction ( x - axis ) of the area sensor is read , and data for a line at the position j in the vertical direction ( y - axis ) are stored in im ( i , 4 ) i = 1 to 149 !. therefore , an address ( i , 2 ) with respect to the variable im corresponds to a position ( i , j - 2 ) on the area sensor . if image data satisfying the p image condition is found in step (# 202 ), the flow branches to step (# 203 ) and the subsequent steps ; otherwise , the outer loop variable i is counted up . in step (# 203 ) and the subsequent steps , processing for determining the presence range ( the range ip1 to ip2 ! in the x - axis direction and the range jp1 to jp2 ! in the y - axis direction of the two p images is performed . in step (# 203 ), the variable i representing the position , in the horizontal direction ( x - axis ), of the area sensor is compared with the variable ip1 . if &# 34 ; i & lt ; ip1 &# 34 ;, the flow branches to step (# 204 ). more specifically , if the position of the variable i is present on the left side of the left p image position ip1 in the horizontal direction , in the presence range of the p image , ip1 is rewritten . in step (# 204 ), the value of the variable i is stored in the variable ip1 , and the position ( j - 2 ) in the vertical direction at that time is stored in the variable jp1 . in steps (# 205 ) and (# 206 ), the right p image position ip2 in the horizontal direction and the position jp2 in the vertical direction in the p image presence range are updated . as described above , in the loop processing in step (# 201 ), upon completion of the processing for one line corresponding to the position i = 0 to 149 in the horizontal direction , the flow advances to step (# 207 ). in step (# 207 ), variables xp1 , xp2 , yp1 , and yp2 to be looked up in image processing are calculated using formulas shown in fig9 . these variables are used for removing pupil edge information generated around the p image positions upon detection of the center of the pupil . upon completion of the processing in step (# 207 ), the control returns from the &# 34 ; p image detection &# 34 ; subroutine to the main routine in step (# 208 ). a description will be continued with reference to the flow chart in fig7 again . upon completion of the &# 34 ; p image detection &# 34 ; subroutine in step (# 013 ), a &# 34 ; pupil edge detection &# 34 ; subroutine is executed in step (# 014 ). the &# 34 ; pupil edge detection &# 34 ; subroutine detects the position of the pupil edge ( the boundary between the iris and pupil ) in the eyeball reflection image . the pupil edge is detected by a predetermined algorithm . however , since this algorithm is not directly related to the gist of this embodiment , a detailed description thereof will be omitted . upon completion of the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 014 ), the loop variable j ( representing the position in the vertical direction , i . e ., the y - coordinate of the area sensor ) in the outer loop processing step (# 009 ) is counted up , and the processing in step (# 010 ) and the subsequent steps is executed until j reaches 99 . if the loop variable j has reached 99 and the read processing of all the picture elements of the area sensor has ended , the flow advances from step (# 009 ) to step (# 015 ). in step (# 015 ), a &# 34 ; pupil designation range setting &# 34 ; subroutine is executed . this subroutine removes false edge points which are generated by various noise components and included in a plurality of edge points detected in the &# 34 ; pupil edge detection &# 34 ; subroutine in step (# 104 ) in addition to those representing the pupil circle ( a circle defined by the boundary between the iris and pupil ). in this subroutine , the coordinates of probable edge points are limited based on the p image position information . however , a detailed description of this subroutine will be omitted here . in step (# 016 ), a &# 34 ; pupil center detection &# 34 ; subroutine is executed . this subroutine estimates the shape of the pupil circle on the basis of the probable pupil edge points so as to obtain the central coordinate , and uses the &# 34 ; method of least squares &# 34 ;. a detailed description of this subroutine will be omitted here . in step (# 017 ), a &# 34 ; line of sight detection &# 34 ; subroutine is executed . the &# 34 ; line of sight detection &# 34 ; subroutine detects the line of sight ( gazing point ) on the basis of the p images and the central position of the pupil circle detected in the above - mentioned processing . basically , as in the above - mentioned prior art , the rotation angle \u03b8 of the eyeball optical axis can be calculated in accordance with formula ( 2 ). referring back to fig5 upon completion of the line of sight detection subroutine in step (# 03 ), the flow advances to step (# 04 ). in step (# 04 ), the power supply of the line of sight detection circuit is turned on , and the operation frequency of the mpu 100 is decreased to 1 / 2 , thus suppressing the consumption current in the subsequent routines . in step (# 03 ) for performing the line of sight detection operation , since a very large amount of calculation processing is generated , a very long time is required for line of sight detection unless the operation frequency of the mpu 100 is maximized . however , since a step other than the line of sight detection operation , e . g ., step (# 05 ) for performing a focus detection operation does not require a large calculation processing amount , unlike in the line of sight detection processing , the operation frequency of the mpu 100 can be lowered to attain power saving . in step (# 05 ), the focus detection operation is performed . this operation is performed based on the known phase difference detection method using the focus detection circuit 105 , as described above . in step (# 06 ), the mpu 100 controls the lens control circuit in accordance with the focusing state detected by the focus detection operation , thus attaining focus adjustment of the lens . in step (# 07 ), since a photometric operation to be executed in the next step (# 08 ) requires a further smaller amount of calculation processing , the operation frequency is decreased to be 1 / 16 . in step (# 08 ), the mpu 100 determines an exposure amount on the basis of luminance information of an object from the photometric circuit 106 . in step (# 09 ), a feeding finish flag indicating whether or not the camera is in a film feeding state is checked . if the flag is 0 , since a continuous feeding operation is being performed currently , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 09 ). on the other hand , if the feeding finish flag is 1 , the flow advances to step (# 10 ) to check if the switch sw2 , which is turned on at the second stroke position of the release button , is on . if the switch sw2 is off , the flow returns to step (# 01 ) to repeat the operations in steps (# 01 ) to (# 10 ). if the feeding finish flag is 1 and the switch sw2 is on , a series of &# 34 ; exposure operations &# 34 ; in steps (# 11 ) to (# 15 ) are started . in step (# 11 ), the main mirror 2 is moved upward prior to the exposure operation , and is retracted from the phototaking optical path . in step (# 12 ), the aperture 31 in the lens 1 is driven via the lens control circuit 112 to have an aperture value based on the determined exposure amount . in step (# 13 ), the shutter is controlled by the shutter control circuit 107 to have a shutter release time ( shutter speed ) based on the determined exposure amount . in step (# 14 ), the main mirror 2 , which was retracted from the phototaking optical path , is moved downward , and is obliquely inserted in the phototaking optical path again . in step (# 15 ), the motor control circuit 108 starts a film feeding operation to wind up the film by one frame , and the feeding finish flag is set to be 0 , thus setting interruption processing . thereafter , the control waits for a film feeding finish signal from the film running detection circuit 109 , and returns to step (# 01 ). the feeding finish interruption routine will be described below with reference to fig6 . when the camera operation is in any one of steps (# 01 ) to (# 09 ), if the film running detection circuit 109 generates a film feeding finish interruption , the flow advances from step (# 20 ) to step (# 21 ). in step (# 21 ), the mpu 100 supplies a signal to the motor control circuit 108 to stop the feeding operation , thus ending the wind - up operation of the film by one frame . in step (# 22 ), the feeding finish flag is set to be 1 , and the flow returns to the main routine in step (# 23 ). as has been described above with reference to the flow charts , when the on state of the release button is held at its first stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, and &# 34 ; photometric operation &# 34 ; are repetitively performed . on the other hand , when the on state of the release button is held at its second stroke position , the &# 34 ; line of sight detection operation &# 34 ;, &# 34 ; focus detection operation &# 34 ;, &# 34 ; photometric operation &# 34 ;, and &# 34 ; exposure operation &# 34 ; are performed . fig1 a and 12b show a change in consumption current when the on state of the release button is held at its first stroke position in the camera operation of this embodiment . when the photographer looks into the finder and p images for line of sight detection exist ( see fig1 a ), since the line of sight detection operation continues for a long period of time and the consumption current is large , the average consumption current in the entire sequence has a value close to the consumption current in the line of sight detection operation . however , when the photographer does not look into the finder , and no p images for line of sight detection exist ( see fig1 b ), since the line of sight detection operation finishes within a short period of time , the average consumption current in the entire sequence lowers very much . as described above , in the first embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from the area sensor 14 and executing sequential processing of the a / d - converted values , the area sensor 14 is divided into blocks in units of horizontal lines , and the output values from maximum output picture elements in the respective lines ( blocks ) are a / d - converted to detect the presence / absence of p images . in this case , if it is detected that the observer does not look into the finder , the line of sight detection operation is suspended . as a result , the time required for operating the mpu 100 at the maximum operation frequency 1 / 1 can be shortened , and the consumption current can be greatly reduced in the entire camera operation . the second embodiment of the pre - read operation in step (# 003 ) will be described below with reference to the timing chart in fig1 . in fig1 , the & lt ; base clamp & gt ;, & lt ; sequential reset & gt ;, and & lt ; accumulation & gt ; operations are the same as those in fig1 . the pre - read operation in fig1 is the same as the main read operation in fig1 in a hardware manner , and signals are read from a terminal 220 in turn by an mpu 100 from the first line . at this time , a comparator 241 compares the picture element of interest with a reference potential vref1 , and if the picture element output is equal to or higher than a predetermined level , an output c1 ( 242 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . when a pulse \u03c6cl ( 240 ) is enabled , the picture element output of the previous picture element is clamped at one terminal of the capacitor c3 , and thereafter , the pulse \u03c6cl ( 240 ) is disabled to read the next picture element output , thereby inputting the difference output from the previous picture element to a comparator 243 . the comparator 243 compares the input difference with a reference potential vref2 , and if a difference picture element output equal to or higher than a predetermined level is found , an output c2 ( 244 ) generates a signal &# 34 ; 1 &# 34 ; in association with the picture element of interest . if both the outputs c1 ( 242 ) and c2 ( 244 ) are &# 34 ; 1 &# 34 ; for the picture element of interest , the picture element is considered to be a p image candidate , since it satisfies the p image detection condition that a picture element is like a spot image having a predetermined luminance level or higher . the method of searching p image candidates on the basis of the output signals c1 ( 242 ) and c2 ( 244 ) from the mpu 100 can be completed within a shorter period of time than the method of obtaining the p images by calculations of the a / d - converted values , as has been described above with reference to fig9 . if it is determined in step (# 004 ) in fig7 that two or more p image candidates are obtained , it is determined that p images exist , and the photographer looks into the finder , and the flow advances to step (# 009 ) and the subsequent steps . on the other hand , if the number of p image candidates is one or fewer , it is determined that the photographer does not look into the finder , and the line of sight detection operation ends in step (# 018 ). the operations in step (# 009 ) and the subsequent steps are the same as those in the first embodiment , and a detailed description thereof will be omitted . as described above , according to the second embodiment , prior to the calculations of the gazing point ( line of sight ) of the observer by a / d - converting respective picture element outputs from an area sensor 14 and executing sequential processing of the a / d - converted values , the feature points of the eyeball image are detected by analog processing simultaneously with the high - speed read operation of the area sensor 14 . if it is detected based on the presence / absence of the feature points that the observer does not look into the finder , the line of sight detection operation is suspended immediately . the first embodiment may erroneously detect that the observer looks into the finder when an image on the area sensor simply has a predetermined luminance level , even through the observer does not actually look into the finder . however , in the second embodiment , although the time required for the pre - read operation is not much shorter than that in the first embodiment , a discrimination probability increases in consideration of the feature point indicating that a p image is a spot image , thus realizing further power saving . the third embodiment of the line of sight detection operation in step (# 03 ) will be described below with reference to the flow chart in fig1 . the same step numbers denote steps that execute the same operations as in fig7 . in the third embodiment , after sensor accumulation (# 002 ), the loop processing in step (# 009 ) and the subsequent steps are executed without performing the pre - read operation (# 003 ) and p image discrimination (# 004 ). upon completion of this loop processing , p image discrimination in step (# 004 ) is performed . if it is determined that no p images formed by the eyeball image of the photographer exist on an area sensor 14 , i . e ., if variables ip1 , ip2 , jp1 , and jp2 indicating the positions of the p images remain set in initial values , since the subsequent line of sight detection operation need not be performed , the flow advances to step (# 018 ), thus ending the line of sight detection subroutine . if the variables ip1 , ip2 , jp1 , and jp2 are updated from the initial values , and it is determined that p images exist , the flow advances to step (# 015 ) and the subsequent steps . as described above , since the third embodiment has a larger number of steps than in the first and second embodiments before discrimination of the presence / absence of p images , the effect of reducing the consumption current and increasing the processing speed slightly lowers . however , since this embodiment does not require any new hardware circuits for the pre - read operation , the effect of the present invention can be attained by modifying only software programs of the conventional circuit , thus providing a merit of a simple arrangement . according to each of the above embodiments , after a line of sight detection sensor , which detects the line of sight by accumulating and reading an eyeball image of the observer , a / d - converting picture element information , and executing sequential processing of the a / d - converted values , and accumulates the eyeball image , the pre - read operation which is completed in a short period of time as compared to the sequential processing is performed , and it is discriminated if the eyeball image of the observer is present . therefore , a line of sight detection apparatus which can systematically attain power saving , e . g ., when the observer does not look into an observation unit in a mode for continuously performing line of sight detection , can be realized . in this embodiment , the ireds 13a to 13d correspond to an illumination means of the present invention , the area sensor 14 corresponds to a light - receiving means of the present invention , a portion for performing the main read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a first signal read processing means of the present invention , and a portion for performing a / d conversion , p image detection , pupil edge detection , and the like attained by the mpu 100 corresponds to a feature point extraction means . a portion for performing the pre - read operation attained by the mpu 100 and the line of sight detection circuit 104 corresponds to a second read processing means of the present invention , and a portion for performing p image discrimination in step (# 004 ) in fig7 by the mpu 100 corresponds to a discrimination means of the present invention . a portion for performing the pre - read operation of the first embodiment corresponds to a means for reading and processing signals associated with respective blocks in claim 4 , and a portion for performing the pre - read operation of the second embodiment corresponds to a means for reading and processing analog - processed second signals in claim 6 . in each of the above embodiments , the present invention is applied to a single - lens reflex camera . however , the present invention may be applied to other cameras such as a lens - shutter camera , a video camera , and the like . furthermore , the present invention may be applied to other optical equipment , other apparatuses , and a constituting unit of other equipment . furthermore , the present invention may be applied to an arrangement as an appropriate combination of the above embodiments or their techniques . as described above , according to the present invention , a peak signal read by a peak read processing means before a line of sight detection operation is a / d - converted , and it is checked based on the a / d - converted value if a purkinje image associated with an eyeball image of an observer is present on a light - receiving means , or the peak signal is analog - processed , and it is checked based on the analog value if a purkinje image associated with an eyeball image of an observer is present on the light - receiving means . if the purkinje image is present on the light - receiving means , since the observer looks into the finder with a high possibility , read processing in units of picture elements of the area sensor is performed , image information associated with the eyeball image of the observer is extracted from the read processing result , and the line of sight of the observer is detected based on the image information . if the purkinje image is not present on the light - receiving means , since the observer does not look into the finder with a high possibility , the line of sight detection operation is suspended . therefore , when the observer does not look into an eyepiece portion with a high possibility , the line of sight detection operation is suspended , thus reducing the consumption power .", "category": "General tagging of new or cross-sectional technology"}
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Does the patent belong in this category?
| 0.25 |
6e947b918cda66c390fc65e20a60ac6370f64e6135380b75548647bac18fdbc8
| 0.9375 | 0.769531 | 0.988281 | 0.921875 | 0.980469 | 0.824219 |
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{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
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{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Performing Operations; Transporting"}
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Does the category match the content of the patent?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.332031 | 0.015442 | 0.546875 | 0.029785 | 0.507813 | 0.08252 |
null |
{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
|
{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Chemistry; Metallurgy"}
|
Is the categorization of this patent accurate?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.200195 | 0.001808 | 0.433594 | 0.040283 | 0.277344 | 0.026001 |
null |
{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
|
{"category": "Textiles; Paper", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
|
Is the categorization of this patent accurate?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.195313 | 0.150391 | 0.433594 | 0.008057 | 0.291016 | 0.041504 |
null |
{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
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{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Fixed Constructions"}
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Does the patent belong in this category?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.3125 | 0.010986 | 0.621094 | 0.019165 | 0.365234 | 0.044678 |
null |
{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Human Necessities"}
|
{"category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
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Does the category match the content of the patent?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.006287 | 0.009399 | 0.017456 | 0.00383 | 0.043945 | 0.066406 |
null |
{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
|
{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Physics"}
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Is the categorization of this patent accurate?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.200195 | 0.001869 | 0.433594 | 0.007568 | 0.291016 | 0.006287 |
null |
{"category": "Human Necessities", "patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps ."}
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{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Electricity"}
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Is the category the most suitable category for the given patent?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.098145 | 0.000123 | 0.115723 | 0.001099 | 0.328125 | 0.000805 |
null |
{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "Human Necessities"}
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{"patent": "embodiments of the present disclosure may provide mosquito - repelling wearables that may be formed of repellent - treated mesh that is soft and breathable as it protects the wearer from insect bites . in embodiments of the present disclosure , the repellent technology used to treat the mesh may tightly bond a permethrin formulation into the actual fibers of the fabric during manufacturing , resulting in effectively , odorless insect protection . permethrin is a chemical that may be used as an insect repellent . it belongs to the family of synthetic chemicals called pyrethroids and functions as a neurotoxin , affecting neuron membranes by prolonging sodium channel activation , and it has been a u . s . environmental protection agency ( epa )- registered chemical for almost 40 years , with an excellent safety record . inclusion of the permethrin formulation into the fibers of the fabric may repel insects , including but not limited to , mosquitoes , ticks , ants , flies , chiggers , and midges ( no - see - ums ). while wearables according to embodiments of the present disclosure have been described as including the permethrin formulation bonded with the mesh , it should be appreciated that other repellent formulations may be utilized without departing from the present disclosure . the repelling nature of wearables according to embodiments of the present disclosure may last through approximately 25 launderings , which is the general expected lifetime of a garment . this life span is well beyond the life of most performance finishes commonly used in the technical - apparel industry . wearables according to embodiments of the present disclosure may be worn by adults and children alike . it should be appreciated that these wearables may be provided in a variety of colors , patterns , and styles , even including camouflage , according to embodiments of the present disclosure . in some embodiments of the present disclosure , these wearables may resemble mosquito netting but are formed of a three - dimensional mesh , similar to the top portion of running shoes ; this mesh may breathe but will reduce the likelihood that a mosquito will penetrate the spongy fabric when worn . in further embodiments of the present disclosure , these wearables are formed of a single - layer repellent - treated mesh , either in place of or in addition to the three - dimensional mesh . it should be appreciated that the three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . these wearables may be worn in warmer climates ; however , there may be embodiments of the present disclosure where heavier clothes may be worn underneath the wearable , such as when the climate is a little cooler but certain insects are still present . there may be further embodiments where more than one layer of repellent - treated mesh may be utilized , again when the climate is a little cooler . embodiments of the present disclosure may provide a wrap jacket ( see fig1 a - 1d ) that is treated with the permethrin repellent formulation , provided by insect shield \u00ae in some instances . this type of jacket may be worn by women , including women that are pregnant and may be more susceptible to diseases such as the zika virus . the jacket may be constructed of repellent - treated mesh that is soft , lightweight , and / or breathable as it helps protect the wearer from insect bites . the repellent within the mesh is tightly bonded into the actual fibers of the fabric , thereby providing built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . the mesh forming this wearable may be soft , breathable and may be stretchy / pliable in nature . the repellent may be effective for approximately 25 launderings . fig1 a - 1d depict different views of mosquito - repelling wrap jackets according to embodiments of the present disclosure . more specifically , fig1 a depicts a front view of a mosquito - repelling wrap jacket according to an embodiment of the present disclosure . in this embodiment , the wrap jacket is shown on a hanger ( i . e ., not being worn ), and this reflects the draping nature of the wrap jacket . while the wrap jacket may be sold in a variety of sizes , it should be appreciated that the draping nature of the wrap jacket may allow for people of differing sizes and shapes to wear it , including pregnant women , such as the wrap jacket depicted in the front view of fig1 b . it also should be appreciated that wrap jackets according to embodiments of the present disclosure may be provided in varying colors , patterns , and styles . fig1 b depicts front and back views of mosquito - repelling wrap jackets as worn according to an embodiment of the present disclosure . in this embodiment , belting mechanisms have been utilized to provide closure for the front of the wrap jacket , and the back view illustrates how the belting mechanism may wrap around the wearer . fig1 c depicts front and back views of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the draping nature of the wrap jacket is visible from the back view . further , one of the front views depicts how the wrap jacket may be drawn over a wearer &# 39 ; s head in some embodiments of the present disclosure to provide additional protection for the wearer &# 39 ; s face , neck and head . however , there may be other embodiments wherein one may wear the wrap jacket and also utilize a scarf or head wrap formed of the repellent - treated mesh as described with respect to the wrap jacket . fig1 d depicts a front / side view of a mosquito - repelling wrap jacket as worn according to an embodiment of the present disclosure . in this embodiment , the wrap jacket has been belted to provide a more flattering silhouette for the wearer and make the wearer &# 39 ; s outfit more fashion - forward . in another embodiment of the present disclosure , a tracksuit ( fig2 a - 2c ) may be constructed of mesh ( i . e ., a single - layer repellent - treated mesh and / or a three - dimensional mesh , which may or may not be repellent - treated ) that is soft and breathable . such a tracksuit may be provided for adults and children alike . by wearing the tracksuit , a human may be protected from insect bites as the repellent within the mesh fabric is tightly bonded into the actual fibers of the fabric . this may provide built - in protection from mosquitoes , ticks and other potentially dangerous biting insects . like the net wrap jacket , a tracksuit according to embodiments of the present disclosure may be formed of soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig2 a - 2c depict different views of mosquito - repelling tracksuits according to embodiments of the present disclosure . more specifically , these figures depict front and back views of children wearing tracksuits according to embodiments of the present disclosure . the trouser portion of the tracksuit may have a waistband , and the trousers may cover the lower torso and legs of the wearer , while the jacket portion may cover the upper torso and arms of the wearer in some embodiments of the present disclosure . as depicted , these tracksuits are suitable for girls as well as boys and may be provided in a variety of colors , patterns and styles . it also should be appreciated that tracksuits as well as other wearables according to embodiments of the present disclosure may include reflective patterns or other safety / design features . further , while the tracksuits of fig2 a - 2c are being worn by children , it should be appreciated that these tracksuits may also be formed in sizes / styles to be worn by men and women without departing from the present disclosure . in addition , tracksuits according to embodiments of the present disclosure may be provided in a variety of sizes ; however , there may be some embodiments of the present disclosure wherein tracksuits could be provided in a one - size - fits - most style . fig2 a - 2c depict the relatively see - through nature of tracksuits according to embodiments of the present disclosure ; accordingly , wearers generally wear the tracksuits in sizes that allow for their regular clothes to fit underneath the track suit when worn . fig2 a provides a front view of a tracksuit according to an embodiment of the present disclosure . in this embodiment , the fabric is formed in a gathered manner at various points of the track suit , particularly at the wrists , the waistband and the ankles of the wearer . this gathering may reduce the likelihood that a mosquito may reach the wearer &# 39 ; s skin through one of these more open areas of the tracksuit . the gathering may be a ribbed material in some embodiments of the present disclosure . the tracksuit also may include a collar that may have a fold on top but be seamed at the corner front in some embodiments of the present disclosure . this collar also may be formed of a ribbed material . fig2 a also depicts how the tracksuit according to an embodiment of the present disclosure may have a zippered front closure to allow for easy wearability ; the zipper may be attached to the track suit by way of fabric strips ; however , other methods of attachment may be used without departing from the present disclosure . it also should be appreciated that there may be other embodiments of the present disclosure where closure mechanisms other than a zipper may be utilized , for example , buttons or velcro . there may be further embodiments wherein the jacket portion of the track suit may be formed more like a pullover jacket in which case a closure mechanism may not be necessary . in addition , wearable may have reflective portions on one or more sections so that safety can be increase in low - light , hunting , or other similar situations . in a further embodiment of the present disclosure , a track jacket ( fig3 a - 3b ) may be provided . this track jacket may be constructed of a single - layer repellent - treated mesh that is soft and breathable as it helps protect the wearer from inspect bites . the repellent within the mesh may be tightly bonded into the actual fibers of the fabric . this may provide built - in protection that helps protect the wearer against mosquitoes , ticks and other potentially dangerous biting insects . like the other wearables previously described , the track jacket according to embodiments of the present disclosure may be formed of a soft and breathable stretch mesh having a repellent that is effective for approximately 25 launderings . fig3 b depicts how a track jacket according to an embodiment of the present disclosure may cover the upper torso of the wearer in the form of a jacket . while the wearer in fig3 b is depicted as a woman , it should be appreciated that jackets may be provided for men and children ( boys and girls ) as well without departing from the present disclosure . while not specifically depicted in fig2 a - 2c or fig3 a - 3b , it should be appreciated that a track suit or track jacket according to embodiments of the present disclosure may include a hood that connects to the track suit or jacket at a neck line . fig6 depicts a view of mosquito - repelling pants according to an embodiment of the present disclosure . like the pants described in fig2 a - 2c , a ribbed material may be utilized to form a waistband ; however , the pants in fig6 also depict a drawstring closure . further , the pants in fig6 also include drawstring closures at the ankle portions of the pants along with ribbed material . while drawstring closures are depicted in fig6 , it should be appreciated that these closures may not be utilized in all embodiments of the present disclosure . fig7 a depicts a view of a mosquito - repelling infant bunting according to an embodiment of the present disclosure . a hood may be provided as depicted in fig7 a . the bunting also may include a zipper to open and close the bunting , and the bunting also may include a front face that covers the zipper for cleaner finishing on the bunting . the arm portions of the bunting may include back pocket folds over the front to cover the infant &# 39 ; s fingers in some embodiments of the present disclosure . the bunting as depicted in fig7 a may provide a completely closed bottom , such as when the bunting may be employed for a sleeping infant ; however , it should be appreciated that there may be embodiments of the present disclosure where the bunting may not be completely closed and / or may not be used for a sleeping infant . fig7 b depicts a view of a mosquito - repelling infant bunting being worn by an infant according to an embodiment of the present disclosure . fig8 a and 8b depict mosquito - repelling cover - ups according to an embodiment of the present disclosure . more specifically , fig8 a depicts a front view of a cover - up including a hood where there is an overlapping edge between the hood and the body portion of the cover - up to improve skin coverage when worn . fig8 b depicts a cover - up that includes a hood , and this cover - up also includes a neck portion formed of a ribbed material . in some embodiments of the present disclosure , the neck portion may include a slit for the neck opening and / or a serge neckline seam . it should be appreciated that a cover - up may include openings for the arms to be received but otherwise may be closed at the sides . fig9 a depicts a front view of a mosquito - repelling poncho according to an embodiment of the present disclosure , and fig9 b depicts a back view of a mosquito - repelling poncho according to an embodiment of the present disclosure . as depicted herein , a poncho may include a hood that may be placed on the outside of the collar portion . a poncho may differ from the cover - ups depicted in fig8 a and 8b at least insofar as the poncho is open at the sides ( i . e ., does not contain armholes ). the neck portion of the poncho as depicted in fig9 a and 9b may include a ribbed material , and it also may include a button , elastic cord loop or another fastening mechanism around the neck portion to secure the poncho in place in some embodiments of the present disclosure . as depicted in fig9 b , the hood is outside the collar portion at the back of the wearer &# 39 ; s neck and may be gathered as described in other embodiments of the present disclosure . fig1 depicts a front view of a mosquito - repelling caftan cover - up according to an embodiment of the present disclosure . the caftan cover - up of fig1 is similar to the cover - ups and / or ponchos previously described in that it may include ribbed material around the neck portion ; however , it does not include a hood portion . fig4 depicts a mosquito - repelling mesh according to an embodiment of the present disclosure , and fig5 depicts a close - up view of a mosquito - repelling fabric forming the track jackets of fig3 a and 3b . while embodiments of the present disclosure have been described as having repellent within the mesh fabric tightly bonded into the actual fibers of the fabric , it should be appreciated that the repellent also may be woven into the fabric or may be sprayed onto or otherwise applied to the fabric without departing from the present disclosure . in addition , the mosquito - repelling fabric , in one embodiment , can be three - dimensional fabric / mesh , such as depicted in fig2 b and 2c . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . the type of fabric used to form wearables according to embodiments of the present disclosure may depend on the type of wearable . for example , a tracksuit may be formed from a combination of sheer stretch or spandex mesh ( approximately 82 % nylon and approximately 18 % spandex ) and milliskin tricot ( approximately 80 % nylon and approximately 20 % spandex ) while a wrap jacket may be formed of just the sheer stretch or spandex mesh ( i . e ., no milliskin tricot ). there also may be embodiments of the present disclosure where a three - dimensional mesh may be used in addition to or in place of the sheer stretch or spandex mesh and / or milliskin tricot . this three - dimensional mesh may or may not be repellent - treated in embodiments of the present disclosure . however , it should be appreciated that other similar materials may be utilized without departing from the present disclosure . the fabric forming wearables according to embodiments of the present disclosure may have a spongy or springiness that may resist compression and reduction in thickness of the fabric when in use ; this may lessen the likelihood that the insect stinger penetrates the wearer &# 39 ; s skin . the fabric also may provide for sufficient ventilation such that the resultant wearable is not too hot to wear when the weather is warm or when the wearer is engaging in physical activity . regardless the composition of the fabric , the fabric , particularly with respect to a three - dimensional mesh , should be formed of sufficient thickness to prevent an insect stinger bite from penetrating the skin of the wearer . this thickness may be approximately \u215b inches thick ; however , the fabric may be thicker or thinner without departing from the present disclosure . further , the mesh pattern should be formed in such a way that the distance between the wearer &# 39 ; s skin and the insect stinger is as large as possible . also , because of the tightly woven nature of the fabric , the stinger is less likely to penetrate the fabric due to the lack of passageways through the fabric ; this is where the 3 - d nature of the fabric also may be helpful . thus , wearables according to embodiments of the present disclosure may place the repellent near the wearer &# 39 ; s skin instead of being applied to the skin itself . the repellent nature is long - lasting and does not have to be reapplied to the fabric . in addition , the wearables may also include sensors , gps sensors , bluetooth sensors , wi - fi sensors , watches , heart rate monitor , humidity sensor , phone , touchscreen , display , graphical user interface , voice recognition interface , temperature sensor , watch , blood sugar monitor , panic button , camera , drone interface , lte / wi - fi / bluetooth communication processors / sensors , used either alone or in combination with one another , to better improve the use of the wearable . while the embodiments described herein have focused on wearables for humans , there also may be embodiments of the present disclosure wherein pets , such as dogs and cats , may be provided with wearables that may reduce the risk of mosquito bites . for example , a jacket or vest may be provided that may be formed of repellent - treated mesh that a dog may wear when he / she is being walked outside . although the present disclosure and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .", "category": "General tagging of new or cross-sectional technology"}
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Is the category the most suitable category for the given patent?
| 0.25 |
f110da20b8385881318ba008a01321786a066c8e1afc7876c3ab29eb458a9458
| 0.001648 | 0.125977 | 0.022339 | 0.060059 | 0.029785 | 0.083984 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Human Necessities"}
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Does the category match the content of the patent?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.018311 | 0.000755 | 0.043457 | 0.003281 | 0.061768 | 0.016357 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"category": "Performing Operations; Transporting", "patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.001808 | 0.091309 | 0.013245 | 0.015442 | 0.059326 | 0.335938 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Chemistry; Metallurgy"}
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Does the category match the content of the patent?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.018311 | 0.000045 | 0.043457 | 0.004913 | 0.061768 | 0.015442 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"category": "Textiles; Paper", "patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims ."}
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Is the categorization of this patent accurate?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.007568 | 0.014526 | 0.022583 | 0.00038 | 0.081543 | 0.031982 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"category": "Fixed Constructions", "patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims ."}
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Is the patent correctly categorized?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.010315 | 0.053467 | 0.029785 | 0.10498 | 0.051025 | 0.332031 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Does the category match the content of the patent?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.018311 | 0.001701 | 0.043457 | 0.007813 | 0.061768 | 0.025513 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"category": "Physics", "patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims ."}
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Is the categorization of this patent accurate?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.007568 | 0.099609 | 0.022583 | 0.149414 | 0.081543 | 0.232422 |
null |
{"patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .", "category": "Electricity"}
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{"category": "General tagging of new or cross-sectional technology", "patent": "referring now to the drawings , fig1 is a schematic diagram of a microphone comprising a housing 10 in which an audio transducer ( e . g . a microphone insert ) 20 and a one - bit digital signal processor 30 are disposed . a transmission line such as a coaxial cable 40 carries signals from ( and , in some embodiments , to ) the signal processor 30 . fig2 to 4 are more detailed schematic diagrams of respective embodiments of the microphone connected to an input stage 50 of a digital signal processing apparatus 60 . in fig2 to 4 , the following reference numerals are used to denote similar , though not identical , parts : [ 0022 ] 30 , 30 \u2032, 30 \u2033 digital signal processor within the microphone housing the digital signal processing apparatus 60 could be , for example , an audio mixing console or effects unit operable to process one - bit digital audio signals . starting therefore with fig2 the signal processing apparatus 60 includes a clock generator 110 which generates a clocking signal to which the one - bit digital audio signal from the microphone is to be synchronised . the clock generator supplies the clock signal to the input stage 50 and also , via the coaxial cable 40 ( but in a \u201c reverse \u201d direction ), to a clock recovery and power supply unit 120 within the signal processor 30 of the microphone . the clock recovery and power supply unit 120 generates two output signals : one is a straightforward clocking signal supplied to a one - bit analogue - to - digital converter ( adc ) 130 , and the other is a power output which supplies operating power to the one - bit adc 130 , a line driver 140 and ( if necessary ) the audio transducer 20 . the power supply is derived from the clocking signal carried by the coaxial cable 40 by rectifying and smoothing the clocking signal . this avoids the need for a conventional \u201c phantom power \u201d arrangement , although conventional phantom power could be used instead if desired . in operation , therefore , the audio transducer 20 generates an analogue - audio output signal dependant on sound levels in the vicinity of the audio transducer 20 . the one - bit adc 130 converts the analogue signal into a one - bit digital signal in accordance with the clock supplied from the clock recovery and power supply unit 120 . the line driver 140 then amplifies the output of the one - bit adc 130 to a suitable level for transmission via the coaxial cable 40 . at the digital signal processing apparatus 60 , the input stage ( synchronised by the clock generator 110 ) terminates the coaxial cable 40 and \u201c cleans up \u201d the waveform of the digital signal transmitted via the coaxial cable 140 by using a thresholder ( e . g . a schmidt trigger ) to detect whether the signal on the coaxial cable 40 is above or below a threshold signal level , thereby generating a \u201c clean \u201d digital output for subsequent processing . a second embodiment is illustrated in fig3 where the digital signal processing 30 \u2032 includes a clock generator 210 which supplies a clocking signal to the one - bit adc 130 as before . also , as in fig2 the line driver 140 amplifies the output of the one - bit adc 130 to a suitable level for transmission along the coaxial cable 40 . in fig3 the clock generator 210 , the one - bit adc 130 , the line driver 140 and ( if necessary ) the audio transducer 20 are powered either by batteries or by conventional phantom powering . at the recipient digital signal processing apparatus 60 , the signal on the coaxial cable 40 is passed to a clock recovery unit 220 which recovers the clocking rate of the one - bit digital signal by synchronising a phase - locked - loop to the bit rate of the one - bit signal . the input stage 50 \u2032 is synchronised by the output of the clock recovery unit 220 . a further synchronising stage may be required if the one - bit signal from the microphone is to be processed along with one - bit signals synchronised to other clocking sources ( e . g . from other microphones ). [ 0035 ] fig4 illustrates a third embodiment which addresses three potential problems with the embodiment of fig3 . these problems are ( i ) it not always easy to recover a clocking signal from a one - bit digital audio signal ; ( ii ) since a low - pass filtered version of a one - bit digital audio signal can be considered as a representation of the analogue audio signal , there is the danger that the relatively high signal levels output from the line driver 140 will be fed back ( e . g . by induction ) to the relatively low signal level input of the one - bit adc 130 , leading to possible feedback problems potentially causing non - linear distortion ; and ( iii ) if the microphone is unplugged or powered down , the thresholder in the input stage 50 could output a continuous sequence of the same bit value ( e . g . zero )\u2014 which represents a very large signal level indeed in the one - bit digital domain . these potential problems are addressed in the embodiment of fig4 by incorporating a status scrambler 310 in the microphone and a corresponding de - scrambler 320 at the recipient digital signal processing apparatus . the scrambler 310 and de - scrambler 320 will be described in detail below with reference to fig5 but , briefly , their purpose is to ensure that the data transmitted along the coaxial cable 40 is relatively de - correlated from the audio signal supplied to the one - bit adc 130 . this can reduce the problems of feedback between the output of the line driver 130 and the input to the one - bit adc 130 . also , the digital content of the data signal can be changed so that it is easier for the clock recovery circuit 220 to recover a clocking signal from the scrambled signal . [ 0039 ] fig5 a schematically illustrates one embodiment of the scrambler 310 , and fig5 b schematically illustrates one embodiment of the complementary descrambler 320 . in fig5 a , the signal to be scrambled is supplied as one input to a two - input exclusive - or gate 500 . the output of the exclusive - or gate 500 is fed through a series of n one - bit delays 510 \u2014 where n could be , for example , between 8 and 16 . the output of the final delay of the chain forms the scrambled data output and is also fed back to provide the second input to the exclusive - or gate 500 . similarly , in fig5 b , the input data to be descrambled is supplied in parallel to the first of a chain of m one - bit delays ( where m is the same as the value of n in fig5 a ) and to one input of a two - input exclusive - or gate 530 . the other input of the exclusive - or gate 530 receives the output of the chain of delays 520 . the output of the exclusive - or gate 530 forms the descrambled data . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims ."}
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Is the categorization of this patent accurate?
| 0.25 |
81db7d4449235049ddfd44f8c25f9635807ff92bf0243e27cbbae5e07c612113
| 0.007568 | 0.253906 | 0.022583 | 0.326172 | 0.081543 | 0.304688 |
null |
{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"category": "Human Necessities", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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Is the patent correctly categorized?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.341797 | 0.009705 | 0.902344 | 0.016357 | 0.824219 | 0.006287 |
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{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Physics"}
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{"category": "Performing Operations; Transporting", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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Does the category match the content of the patent?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.039551 | 0.02063 | 0.233398 | 0.070801 | 0.135742 | 0.339844 |
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{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Chemistry; Metallurgy"}
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Is the categorization of this patent accurate?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.259766 | 0.000587 | 0.835938 | 0.010315 | 0.648438 | 0.001411 |
null |
{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Textiles; Paper"}
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Is the patent correctly categorized?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.353516 | 0.000278 | 0.902344 | 0.003372 | 0.824219 | 0.003281 |
null |
{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Fixed Constructions"}
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Is the patent correctly categorized?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.341797 | 0.049561 | 0.902344 | 0.225586 | 0.824219 | 0.462891 |
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{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Is the categorization of this patent accurate?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.251953 | 0.001328 | 0.835938 | 0.006897 | 0.648438 | 0.048828 |
null |
{"patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions .", "category": "Physics"}
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{"category": "Electricity", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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Does the category match the content of the patent?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.043457 | 0.482422 | 0.233398 | 0.828125 | 0.135742 | 0.714844 |
null |
{"category": "Physics", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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{"category": "General tagging of new or cross-sectional technology", "patent": "now , preferred embodiments of the present invention will be described in detail with reference to fig1 to 8 . fig1 is a diagram showing the construction of an optical encoder according to a first embodiment . in fig1 , the optical encoder includes two light - emitting elements 11 and 12 disposed in parallel to each other . the optical encoder also includes both an encoder scale having an optical grating and having a movable member at a middle part , and a photoreceptor 14 having photodiodes s 1 to s 4 on a surface thereof , disposed opposing the light - emitting elements 11 and 12 across the encoder scale 13 . as shown in fig2 , the light - emitting elements 11 and 12 have light - emitting windows 11 a and 12 a , receive voltages through wires 11 b and 12 b , respectively , and also receives a common voltage through a common electrode 15 . one advantage of the present invention is that at least two light - emitting windows 11 a and 12 a are provided so that light - emitting states are controlled independently of each other . in contrast , in the related art , windows are provided for light - emitting elements and lights are emitted simultaneously at multiple points . the light - emitting elements 11 and 12 are positioned such that lights received on the photoreceptor 14 are mutually shifted in position by 45 \u00b0. thus , the intensity of light received on the photoreceptor 14 when the light - emitting element 11 is turned on is as indicated by 11 \u2032 in fig1 , and the intensity of light received on the photoreceptor 14 when the light - emitting element 12 is turned on is as indicated by 12 \u2032. fig3 is a diagram showing the relationships between positions of the encoder scale 13 and signal outputs in cases where the light emitting elements 11 and 12 are turned on , respectively . in fig3 , part ( a ) also shows the relationship between an analog waveform and digitally counted values obtained by multiplying one cycle of the analog waveform by four . when the encoder scale 13 attached to the movable member is moved , a pattern of bright and dark regions moves over the photoreceptor 14 . on the photoreceptor 14 , a set of photodiodes s 1 to s 4 is arranged so as to divide each cycle of the bright and dark pattern by four , and by processing the divided parts of the bright and dark pattern , two - phase signals including phase - a signals ( s 1 - s 3 ) and phase - b signals ( s 1 - s 3 ) are output . for the light distribution of the state 11 \u2032 with the light - emitting element 11 turned on , signal values shown in part ( a ) of fig3 are output from processing circuits for phase a and phase b . on the other hand , for the light distribution of the state 12 \u2032 with the light - emitting element 12 turned on , signal values shown in part ( b ) of fig3 are output from the processing circuits for phase a and phase b . when the bright and dark pattern moves over the photoreceptor 14 , the light - emitting element 11 , which is temporally shifted by 90 \u00b0 in phase , is turned on , and signals of phase a and phase b by the encoder scale 13 are obtained . thus , the amount of movement can be detected by counting the number of wave cycles of phase a and phase b . when the encoder scale 13 is at a halt at a certain point p 1 , signal levels take two points a in part ( a ) of fig3 . when the light - emitting element 11 is turned off and the light - emitting element 12 is turned on , the positional relationship between the light - emitting elements 11 and 12 and the encoder scale 13 changes as shown in part ( b ) of fig3 . thus , the relationship between positions and signals also changes ; more specifically , the signals at points a in part ( a ) of fig3 change to points b in part ( b ) of fig3 . this is equivalent to moving the encoder scale 13 by 45 \u00b0 in the arrow direction . with regard to signals output from the signal processing circuits , when the light - emitting element 11 is on , points a are high for both phase a and phase b . on the other hand , when the light - emitting element 12 is on , points b are low for phase a and high for phase b . the switching for phase b indicates that when the encoder 13 actually stops moving after further moving by 45 \u00b0, the signal for phase a switches . that is , phase a and phase b reside in a 45 \u00b0 to 90 \u00b0 region within the 90 \u00b0 region at high level , so that the resolution becomes twice as high . if the signal for phase a remains high , phase a and phase b exist within a 0 \u00b0 to 45 \u00b0 range in the above 90 \u00b0 region at high level . table 1 below shows the relationship between counter values , and digital signal level changes after switching of light - emitting elements , and position . by switching between the light - emitting elements 11 and 12 as described above , the present invention can double the resolution of conventional art systems by reflecting a result obtained to another bit of counter value . fig4 is a diagram showing the construction of an optical encoder according to a second embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the second embodiment , light - emitting elements 21 and 22 are further arranged on both sides of the light - emitting elements 11 and 12 to achieve a resolution that is four times as high compared with the related art . in fig4 , lines 11 \u2032, 12 \u2032, 21 \u2032, and 22 \u2032 represent the intensities of lights received on the photoreceptor 14 when the light - emitting elements 11 , 12 , 21 , and 22 are turned on , respectively . the light - emitting elements 11 , 21 , 12 , and 22 are positioned such that lights received thereby on the photoreceptor 14 are shifted in position by 22 . 5 \u00b0. fig5 is a perspective view of the light - emitting elements in the second embodiment . the light - emitting elements 11 , 12 , 21 , and 22 have light - emitting windows 11 a , 12 a , 21 a , and 22 a , and are connected to wires 11 b , 12 b , 21 b , and 22 b for supplying voltages , respectively . fig6 shows the relationship between the positions of the encoder scale 13 and phase - a signals in cases where the light - emitting elements 11 , 12 , 21 , and 22 are turned on . when the light - emitting element 11 is on , and when the encoder scale 13 stops at a certain point p 2 , signal a is obtained as a phase - a voltage . at this time , the voltage is at high level . then , the light - emitting element 21 is turned on , whereby a signal c is obtained . furthermore , as the light - emitting elements are switched to turn on the light - emitting elements 12 and 22 sequentially , the voltage changes to low level when the light - emitting element 22 is switched on . the state where the light - emitting element 22 is on corresponds to the state where the encoder scale 13 is moved by 67 . 5 \u00b0. that is , a point at which signal level changes correspond to a movement of the encoder scale by 67 . 5 \u00b0. thus , it is understood that p 2 is in a range of 22 . 5 \u00b0 to 45 \u00b0 of the region of the counter value 1 . fig7 and 8 show the construction of an optical encoder according to a third embodiment . in the first embodiment , the two light - emitting elements 11 and 12 are provided and switched to achieve a resolution that is twice as high compared with the related art . in the third embodiment , light - emitting powers of the two light - emitting elements 11 and 12 are changed and the lights are combined to produce a signal . referring to fig7 , when the light - emitting element 11 and the light - emitting element 12 are turned on individually , patterns of bright and dark occur at positions shifted by 90 \u00b0 corresponding to one wave cycle on the photoreceptor 14 . the bright and dark pattern indicated by 11 \u2032 is achieved on the photoreceptor 14 when only the light - emitting element 11 is turned on while the light - emitting elements 11 and 12 and the encoder scale 13 are in a certain positional relationship . when the light - emitting element 12 is then switched on , the bright and dark pattern is shifted by 90 \u00b0 on the photoreceptor 14 , as indicated by 12 \u2032. when the light - emitting elements 11 and 12 are simultaneously caused to emit light at a power of 1 /\u221a 2 compared with the related art , signals output from the processing circuits are combined as indicated by 13 \u2032. this is equivalent to the signal in a case where the photoreceptor 14 is shifted by 45 \u00b0 with respect to the light - emitting element 11 . fig8 shows a case where the balance of light - emitting powers of the light - emitting elements 11 and 12 is changed . as shown in fig8 , a signal in a case where the photoreceptor 14 is shifted by 30 \u00b0 with respect to the light - emitting element 11 can be obtained by setting a ratio such that the light - emitting power of the light - emitting element 11 is cos ( 30 \u00b0)=\u221a 3 / 2 and the light - emitting power of the light - emitting element 12 is sin ( 30 \u00b0)= \u00bd . as for other points , similarly , signals corresponding to shifts in light - emitting position can be obtained by changing the light - emitting powers of the light - emitting elements 11 and 12 . thus , after the encoder scale 13 is stopped , by changing the balance between the light - emitting elements 11 and 12 as if the device is moving , and finding a point where the digital signal level changes , the stop position can be detected at a desired resolution . optical power can be changed by stabilizing optical power while detecting it . or , the optical power can be controlled based on current values assuming a substantially linear relationship between optical power and current . although not discussed , optical power may also be changed by using other methods . although this embodiment relates to a transmissive optical encoder , the same advantages can be achieved by a reflective optical encoder , with the light - emitting elements and the photoreceptor element disposed on the same side . according to one aspect of the present invention , by switching between or changing the power of light sources , a resolution much higher than that of a conventional optical encoder can be achieved . while the present invention has been described with reference to what are presently considered to be the preferred embodiments , it is to be understood that the invention is not limited to the disclosed embodiments . on the contrary , the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims . the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions ."}
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Does the category match the content of the patent?
| 0.25 |
556bf7bba034509eb846dc6effc1daf41a9bb8f2950bb892e641137ae4b904a0
| 0.382813 | 0.28125 | 0.878906 | 0.695313 | 0.84375 | 0.239258 |
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{"category": "Electricity", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Human Necessities"}
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Is the patent correctly categorized?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.208008 | 0.003937 | 0.691406 | 0.306641 | 0.632813 | 0.241211 |
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Electricity"}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Performing Operations; Transporting"}
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Is the category the most suitable category for the given patent?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.004913 | 0.007355 | 0.09668 | 0.056641 | 0.197266 | 0.195313 |
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Electricity"}
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{"category": "Chemistry; Metallurgy", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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Is the patent correctly categorized?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.011353 | 0.009399 | 0.255859 | 0.009155 | 0.248047 | 0.037354 |
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Electricity"}
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{"category": "Textiles; Paper", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.004913 | 0.152344 | 0.09668 | 0.006287 | 0.197266 | 0.316406 |
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{"category": "Electricity", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Fixed Constructions"}
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Does the category match the content of the patent?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.246094 | 0.03418 | 0.632813 | 0.06543 | 0.453125 | 0.178711 |
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{"category": "Electricity", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting"}
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Does the category match the content of the patent?
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9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.246094 | 0.000999 | 0.632813 | 0.192383 | 0.453125 | 0.111328 |
null |
{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Electricity"}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "Physics"}
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Does the patent belong in this category?
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9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.061768 | 0.194336 | 0.675781 | 0.863281 | 0.494141 | 0.613281 |
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{"category": "Electricity", "patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged ."}
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{"patent": "in fig1 a a logic gate according to an exemplary embodiment is depicted . the logic gate 10 comprises a pull - down network 12 , also referred to as \u201c n - block \u201d, a precharge transistor p p , a base transistor n f , also referred to as foot transistor , a keeping circuitry 14 comprising a keeping transistor p k and a switching transistor p pd . the logic gate 10 further comprises an inverter 16 . the logic gate 10 comprises an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the precharge transistor p p is connected between a supply node vdd and a logic node 22 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the precharge transistor p p is a p - channel ( e . g . mosfet ) transistor . the base transistor n f is connected between a reference node ref and the n - block 12 and comprises a control terminal which is connected to the enabling input 18 to receive the enabling signal \u201c enable \u201d. the base transistor n f is an n - channel ( e . g . mosfet ) transistor . the pull - down network 12 is connected between the logic node 22 and the base transistor n f . the pull - down network 12 comprises the logic tree input 19 for receiving the n logic inputs . the pull - down network 12 either pulls the logic node 22 to a logic zero or leaves it at its logic one pre - charged state in response to a boolean combination of the n logic inputs . the keeping circuitry 14 comprises a series connection of the keeping transistor p k and the switching transistor p pd . the series connection of keeping transistor p k and switching transistor p pd is connected between the supply node vdd and the logic node 22 . both transistors p k and p pd are p - channel ( e . g . mosfet ) transistors . a control terminal of the keeping transistor p k is coupled via the inverter 16 to the logic node 22 . the control terminal of the keeping transistor p k is connected to the output 20 of the logic gate 10 . a control terminal of the switching transistor p pd is controlled by a switching control signal \u201c pden \u201d. the central element of the exemplary embodiment is represented by the switching transistor p pd which is controlled by the switching control signal \u201c pden \u201d \u201c pden \u201d. it is its task to speed up the circuit , to avoid short - circuit currents and to reduce the faulty dimensioning risk as well as susceptibility to failure . to clarify the functionality of the switching transistor p pd , in a first section the logic gate 10 is described without the functionality of the switching transistor p pd . this can be achieved by an always switched - on switching transistor p pd , for example , by setting the switching control signal \u201c pden \u201d \u201c pden \u201d to a logical 0 . in a successive section the functionality of the switching transistor p pd is described by choosing an adequate control of the switching control signal \u201c pden \u201d. in the initial state for the consideration , the enabling signal \u201c enable \u201d is in the state 0 and the output (\u201c wl \u201d node ) 20 takes on the logical value 0 . the logical states of the inputs 19 in the pull - down network 12 remains without influence on the output 20 . by the effect of the precharge transistor p p and the keeping transistor p k , the logic node 22 , also referred to as \u201c precharge \u201d node is in the logical precharge state 1 , the switching transistor p pd is always switched - on . thereupon , valid data are applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d and the output (\u201c wl \u201d node ) 20 still being in the state 0 . furthermore , the enabling signal \u201c enable \u201d changes to the state 1 . thus , the precharge transistor p p is blocked , and the base transistor n f enables the pull - down network 12 . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . if the occupancy of the inputs 19 of the pull - down network 12 is , however , such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops and the charge that was stored on the \u201c precharge \u201d node 22 as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . at ( nearly ) the same time , however , the output 20 still is in the state 0 , and the keeping transistor p k thus is conducting . it supplies the \u201c precharge \u201d node 22 with charge . thus , the keeping transistor p k drives (\u201c fights \u201d) against the pull - down network 12 . in the path from the supply node vdd via the keeping transistor p k , the pull - down network 12 and the base transistor n f , a short - circuit current flows . this happens until the \u201c precharge \u201d node 22 has reached the state 0 and then the output (\u201c wl \u201d node ) 20 the state 1 . only then the keeping transistor p k is turned off . the prerequisite for the correct functionality of the circuit 10 consists in the fact that the keeping transistor p k provides less charge than the amount of charge led off to ground by the pull - down network 12 in series with the base transistor n f . this can be the case if the keeping transistor p k is dimensioned to be sufficiently weak as compared with the transistors of the pull - down network 12 . thus , there is the possibility of faulty dimensioning of the keeping transistor p k , so that the pull - down network 12 , particularly if it is a series connection of several n ( e . g . n - channel ) transistors , does not have enough driver strength to overcome the current of the keeping transistor p k . if the pull - down network 12 is not constructed of transistors having great width , the keeping transistor p k should be adapted by enlarging the transistor length . here , it should be taken into consideration that such a dimensioning possibly may be produced only with great tolerance for technological reasons . apart from area losses , this leads to the design risk and reduced robustness . furthermore , at low supply voltage , the driver capability of the series connection of n transistors decreases more quickly than that of the individual keeping transistor p k . in an otherwise robust circuit , this may lead to malfunction . it is also disadvantageous that the pull - down network 12 , which determines the logic function of the logic gate 10 , is hindered in its driver capability by the keeping transistor p k , since the current through the p - channel keeping transistor p k drives against the current of the pull - down network 12 , whereby the switching speed of the circuit 10 is affected noticeably . this effect also is more strongly pronounced toward lower supply voltages . if it is attempted to avoid the above mentioned effect , there is the risk of the keeping transistor p k being designed to be too weak . in turn , this might entail that the \u201c precharge \u201d node 22 is not protected sufficiently against external disturbances . an introduction of the switching transistor p pd and its control by the switching control signal \u201c pden \u201d overcomes the problems mentioned above . the functionality of the logic gate 10 comprising the switching transistor p pd is described hereinafter . the \u201c precharge \u201d node 22 is stabilized and secured against coupling and leakage losses , not by a keeping transistor p k , but by a series connection of the keeping transistor p k and the switching transistor p pd , or the keeping circuitry 14 , respectively . the sequence of the keeping transistor p k and the switching transistor p pd in the series - connection is irrelevant here . also the sequence of the base transistor n f and the n - block 12 is irrelevant . the gate terminal of the keeping transistor p k is attached to the output node 20 for providing the output signal wl . the switching transistor p pd is connected in series with the keeping transistor p k into the path between the supply node vdd and the \u201c precharge \u201d node 22 and is controlled by the switching control signal \u201c pden \u201d. the initial state for the consideration corresponds to the one already described above . in the precharge state , the enabling signal enables in the state 0 , and the output (\u201c wl \u201d node ) 20 takes on the value 0 . the switching control signal \u201c pden \u201d here also is logically 0 . now , the \u201c precharge \u201d node 22 is in the precharge state through the effect of the precharge transistor p p , and the series connection of the keeping transistor p k and the switching transistor p pd . the occupancy of the inputs 19 in the pull - down network 12 remains without effect . valid data are further applied to the pull - down network 12 , with the enabling signal \u201c enable \u201d as well as the output 20 and the switching control signal \u201c pden \u201d still being in the state 0 . thereupon , the enabling signal \u201c enable \u201d and the switching control signal \u201c pden \u201d ( nearly ) simultaneously change into the state 1 . alternatively , the switching control signal \u201c pden \u201d may be set into the state 1 earlier . thus , the precharge transistor p p and the switching transistor p pd are blocked , and the base transistor n f enables the pull - down network 12 . the path between the supply node vdd and the \u201c precharge \u201d node 22 is interrupted by the switching transistor p pd . the \u201c precharge \u201d node 22 takes on the state 1 or 0 , corresponding to the occupancy of the inputs 19 in the pull - down network 12 . in the first case , the circuit 10 does not change its state . however , if the occupancy of the inputs 19 of the pull - down network 12 is such that the pull - down network 12 connects through , the following situation arises . in the series connection comprising the base transistor n f and the n transistors of the pull - down network 12 , a current flow develops , and the charge that was stored on the \u201c precharge \u201d node 22 , as well as maybe on the intermediate nodes of the pull - down network 12 flows off to ground ref . since the switching transistor p pd now blocks , the pull - down network 12 only has to drain off the charge stored on the above - mentioned nodes . no additional charge is supplied by the keeping transistor p k , and short - circuit current does not flow either . after the \u201c precharge \u201d node 22 has reached a state corresponding to the input 19 occupancy and function of the pull - down network 12 , the switching control signal \u201c pden \u201d may again change to the state 0 . in case the pull - down network 12 does not switch , i . e . the \u201c precharge \u201d signal ( at the \u201c precharge \u201d node 22 ) remains logically 1 , this change should happen quickly so as not to leave the \u201c precharge \u201d node 22 in a non - driven state for long . switching on the switching control signal \u201c pden \u201d may be linked directly to the enabling signal \u201c enable \u201d. switching off may be realized by a delay chain , for example . this is possible in short combinational paths with many gates switching in parallel . if the switching control signal \u201c pden \u201d is controlled correctly , embodiments of the exemplary embodiment offer a series of advantages . there is no risk of the keeping transistor p k being dimensioned to be too strong ( or the pull - down network 12 to be dimensioned too weak ). the transistor length of the keeping transistor p k remains minimal . the speed the pull - down network 12 can work with is increased because less charge has to be drained - off . the functionality of the circuit 10 is not at risk even at low supply voltages . there is no risk of the keeping transistor p k being dimensioned to be too weak . with this , the susceptibility of the \u201c precharge \u201d node 22 to disturbing influences is reduced . the short - circuit current is avoided , the power consumption drops . potentially , a reduction in area is achieved , because the width of the transistors in the pull - down network 12 may be dimensioned to be smaller . additionally , the length of the keeping transistor p k may be kept minimal . by the inclusion and the control of the switching transistor p pd a speed - up of the circuit 10 , avoidance of short circuit currents and reduction of the faulty dimensioning risk as well as susceptibility to failures is achieved . exemplary embodiments may be applied as speed - up and robustness measure also in dynamic logic , for example , domino circuits . in these families of circuits , the keeping transistor p k often is required only when circuit 10 is in idle state , because otherwise the time in which the \u201c precharge \u201d node 22 is not driven is very short . here , the control of the switching transistor p pd by the switching control signal \u201c pden \u201d is also very simple . the switching transistor p pd is blocked in the active phase and switched on in the inactive phase . if the keeping transistor p k is to become effective also in the active phase , the switch - off time instant for the switching control signal \u201c pden \u201d can be derived from the enabling signal \u201c enable \u201d, for example , through delay . fig1 b shows a set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a . in a first timing diagram ( 1 .) the timing of the enabling signal \u201c enable \u201d is depicted . the enabling signal assumes a first signal state vref and a second signal state vdd and is a periodical signal . the first signal state vref corresponds to a precharge phase 100 while the second signal state vdd corresponds to an evaluation phase 101 of the logic gate 10 . a second timing diagram ( 2 .) depicts the timing of the precharge signal \u201c precharge \u201d which is the signal state which the logic node 22 assumes when the logic gate 10 is enabled by the enabling signal \u201c enable \u201d. in a first period 102 of the enabling signal , the pull down - network ( n - block ) 12 is enabling the discharge of logic node 22 while in a second period 103 of the enabling signal the n - block 12 is disabling the discharge of logic node 22 . during the precharge phase 100 of the first period 102 , the precharge signal is inverse to the enabling signal . when the enabling signal changes from the first state vref to the second state vdd and the n block 12 is enabling , a driver conflict may occur such that a switching of the precharge signal from vdd to vref does not occur upon the rising edge of the enabling signal . for a short conflicting time period 104 , a switching of the precharge signal may be non - deterministic as the charge of the logic node 22 is fed to vref by the n - block 12 while at the same conflicting time period 104 , the keeping transistor p k is delivering a charge of potential vdd to the logic node 22 . during the second period 103 of the enabling signal , the n - block 12 is disabling the discharge of the logic node 22 such that the precharge signal assumes the second state vdd without a change upon a rising edge of the enabling signal . the third timing diagram ( 3 .) shows the timing behavior of the output signal \u201c wl \u201d of the logic gate 10 which shows the inverse signal state as the precharge signal . a fourth timing diagram ( 4 .) shows the timing of the switching control signal \u201c pden \u201d which holds the first state vref for the complete representation time depicted in fig1 b . this corresponds to a permanent through connection of the switching transistor ppd . fig1 c shows another set of timing diagrams of signals associated with the logic gate 10 as depicted in fig1 a according to an exemplary embodiment . a first timing diagram ( 1 .) shows the timing of the enabling signal \u201c enable \u201d which corresponds to the timing of the enabling signal as depicted in fig1 b . the second timing diagram ( 2 .) shows a timing of a delayed enabling signal \u201c enabledel \u201d. a delay of d is applied to the enabling signal \u201c enable \u201d to obtain the delayed enabling signal \u201c enabledel \u201d. a third timing diagram ( 3 .) shows the timing of the switching control signal \u201c pden \u201d which corresponds to the enabling signal \u201c enable \u201d combined with the inverse of the delayed enabling signal \u201c enabledel \u201d by a logical and combination . a fourth timing diagram ( 4 .) depicts the timing of the precharge signal during a first period 102 of the enabling signal when the n - block is enabling the discharge of logic node 22 and during a second period 103 of the enabling signal when the n - block is disabling the discharge of logic node 22 . in contrast to the precharge signal depicted in fig1 b , the precharge signal depicted in fig1 c is changing its signal state during the first enabling signal period 102 ( n - block is enabling ) from vdd to vref in a deterministic manner upon a rising edge of the enabling signal without a conflicting time period 104 . no driver conflicts can be seen in the timing diagram ( 4 .) of the precharge signal . this results from the control of the switching control signal \u201c pden \u201d which switches off the first potential vdd from the logic node 22 during a transition of the enabling signal from vref to vdd for the duration of the delay time d . after the delay time d when the discharging process is finished and the precharge signal assumes a logical 0 , the switching control signal \u201c pden \u201d switches - on the switching transistor p pd to allow the keeping transistor p k taking over control . the delay time d may be dimensioned such that a bridging of the conflicting time period 104 as depicted in fig1 b may be achieved . the delay time d may , for example , be greater or equal to the conflicting time period 104 . a fifth timing diagram ( 5 .) depicts the timing of the output signal \u201c wl \u201d which assumes the inverse value of the precharge signal without showing any driver conflicting phases as the output signal \u201c wl \u201d depicted in fig1 b . fig2 shows an address decoding circuit 30 according to an exemplary embodiment . the address decoding circuit 30 uses a wired - or circuitry 32 for generation of a switching control signal \u201c pden \u201d ( rdy , respectively ). the address decoding circuit 30 comprises a logic gate 10 which corresponds to the logic gate 10 as described in fig1 having an enabling input 18 for receiving an enabling signal \u201c enable \u201d, a logic tree input 19 for receiving n logic inputs of the n - block 12 and an output 20 for providing a data output signal wl . the address decoding circuit 30 further comprises a plurality of further logic gates 10 b , 10 c and the wired - or circuitry 32 . each of the further logic gates 10 b , 10 c corresponds to the logic gate 10 as described in fig1 . while having a same enabling input 18 for receiving an enabling signal \u201c enable \u201d each of the further logic gates comprises an individual logic tree input 19 b , 19 c for receiving n logic inputs and an individual output 20 b , 20 c for providing a plurality of further data output signals wl 2 , wl 3 . the wired - or circuitry 32 comprises a wired - or node \u201c wiredor \u201d, a supply transistor p wo , an output transistor p wo1 associated with the logic gate 10 and a plurality of further output transistors p wo2 , p wo3 associated with a respective further logic gate 10 b , 10 c . a control terminal of the output transistor p wo1 is connected to the output 20 of the logic gate 10 . control terminals of the further output transistors p wo2 , p wo3 are connected to the outputs 20 b , 20 c of the respective further logic gates 10 b , 10 c . a first channel terminal of the output transistor p wo1 is connected to the reference node ref and a second channel terminal of the output transistor p wo1 is connected to the wired - or node \u201c wiredor \u201d. first channel terminals of the further output transistors p wo2 , p wo3 are connected to the reference node ref and second channel terminals of the further output transistors p wo2 , p wo3 are connected to the wired - or node . the supply transistor p wo is controlled by a supply control signal \u201c wopq \u201d at its control terminal . the supply transistor p wo is connected between the supply node vdd and the wired - or node \u201c wiredor \u201d. while the supply transistor p wo may be shared between different logic gates 10 , 10 b , 10 c a respective output transistor p wo1 , p wo2 , p wo3 will be used for each logic gate 10 , 10 b , 10 c . a condition for the switching - on ( closing ) of the switching transistor p pd by the switching control signal \u201c pden \u201d may be derived from the signal at the wired - or node \u201c wiredor \u201d which is denoted by \u201c rdy \u201d in fig2 . the logic gate 10 may be applied in any type of address decoding circuit 30 because the point at time in which the switching control signal \u201c pden \u201d is reset to the state 0 can be determined in a particularly simple way here . since an address decoder 30 typically works in a \u201c one - hot \u201d arrangement , only one of the address decoder cells 10 , 10 b , 10 c changes its state . the outputs 20 , 20 b , 20 c of the cells 10 , 10 b , 10 c may be linked by means of a \u201c wired - or \u201d connection . a \u201c wired - or \u201d connection connects different outputs 20 , 20 b , 20 c in a direct way without wasting resources to save power . if the common node \u201c wiredor \u201d has changed its state , the switching control signal \u201c pden \u201d can safely be placed into the state 0 again . the state of the node \u201c wiredor \u201d is evaluated and has direct influence on the switching control signal \u201c pden \u201d. here , the supply transistor p wo is implemented only once for the entire address decoder 30 . fig3 a shows a logic circuit 40 comprising logic gates and a reference path for generating a switching control signal for the logic gates according to an exemplary embodiment . the logic circuit 40 comprises a dynamic logic stage 42 and a dummy ( reference ) path stage 44 which are connected in parallel . the dummy path stage 44 comprises a static logic sub - circuit 46 and a dynamic logic sub - circuit 48 . the dynamic logic stage 42 comprises two dynamic logic or gates dor 1 and dor 2 and two dynamic logic and gates dand 2 and dand 3 . the two dynamic logic or gates and the two dynamic logic and gates may represent logic gates 10 , according to the logic gate 10 as depicted in fig1 a . the two dynamic logic or / and gates are arranged in propagation groups 51 , 52 , 53 with respect to signal propagation times which input signals of respective dynamic logic or / and gates experience when propagating through the dynamic logic stage 42 . the first dynamic logic or gate dor 1 is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . a first propagation signal 61 which may correspond to one of the n logic inputs at the logic tree input 19 as depicted in fig1 is provided at both inputs of the first dynamic logic or gate dor 1 , at the first input of the second dynamic logic or gate dor 2 and at the second input of the first dynamic logic and gate dand 2 . a second propagation signal 62 is provided at the output of the first dynamic logic or gate dor 1 which is connected to the second input of the second dynamic logic or gate dor 2 and to the first input of the first dynamic logic and gate dand 2 . a third propagation signal 63 a is provided at the output of the second dynamic logic or gate dor 2 which is connected to the first input of the second dynamic logic and gate dand 3 . a fourth propagation signal 63 b is provided at the output of the first dynamic logic and gate dand 2 which is connected via an inverter inv to the second input of the second dynamic logic and gate dand 3 . a fifth propagation signal 64 is provided at the output of the second dynamic logic and gate dand 3 . according to propagation times of their input signals the dynamic logic or / and gates are associated to propagation groups . as the first dynamic logic or gate dor 1 has only the first propagation signal 61 as input it is associated with the first propagation group 51 . the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 have beside the first propagation signal 61 additionally the second propagation signal 62 as input . the second propagation signal 62 has the additional signal propagation time of the first dynamic logic or gate dor 1 with respect to the first propagation signal 61 . therefore , the second dynamic logic or gate dor 2 and the first dynamic logic and gate dand 2 are associated with the second propagation group 52 . the second dynamic logic and gate dand 3 has the propagation signals 63 a , 63 b as inputs which are related to signal propagation times of the first propagation signal 61 propagating through the first dynamic logic or gate dor 1 and the second dynamic logic or gate dor 2 or the first dynamic logic and gate dand 2 , respectively . the second dynamic logic and gate dand 3 is associated with the third propagation group 53 . dor 1 is enabled by the enabling signal \u201c enable_ 1 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 1 \u201d. dor 2 and dand 2 are enabled by the enabling signal \u201c enable_ 2 \u201d, their switching transistors are controlled by the switching control signal \u201c pden_ 2 \u201d. dand 3 is enabled by the enabling signal \u201c enable_ 3 \u201d, its switching transistor is controlled by the switching control signal \u201c pden_ 3 \u201d. the dynamic logic sub - circuit 48 comprises three dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d which are arranged in dummy propagation groups 51 d , 52 d and 53 d associated with the propagation groups 51 , 52 and 53 of the dynamic logic stage 42 . each of the dummy dynamic logic or gates arranged in a respective dummy propagation group has a similar or identical signal propagation delay as the dynamic logic or / and gate of the propagation group the respective dummy propagation group is associated with . a first dummy dynamic logic or gate dor 1 d is arranged in the first dummy propagation group 51 d and receives the first propagation signal 61 at its first and second input . a second dummy dynamic logic or gate dor 2 d is arranged in the second dummy propagation group 52 d and is connected with its both inputs to the output of the first dummy dynamic logic or gate dor 1 d . a third dummy dynamic logic or gate dor 3 d is arranged in the third dummy propagation group 53 d and is connected with its both inputs to the output of the second dummy dynamic logic or gate dor 2 d . the output signal 62 d of dor 1 d has a similar propagation delay as the second propagation signal 62 . the output signal 63 d of dor 2 d has a similar propagation delay as the third or fourth propagation signals 63 a , 63 b . the output signal 64 d of dor 3 d has a similar propagation delay as the fifth propagation signal 64 . dor 1 d is enabled by a first dummy enabling signal \u201c enabledummy_ 1 \u201d. dor 2 d is enabled by a second dummy enabling signal \u201c enabledummy_ 2 \u201d. dor 3 d is enabled by a third dummy enabling signal \u201c enabledummy_ 3 \u201d. the static logic sub - circuit 46 is used to combine the output signals and associated enabling signals of the dummy dynamic logic or gates dor 1 d , dor 2 d and dor 3 d to provide switching control signals \u201c pden 1 \u201d, \u201c pden 2 \u201d, and \u201c pden 3 \u201d to the dynamic logic or gates dor 1 , dor 2 and dynamic logic and gates dand 2 and dand 3 . the static logic sub - circuit 46 comprises three static logic and gates . a first static logic and gate and 1 combines the inverted output signal 62 d of dor 1 d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d by a logical and combination to provide the first switching control signal \u201c pden_ 1 \u201d. a second static logic and gate and 2 combines the inverted output signal 63 d of dor 2 d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d by a logical and combination to provide the second switching control signal \u201c pden_ 2 \u201d. a third static logic and gate and 3 combines the inverted output signal 64 d of dor 3 d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d by a logical and combination to provide the third switching control signal \u201c pden_ 3 \u201d. the switching control signals \u201c pden_ 1 \u201d, \u201c pden_ 2 \u201d and \u201c pden_ 3 \u201d are provided by a logic circuitry ( dummy path stage 44 ) representing a reference circuit for the dynamic logic stage 42 . by this circuitry it can be assured that the respective switching control signals have an adequate timing with respect to signal propagation delay of the dynamic logic gates dor 1 , dor 2 , dand 2 and dand 3 . for a greater number of combinational paths , the reference path 44 or dummy path , respectively setting the point in time at which the switching control signal \u201c pden \u201d is to be switched off in individual propagation groups 51 , 52 , 53 may be constructed . so , as to achieve better temporal behaviour the reference path 44 could operate in a slightly phase - shifted manner . the dynamic logic or gates dor 1 , dor 2 and the dynamic logic and gates dand 2 , dand 3 of the dynamic logic stage 42 are examples illustrating the functionality of a logic gate 10 as depicted in fig1 a . instead of a dynamic logic or / and gate also any other type of logic combinational element can be used . the dynamic logic or gates dor 1 d , dor 2 d , dor 3 d of the dynamic logic sub - circuit 48 are dimensioned to comprise similar signal propagation times as the dynamic logic gates of the dynamic logic stage 42 . the output signals 62 d , 63 d , 64 d of the dummy dynamic logic or gates dor 1 d , dor 2 d , dor 3 d are configured to change their signal state responsive to a transition of the respective dummy enabling signal from a logical 0 to a logical 1 . the respective dummy enabling signals may be coupled to the respective enabling signals such that a signal transition of the respective enabling signal triggers a signal transition of the respective dummy enabling signal . fig3 b shows a set of timing diagrams of signals associated with the logic circuit 40 as depicted in fig3 a according to an exemplary embodiment . the timing diagrams depicted in fig3 b are one possible implementation for dimensioning the logic circuit 40 as depicted in fig3 a . in this embodiment , the input signal 61 , the first enabling signal \u201c enable_ 1 \u201d and the first dummy enabling signal \u201c enabledummy_ 1 \u201d are synchronized with respect to their rising and falling signal edges . in this embodiment all three signals are ( nearly ) equal . a second timing diagram ( 2 .) depicts the timing of the input signals 62 , 62 d , the second enabling signal \u201c enable_ 2 \u201d and the second dummy enabling signal \u201c enabledummy_ 2 \u201d. these four signals have a synchronized timing and are delayed by a time delay d 1 with respect to the input signal 61 , the first enabling signal and the first dummy enabling signal . the time delay d 1 results from the propagation delay of the dynamic or gate dor 1 or from the propagation delay of the dynamic or gate dor 1 d , which is designed to have a similar propagation delay as the dynamic or gate dor 1 . the third timing diagram ( 3 .) depicts the timing of the first switching control signal \u201c pden 1 \u201d which is derived from the first dummy enabling signal \u201c enabledummy_ 1 \u201d and the inverse of the input signal 62 d by a logical and combination . the first switching control signal \u201c pden 1 \u201d is synchronized to the input signal 61 and the first enabling signal \u201c enable_ 1 \u201d such that a transition of the first enabling signal from a logical 0 \u201c vref \u201d to a logical 1 \u201c vdd \u201d controls the switching transistor p pd of the first dynamic or gate dor 1 to provide for an accelerated charge transition of the respective logic node 22 . the fourth timing diagram ( 4 .) depicts the timing of the input signals 63 a , 63 b , 63 d , the third enabling signal \u201c enable_ 3 \u201d and the third dummy enabling signal \u201c enabledummy_ 3 \u201d. these signals are synchronized with respect to their rising and falling edges and are delayed by a second time delay d 2 with respect to the input signal 62 and the second enabling signal \u201c enable_ 2 \u201d. the second time delay d 2 corresponds to the propagation delay of the second dummy dynamic or gate dor 2 d which is dimensioned such that it has a similar propagation delay corresponding to the second dynamic or gate dor 2 or the first dynamic and gate dand 2 , respectively . the fifth timing diagram ( 5 .) depicts the timing of the second switching control signal \u201c pden 2 \u201d which corresponds to a logical and combination of the second dummy enabling signal \u201c enabledummy_ 2 \u201d and the inverse of the input signal 63 d of the third dummy dynamic or gate dor 3 d . the second switching control signal \u201c pden 2 \u201d is synchronized to the second enabling signal \u201c enable_ 2 \u201d and is dimensioned such that the switching transistor p pd of the second dynamic or gate dor 2 and the first dynamic and gate dand 2 are controlled to provide for an accelerated charge transition of their respective logic nodes 22 . a sixth timing diagram ( 6 .) shows a timing of the output signals 64 , 64 d of the third dummy dynamic or gate dor 3 d and the second dynamic and gate dand 3 , respectively . both signals are synchronized with respect to their rising and falling signal edges and are delayed by a time delay d 3 with respect to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively . the third time delay d 3 corresponds to a propagation delay of the third dummy dynamic or gate dor 3 d which is dimensioned to be similar to the signal propagation delay of the second dynamic and gate dand 3 . the seventh timing diagram ( 7 .) shows the timing of the third switching control signal \u201c pden 3 \u201d which corresponds to a logical and combination of the third dummy enabling signal \u201c enabledummy_ 3 \u201d and the inverse of the output signal \u201c output 64 d \u201d of the third dummy dynamic logic or gate dor 3 d . the third switching control signal \u201c pden 3 \u201d is synchronized to the third enabling signal \u201c enable_ 3 \u201d and the input signals 63 a , 63 b , 63 d of dand 3 and dor 3 d , respectively , to provide for an accelerated charge transition of their respective logic nodes 22 . fig4 a shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic and gate according to an exemplary embodiment . the pull down network 12 a of the logic gate 10 a comprises a dynamic logic and gate which is implemented as a series connection of two n - channel transistors n 0 and n 1 , connected between the logic node 22 and the base transistor n f . the first n - channel transistor n 0 is controlled by a first input signal a 0 and the second n - channel transistor n 1 is controlled by a second input signal a 1 . both input signals a 0 and a 1 are provided by the logic tree input 19 . fig4 b shows a circuit diagram of the logic gate 10 as depicted in fig1 a , wherein the n - block 12 comprises a dynamic logic or gate according to an exemplary embodiment . the pull down network 12 b of the logic gate 10 b comprises a logic or gate which is implemented as a series - connection of an n - channel compensation transistor n t and a parallel - connection of a first n - channel transistor n 0 and a second n - channel transistor n 1 . the series - connection is connected between the logic node 22 and the base transistor n f . the compensation transistor n t is controlled by the enabling signal \u201c enable \u201d and is adapted to compensate differences in the switching times of the first and the second n - channel transistors n 0 , n 1 . the first n - channel transistor n 0 is controlled by a first control signal a 0 and the second n - channel transistor n 1 is controlled by a second control signal a 1 . both control signals a 0 , a 1 are provided by the logic tree input 19 . the compensation transistor n t optimizes the performance of the pull down network 12 b but is not necessarily required . other embodiments may comprise a pull down network 12 b without the compensation transistor n t , such that the parallel connection of the first n - channel transistor n 0 and the second n - channel transistor n 1 is connected between the logic node 22 and the base transistor n f . the logic gate 10 may also be implemented using transistors of complementary channel type . the base transistor n f may be implemented as p - channel transistor , the pull - down network 12 implemented as a pull - up network 12 comprising n p - channel ( or optionally n - channel ) transistors , the charging transistor p p , the keeping transistor p k and the switching transistor p pd implemented as n - channel transistors . the sequence of the n - block 12 and the base transistor n f may be exchanged .", "category": "General tagging of new or cross-sectional technology"}
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Is the patent correctly categorized?
| 0.25 |
9368f039f0e5054fa2b5c9c80e9f6ef721a78619261b1704e12ea1466b122fda
| 0.208008 | 0.040771 | 0.691406 | 0.404297 | 0.632813 | 0.298828 |
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{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "General tagging of new or cross-sectional technology"}
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{"category": "Human Necessities", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.1875 | 0.188477 | 0.095215 | 0.027588 | 0.083984 | 0.179688 |
null |
{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "General tagging of new or cross-sectional technology"}
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{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "Performing Operations; Transporting"}
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Is the categorization of this patent accurate?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.067383 | 0.015869 | 0.257813 | 0.151367 | 0.129883 | 0.223633 |
null |
{"category": "General tagging of new or cross-sectional technology", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "Chemistry; Metallurgy"}
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Does the category match the content of the patent?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.582031 | 0.017456 | 0.574219 | 0.063477 | 0.439453 | 0.063477 |
null |
{"category": "General tagging of new or cross-sectional technology", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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{"category": "Textiles; Paper", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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Is the patent correctly categorized?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.408203 | 0.447266 | 0.636719 | 0.00885 | 0.554688 | 0.660156 |
null |
{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "General tagging of new or cross-sectional technology"}
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{"category": "Fixed Constructions", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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Is the category the most suitable category for the given patent?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.1875 | 0.365234 | 0.095215 | 0.429688 | 0.083984 | 0.503906 |
null |
{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "General tagging of new or cross-sectional technology"}
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{"category": "Mechanical Engineering; Lightning; Heating; Weapons; Blasting", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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Is the patent correctly categorized?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.038574 | 0.028931 | 0.09668 | 0.054932 | 0.088867 | 0.332031 |
null |
{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "General tagging of new or cross-sectional technology"}
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{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "Physics"}
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Is the categorization of this patent accurate?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.067383 | 0.036865 | 0.257813 | 0.108398 | 0.129883 | 0.114258 |
null |
{"category": "General tagging of new or cross-sectional technology", "patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea ."}
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{"patent": "a slider 100 of general classical structure is evident in fig1 . this slider 100 comprises a base 110 , two lateral flanges 10 , 120 , 130 and a central bead 140 . the lateral flanges 120 , 130 and the central bead 140 define in combination two channels 150 , 160 , in part at least not parallel . these channels 150 , 160 join at one end of the slider 100 , as in fig2 . the channels 150 , 160 join together the closing elements 200 , 300 , respectively . the specialist understands that as it is moved the slider 100 , according to the direction of motion , separates the closing profiles 200 , 300 , as shown in fig1 , or on the contrary carries the latter engaged , as shown in fig2 . the attached figures illustrate two closing elements 200 , 300 extruded onto films 250 , 350 , constituting the sachet proper . as a variant , and in a manner known per se , the closing elements 200 , 300 could be made initially separately , then connected and fixed onto the films 250 , 350 by any appropriate means , for example by thermal welding . according to the embodiments illustrated in the attached figures , the two closing elements 200 , 300 comprise support bulges 210 , 310 , each of which carries a closing element as such 212 , 312 respectively of complementary male and female type . by way of variant , such elements 212 , 312 could be replaced by any equivalent means , for example structures with hooks or complementary hook and loop fastener type such as those sold under the trademark velcro . as mentioned earlier , according to the present invention the slider 100 comprises , on the apex of the slider 100 opposite the base 110 , at least one flexible lip 145 , 146 placed opposite a lead angle 216 , 316 provided on a closing element 200 , 300 , according to a configuration , such that any attempt to pull back the slider 100 results in autolocking hanging of the lip 145 , 146 . more precisely again , preferably within the scope of the present invention , the closing device comprises two lips 145 , 146 cooperating respectively with a lead angle 216 , 316 provided on each of the two elements 200 , 300 . the lead angles 216 , 316 are provided on the inner face of the closing elements 200 , 300 . the lips 145 , 146 are oriented towards the base 110 by moving away from a plane of symmetry 0 - 0 parallel to the direction of translation of the slider and passing through the plane of symmetry of the central bead 140 . fig3 shows that if the attempt is made to pull back the slider 100 , the lead angles 216 , 316 stress the lips 145 , 146 . the lips 145 , 146 then are underpinned and deformed , their apex being brought closer to the lateral flanges 120 , 130 ( moving away from the base 110 by deformation accompanied by a pivoting movement about the zone connecting the lips 145 , 146 at the apex of the central bead 140 ). this ends in autolocking , where the closing elements or the films 250 , 350 are wedged between the apex of the lips 145 , 146 and the flanges 120 , 130 . the specialist will understand that simultaneously this produces a seal between the two film elements 250 , 350 inside the slider 100 . the height of the lips 145 , 146 , illustrated under reference e 1 in fig3 , is preferably greater than a width e 2 , illustrated in the same fig3 , of the free opening formed between the apex of the central bead 140 and the free end of the flanges 120 , 130 . consequently , owing to this arrangement , it is guaranteed that during an attempt to pull back the slider 100 the apex of the lips 145 , 146 rests against the films 250 , 350 . in the case as shown in fig1 to 3 , the lateral flanges 120 , 130 have a flared sole plate 121 , 131 at their free end , more precisely , the lips 145 , 146 are stressed against the flanks of these sole plates 121 , 131 during an attempt to pull back the slider 100 . fig4 illustrates a variant embodiment according to which the lips 145 , 146 have a length even greater , such that their apexes do not rest against the flanks of the sole plates 121 , 131 but against lead angles 123 , 133 formed between the flanks of the sole plates 121 , 131 and the flanges 120 , 130 , and directed towards the base 110 . the specialist will understand that this arrangement further reinforces the locking effect on the underpinned lips 145 , 146 , at the same time limiting the stress by separating the lateral flanges 120 , 130 . fig5 shows another variant embodiment according to which it is provided with lips 125 , 135 , 145 , 146 simultaneously on the lateral flanges 120 , 130 and on the central bead 140 . these lips 125 , 135 and 145 , 146 cooperate with lead angles 215 , 315 , 216 , 316 provided respectively on the outer faces and on the inner faces 20 of the bulges 210 , 310 of the closing elements . according to the embodiment shown in fig5 , the lips above 125 , 135 and 145 , 146 are situated substantially on the same level and have substantially identical lengths and suppleness . so their apexes come into mutual contact on either side of the films 250 , 350 when the slider 100 is stressed or pulled back . on the contrary fig6 and 7 show pairs of lips 125 , 135 and 145 , 146 , respectively , having different lengths . according to the embodiment shown in fig6 , the longest lips 145 , 146 are solid with the central bead 140 . conversely , according to the embodiment shown in fig7 , the longest lips 125 , 135 are solid with the inner faces of the lateral flanges 120 , 130 in the two cases of the embodiments illustrated in fig6 and 7 , the longest lips are placed on the interior of the slider relative to the shortest lips . the specialist will understand that in this case , the outer face of the longest lips comes into contact with the apex of the shortest lips during an attempt to pull back the slider . fig8 shows another variant embodiment according to which the lateral flanges 120 , 130 are fitted , in the vicinity of their free end opposite the base 110 , and on their inner face , with substantially rigid flanges 122 , 132 . these flanges 122 , 132 each define an inclined facet 124 , 134 forming a ramp which converges towards the plane symmetry 0 - 0 by moving away from the base 110 . two lips 145 , 146 solid with the end free of the central bead 140 opposite the base 110 are placed on the interior of these ramps 124 , 134 . the lips 144 , 146 converge towards the base 100 by moving away from the plane of symmetry 0 - 0 . the ramps 124 , 134 define in combination with the lips 145 , 146 channels 128 , 138 which converge by moving away from the base 110 . the specialist will comprehend from studying fig8 that the channels 128 , 138 cause the films 250 , 350 to approach one another and ensure contact between the latter at the level of a zone referenced 290 in fig8 . such a structure obviously improves the sealing property of the device . in addition , the specialist will comprehend that this sealing is further reinforced when an attempt is made to pull back the slider , with the lips 145 , 146 30 tending to accentuate the effort and convergence of the films 250 , 350 . scrutiny of the attached figures will clarify that the slider 100 is preferably fitted on the outer face of the base 110 with two tappets or lugs 112 , 114 substantially adjacent to the flanges 120 , 130 . in a manner known per se , such tappets 112 , 114 , when they are caused to approach one another , stress the flanges 120 , 130 to move apart and consequently accentuate the width of opening of the channels 150 , 160 to facilitate engagement of a slider on the closing elements 210 , 220 . the lips 125 , 135 , 145 , 146 can be made from the same material as the essential material of the slider 100 , or from a different material . they are preferably made from a supple material such as polyethylene or ethylene copolymer . it is understood that the present invention is not limited to the particular embodiments described hereinabove but extends to any variant in keeping with its basic idea .", "category": "Electricity"}
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Is the patent correctly categorized?
| 0.25 |
f3740f8b2fbded08eb0afadc9aab3eb4c9d9d5d13da1ccc21d72c4594f315fa9
| 0.408203 | 0.00383 | 0.636719 | 0.022583 | 0.554688 | 0.008057 |
null |
{"patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope .", "category": "Physics"}
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{"patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope .", "category": "Human Necessities"}
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Is the patent correctly categorized?
| 0.25 |
2f0ce1de0f76a1441bea3dffa7e8eb006617087ad061b80afc6b89513670388c
| 0.005737 | 0.007111 | 0.014038 | 0.099609 | 0.017456 | 0.066406 |
null |
{"category": "Physics", "patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope ."}
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{"category": "Performing Operations; Transporting", "patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope ."}
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Is the patent correctly categorized?
| 0.25 |
2f0ce1de0f76a1441bea3dffa7e8eb006617087ad061b80afc6b89513670388c
| 0.027222 | 0.087402 | 0.007813 | 0.084961 | 0.026733 | 0.339844 |
null |
{"patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope .", "category": "Physics"}
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{"patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope .", "category": "Chemistry; Metallurgy"}
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Does the patent belong in this category?
| 0.25 |
2f0ce1de0f76a1441bea3dffa7e8eb006617087ad061b80afc6b89513670388c
| 0.003937 | 0.000216 | 0.017944 | 0.024048 | 0.018311 | 0.015869 |
null |
{"patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope .", "category": "Physics"}
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{"category": "Textiles; Paper", "patent": "the message clip according to the invention is a distinctive product to accessorize hats , other articles of clothing , book bags , bracelets , etc . the unique design makes it easy to apply quickly to an assortment of things , the message clip gives people the opportunity to express themselves with a wide variety of messaging . the message clip can be removably attached to a band to be worn on the wrist of a user as a message displaying bracelet . the message clip can be made of spring steel , brass , plastic , precious metals , or other suitable material , in a shape similar to a basic money clip . as shown in fig1 and 2 , a message clip 10 has a body 11 with a clip portion 12 attached to one side and a message portion 13 attached to an opposite side . the body 11 has a generally planar rear surface 14 to which the generally u - shaped clip portion 12 is attached at a generally straight leg 15 thereof . the clip portion 12 can be attached to the surface 14 by a fastening means in any suitable manner such as by welding or with an adhesive material . the clip portion 12 is formed from a resilient material so that a free leg 16 can be bent away from the attached leg 15 to insert an item therebetween such as one or more layers of cloth at an edge of a cap , shirt pocket , pants belt loop , etc . when released , the free leg 16 will spring back toward the attached leg 15 to firmly and releasably hold the message clip 10 on the item . the body 11 has a front surface 17 at which the message portion 13 is mounted . the front surface 17 is surrounded at a periphery by an outwardly extending flange 18 to form a recessed area such that the message portion 13 is partially recessed ( fig2 ). an outwardly facing display surface 19 of the message portion 13 has a visible message applied thereto . as shown in fig1 , the message is an exclamation mark 20 , but can be any symbol , logo , words , picture , etc . the display surface 19 can be flat or curved ( as shown ), and the message can be raised from and / or recessed into the surface 19 . the message portion 13 can be attached to the front surface 17 by a fastening device 21 in any suitable manner such as by welding , or with an adhesive material , or by a mechanical fastener . for example , the fastening device 21 is shown in the form of a layer of adhesive material or a double - sided adhesive sheet . in a preferred embodiment , the body 11 , the clip portion and the message portion are formed from etched brass and the message 20 is offset printed on the display surface . other fastening devices can be used to attach the message portion to the body . as shown in fig3 , an alternate embodiment body 11 a can have a projections 22 formed on an inner surface of a flange 18 a . the projections 22 can be of any suitable shape and cooperate with a depression or groove 23 formed in a side of an alternate embodiment message portion 13 a . the message portion 13 can be permanently fixed relative to the clip portion 12 , as well as be variably fixed , which allows the user to \u201c turn \u201d the display surface 19 to the desired angle . in some cases , the attachment of the message clip 10 to an item may require reorientation of the message 20 for proper viewing . for example , if the message clip 10 shown in fig1 is rotated 90 \u00b0, it may be difficult to recognize the message 20 as an exclamation mark . as shown in fig5 , an alternate embodiment body 11 b can be attached to a clip potion 12 b by a rotation device such as a pivot pin 24 that permits rotation of the body 11 b relative to the clip portion 12 b . as shown in fig4 , a message clip body 11 c , similar to any of the bodies 11 , 11 a , 11 b , can have a clip portion 12 a formed integral therewith such that the body 11 c and the clip portion 12 a are a one - piece unit . a leg 16 a , similar to the leg 16 , extends generally parallel to and is spaced from the rear surface 14 . the leg 16 a has one end 16 b that is u - shaped and connects to a peripheral surface lid of the body 11 c . an opposite free end 16 c of the leg 16 a extends away from the body 11 c at the peripheral surface 11 d . similar to the message clip 10 shown in fig1 and 2 , the free end 16 c of the leg 16 a is positioned at an upper portion of the message 20 when the message clip is oriented for viewing . the message clip 10 also can be provided with the capability to light up and / or play sounds . as shown in fig6 , a light 25 and an audio player 26 , for playing stored music , words , miscellaneous sounds , etc ., are connected to a source of power such as a battery 27 by a switch 28 . the light 25 , the audio player 26 , the battery 27 and the switch 28 can be located in the recess formed in the body 11 by the front surface 17 and the flange 18 . a message portion 13 b is used to selectively actuate the switch 28 by mechanical action , or preferably by sensing contact of a human finger on the display surface 19 . although only the one switch 28 is shown , separate switches could be provided for the light 25 and the audio player 26 . the message clip 10 can come in a variety of shapes and sizes to compliment the message 20 being displayed . for example , the body 11 and the message portion 13 can be circular . this would permit the message portion 13 to be rotatably attached to the body 11 by the pivot pin 24 . the message 20 can be proprietary and non - proprietary verbiage , slogans , sayings , taglines , company names , brand names , logos , icons , licensed materials , and imagery to express any messages desired . as shown in fig7 and 8 , a message clip 30 has a body 31 , similar to the body 11 c shown in fig4 , with a clip portion 32 formed integral therewith such that the body 31 and the clip portion 32 are a one - piece unit . the message clip 30 includes the message portion 13 mounted in a recessed area at the front surface for displaying the message 20 . the clip portion 32 extends from an upper periphery 31 a of the outwardly extending flange 31 b that forms a side wall of the recess . a leg 33 of the clip portion 32 extends at an angle to and is spaced from the rear surface of the body 31 . the leg 33 has one end 33 a that is u - shaped and connects to the upper periphery 31 a of the body 31 . the leg 33 then angles toward the body 31 and terminates in a free end 33 b that curves away from the body 31 short of a lower periphery 31 c . the free end 33 b of the leg 33 has a raised portion 34 extending toward the back surface of the body 31 as shown in fig8 . if the body 31 and the clip portion 32 are formed of a plastic material , the raised portion can be a molded feature . if the body 31 and the clip portion 32 are formed of a metal material , the raised portion 34 can be formed by displacing material in the free end 33 b resulting in a corresponding depression 35 at the outer surface of the leg 33 as shown in fig9 . the message clip 30 is intended to be used in a message display bracelet 36 as shown in fig1 . the bracelet 36 includes a continuous band 37 of flexible , elastic material . for example , the band 37 can be formed from a silicone material that is latex free . the band 37 has a generally rectangular cross section with a width w and a thickness t . the band 37 will stretch in diameter to slide over a hand of the user and then return to the unstretched diameter or larger to accommodate the user &# 39 ; s wrist . the message clip 30 is shown removably attached to the band 37 by receiving the band between the rear surface of the body 31 and the clip portion 32 . the height of the body 31 between the upper periphery 31 a and the lower periphery 31 c is approximately equal to the width w of the band 37 . as shown in fig1 , the body 31 and the clip portion 32 slightly compress the band 37 to reduce the thickness from t to t \u2032. this compression and gripping by the raised portion 34 removably secure the clip 30 to the band 37 for wearing the bracelet 36 . of course , more than one of the message clip 30 can be removably attached to the band 37 for displaying different messages . in accordance with the provisions of the patent statutes , the invention has been described in what is considered to represent its preferred embodiment . however , it should be noted that the invention can be practiced otherwise than as specifically illustrated and described without departing from its spirit or scope ."}
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Does the category match the content of the patent?
| 0.25 |
2f0ce1de0f76a1441bea3dffa7e8eb006617087ad061b80afc6b89513670388c
| 0.006897 | 0.090332 | 0.054199 | 0.0065 | 0.042725 | 0.103516 |
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