Formally Verified Verilog Reasoning Datasets
William Patrick Yubeaton
wilyub
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updated
a dataset
1 day ago
wilyub/VeriThoughtsTrainSetInconsistentReasoningGT
updated
a dataset
1 day ago
wilyub/VeriThoughtsTrainSetInconsistentReasoningGEN
updated
a dataset
1 day ago
wilyub/VeriThoughtsTrainSetInconsistentInstructionGT