system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} | code for sm_80
Function : _Z2dsPfPiS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R6, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0006 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fe200078e0206 */
/*0100*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0110*/ @P0 LEA R8, P1, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000080a11 */
/* 0x040fe400078210ff */
/*0120*/ @P0 MOV R11, 0x3f800000 ; /* 0x3f800000000b0802 */
/* 0x000fe40000000f00 */
/*0130*/ @P0 LEA.HI.X R9, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590000090a11 */
/* 0x000fca00008f14ff */
/*0140*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x000fe8000c101904 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IMAD R7, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007077a24 */
/* 0x004fc800078e0204 */
/*0180*/ IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0006 */
/*0190*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} | .file "tmpxft_0018dc8c_00000000-6_ds.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
.type _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj, @function
_Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2dsPfPiS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj, .-_Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
.globl _Z2dsPfPiS_jj
.type _Z2dsPfPiS_jj, @function
_Z2dsPfPiS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2dsPfPiS_jj, .-_Z2dsPfPiS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2dsPfPiS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2dsPfPiS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} | #include <hip/hip_runtime.h>
__global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2dsPfPiS_jj
.globl _Z2dsPfPiS_jj
.p2align 8
.type _Z2dsPfPiS_jj,@function
_Z2dsPfPiS_jj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x10
v_mul_lo_u32 v5, v2, s3
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v5, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_3
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_mov_b32_e32 v0, 1.0
global_store_b32 v[3:4], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2dsPfPiS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2dsPfPiS_jj, .Lfunc_end0-_Z2dsPfPiS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2dsPfPiS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2dsPfPiS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void ds(float *ds,int * y, float *delta, const unsigned int r, const unsigned int c )
{
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(row < r && col < c) {
if( delta[row * c + col] > 0)
ds[row * c + col ] = 1;
__syncthreads();
ds[row * c + y[row]] = 0;
}
} | .text
.file "ds.hip"
.globl _Z17__device_stub__dsPfPiS_jj # -- Begin function _Z17__device_stub__dsPfPiS_jj
.p2align 4, 0x90
.type _Z17__device_stub__dsPfPiS_jj,@function
_Z17__device_stub__dsPfPiS_jj: # @_Z17__device_stub__dsPfPiS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2dsPfPiS_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__dsPfPiS_jj, .Lfunc_end0-_Z17__device_stub__dsPfPiS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2dsPfPiS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2dsPfPiS_jj,@object # @_Z2dsPfPiS_jj
.section .rodata,"a",@progbits
.globl _Z2dsPfPiS_jj
.p2align 3, 0x0
_Z2dsPfPiS_jj:
.quad _Z17__device_stub__dsPfPiS_jj
.size _Z2dsPfPiS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2dsPfPiS_jj"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__dsPfPiS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2dsPfPiS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2dsPfPiS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R6, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0006 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fe200078e0206 */
/*0100*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0110*/ @P0 LEA R8, P1, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000080a11 */
/* 0x040fe400078210ff */
/*0120*/ @P0 MOV R11, 0x3f800000 ; /* 0x3f800000000b0802 */
/* 0x000fe40000000f00 */
/*0130*/ @P0 LEA.HI.X R9, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590000090a11 */
/* 0x000fca00008f14ff */
/*0140*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x000fe8000c101904 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IMAD R7, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007077a24 */
/* 0x004fc800078e0204 */
/*0180*/ IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0006 */
/*0190*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2dsPfPiS_jj
.globl _Z2dsPfPiS_jj
.p2align 8
.type _Z2dsPfPiS_jj,@function
_Z2dsPfPiS_jj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x10
v_mul_lo_u32 v5, v2, s3
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v5, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 0, v0
s_cbranch_execz .LBB0_3
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_mov_b32_e32 v0, 1.0
global_store_b32 v[3:4], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2dsPfPiS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2dsPfPiS_jj, .Lfunc_end0-_Z2dsPfPiS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2dsPfPiS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2dsPfPiS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018dc8c_00000000-6_ds.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
.type _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj, @function
_Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2dsPfPiS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj, .-_Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
.globl _Z2dsPfPiS_jj
.type _Z2dsPfPiS_jj, @function
_Z2dsPfPiS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z2dsPfPiS_jjPfPiS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2dsPfPiS_jj, .-_Z2dsPfPiS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2dsPfPiS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2dsPfPiS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ds.hip"
.globl _Z17__device_stub__dsPfPiS_jj # -- Begin function _Z17__device_stub__dsPfPiS_jj
.p2align 4, 0x90
.type _Z17__device_stub__dsPfPiS_jj,@function
_Z17__device_stub__dsPfPiS_jj: # @_Z17__device_stub__dsPfPiS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2dsPfPiS_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__dsPfPiS_jj, .Lfunc_end0-_Z17__device_stub__dsPfPiS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2dsPfPiS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2dsPfPiS_jj,@object # @_Z2dsPfPiS_jj
.section .rodata,"a",@progbits
.globl _Z2dsPfPiS_jj
.p2align 3, 0x0
_Z2dsPfPiS_jj:
.quad _Z17__device_stub__dsPfPiS_jj
.size _Z2dsPfPiS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2dsPfPiS_jj"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__dsPfPiS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2dsPfPiS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "bitmap.cuh"
void BmpHeader::setDim(int32_t w, int32_t h) {
width = w;
height = h;
sizeOfBitmapFile = HEADER_SIZE + w * h * 3; // Each pixel takes 3 bytes
}
void BmpHeader::setRes(double mmPerPixel) {
horizontalResolution = (int32_t)(1000/mmPerPixel);
verticalResolution = (int32_t)(1000/mmPerPixel);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "bitmap.cuh"
void BmpHeader::setDim(int32_t w, int32_t h) {
width = w;
height = h;
sizeOfBitmapFile = HEADER_SIZE + w * h * 3; // Each pixel takes 3 bytes
}
void BmpHeader::setRes(double mmPerPixel) {
horizontalResolution = (int32_t)(1000/mmPerPixel);
verticalResolution = (int32_t)(1000/mmPerPixel);
} | .file "tmpxft_000525c0_00000000-6_bitmap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN9BmpHeader6setDimEii
.type _ZN9BmpHeader6setDimEii, @function
_ZN9BmpHeader6setDimEii:
.LFB2027:
.cfi_startproc
endbr64
movl %esi, 18(%rdi)
movl %edx, 22(%rdi)
imull %edx, %esi
leal 54(%rsi,%rsi,2), %eax
movl %eax, 2(%rdi)
ret
.cfi_endproc
.LFE2027:
.size _ZN9BmpHeader6setDimEii, .-_ZN9BmpHeader6setDimEii
.align 2
.globl _ZN9BmpHeader6setResEd
.type _ZN9BmpHeader6setResEd, @function
_ZN9BmpHeader6setResEd:
.LFB2028:
.cfi_startproc
endbr64
movapd %xmm0, %xmm1
movsd .LC0(%rip), %xmm0
divsd %xmm1, %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 38(%rdi)
movl %eax, 42(%rdi)
ret
.cfi_endproc
.LFE2028:
.size _ZN9BmpHeader6setResEd, .-_ZN9BmpHeader6setResEd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "bitmap.cuh"
void BmpHeader::setDim(int32_t w, int32_t h) {
width = w;
height = h;
sizeOfBitmapFile = HEADER_SIZE + w * h * 3; // Each pixel takes 3 bytes
}
void BmpHeader::setRes(double mmPerPixel) {
horizontalResolution = (int32_t)(1000/mmPerPixel);
verticalResolution = (int32_t)(1000/mmPerPixel);
} | /**
* @file bitmap.h
*/
#ifndef BITMAP_H_
#define BITMAP_H_
#include <cstdint>
#define HEADER_SIZE 54
struct __attribute__((packed))BmpHeader {
char bitmapSignatureBytes[2] = {'B', 'M'};
uint32_t sizeOfBitmapFile = 0; // Need to add size to it
uint32_t reservedBytes = 0;
uint32_t pixelDataOffset = HEADER_SIZE;
uint32_t sizeOfThisHeader = HEADER_SIZE - 14;
int32_t width = 0; // in pixels
int32_t height = 0; // in pixels
uint16_t numberOfColorPlanes = 1; // must be 1
uint16_t colorDepth = 24;
uint32_t compressionMethod = 0;
uint32_t rawBitmapDataSize = 0; // generally ignored
int32_t horizontalResolution = 0; // in pixel per meter
int32_t verticalResolution = 0; // in pixel per meter
uint32_t colorTableEntries = 0;
uint32_t importantColors = 0;
void setDim(int32_t width, int32_t height);
void setRes(double mmPerPixel);
};
struct Pixel {
uint8_t blue = 0;
uint8_t green = 0;
uint8_t red = 0;
};
#define BLACK (Pixel{0,0,0})
#define WHITE (Pixel{255,255,255})
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* @file bitmap.h
*/
#ifndef BITMAP_H_
#define BITMAP_H_
#include <cstdint>
#define HEADER_SIZE 54
struct __attribute__((packed))BmpHeader {
char bitmapSignatureBytes[2] = {'B', 'M'};
uint32_t sizeOfBitmapFile = 0; // Need to add size to it
uint32_t reservedBytes = 0;
uint32_t pixelDataOffset = HEADER_SIZE;
uint32_t sizeOfThisHeader = HEADER_SIZE - 14;
int32_t width = 0; // in pixels
int32_t height = 0; // in pixels
uint16_t numberOfColorPlanes = 1; // must be 1
uint16_t colorDepth = 24;
uint32_t compressionMethod = 0;
uint32_t rawBitmapDataSize = 0; // generally ignored
int32_t horizontalResolution = 0; // in pixel per meter
int32_t verticalResolution = 0; // in pixel per meter
uint32_t colorTableEntries = 0;
uint32_t importantColors = 0;
void setDim(int32_t width, int32_t height);
void setRes(double mmPerPixel);
};
struct Pixel {
uint8_t blue = 0;
uint8_t green = 0;
uint8_t red = 0;
};
#define BLACK (Pixel{0,0,0})
#define WHITE (Pixel{255,255,255})
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* @file bitmap.h
*/
#ifndef BITMAP_H_
#define BITMAP_H_
#include <cstdint>
#define HEADER_SIZE 54
struct __attribute__((packed))BmpHeader {
char bitmapSignatureBytes[2] = {'B', 'M'};
uint32_t sizeOfBitmapFile = 0; // Need to add size to it
uint32_t reservedBytes = 0;
uint32_t pixelDataOffset = HEADER_SIZE;
uint32_t sizeOfThisHeader = HEADER_SIZE - 14;
int32_t width = 0; // in pixels
int32_t height = 0; // in pixels
uint16_t numberOfColorPlanes = 1; // must be 1
uint16_t colorDepth = 24;
uint32_t compressionMethod = 0;
uint32_t rawBitmapDataSize = 0; // generally ignored
int32_t horizontalResolution = 0; // in pixel per meter
int32_t verticalResolution = 0; // in pixel per meter
uint32_t colorTableEntries = 0;
uint32_t importantColors = 0;
void setDim(int32_t width, int32_t height);
void setRes(double mmPerPixel);
};
struct Pixel {
uint8_t blue = 0;
uint8_t green = 0;
uint8_t red = 0;
};
#define BLACK (Pixel{0,0,0})
#define WHITE (Pixel{255,255,255})
#endif | .text
.file "bitmap.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000525c0_00000000-6_bitmap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN9BmpHeader6setDimEii
.type _ZN9BmpHeader6setDimEii, @function
_ZN9BmpHeader6setDimEii:
.LFB2027:
.cfi_startproc
endbr64
movl %esi, 18(%rdi)
movl %edx, 22(%rdi)
imull %edx, %esi
leal 54(%rsi,%rsi,2), %eax
movl %eax, 2(%rdi)
ret
.cfi_endproc
.LFE2027:
.size _ZN9BmpHeader6setDimEii, .-_ZN9BmpHeader6setDimEii
.align 2
.globl _ZN9BmpHeader6setResEd
.type _ZN9BmpHeader6setResEd, @function
_ZN9BmpHeader6setResEd:
.LFB2028:
.cfi_startproc
endbr64
movapd %xmm0, %xmm1
movsd .LC0(%rip), %xmm0
divsd %xmm1, %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 38(%rdi)
movl %eax, 42(%rdi)
ret
.cfi_endproc
.LFE2028:
.size _ZN9BmpHeader6setResEd, .-_ZN9BmpHeader6setResEd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitmap.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} | code for sm_80
Function : _Z13xsigny_updateiPKdPdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ DSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f04000 */
/*00d0*/ @P0 BRA 0x150 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*00e0*/ DSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e1c0003f0e000 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0120*/ DADD R2, -R4, R2 ; /* 0x0000000004027229 */
/* 0x004e0e0000000102 */
/*0130*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0160*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0170*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x004e0e0000000002 */
/*0180*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} | .file "tmpxft_0002f11b_00000000-6_xsigny_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
.type _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_, @function
_Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13xsigny_updateiPKdPdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_, .-_Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
.globl _Z13xsigny_updateiPKdPdS1_
.type _Z13xsigny_updateiPKdPdS1_, @function
_Z13xsigny_updateiPKdPdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13xsigny_updateiPKdPdS1_, .-_Z13xsigny_updateiPKdPdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13xsigny_updateiPKdPdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13xsigny_updateiPKdPdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13xsigny_updateiPKdPdS1_
.globl _Z13xsigny_updateiPKdPdS1_
.p2align 8
.type _Z13xsigny_updateiPKdPdS1_,@function
_Z13xsigny_updateiPKdPdS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f64_e32 0, v[3:4]
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_mov_b32 s3, exec_lo
v_cmpx_gt_f64_e32 0, v[3:4]
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[4:5], -v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13xsigny_updateiPKdPdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13xsigny_updateiPKdPdS1_, .Lfunc_end0-_Z13xsigny_updateiPKdPdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13xsigny_updateiPKdPdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13xsigny_updateiPKdPdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void xsigny_update(const int n, const double *a, double *b, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0)
{c[i]+=a[i];}
else
{if (b[i]<0)
{c[i]-=a[i];}
}
}
} | .text
.file "xsigny_update.hip"
.globl _Z28__device_stub__xsigny_updateiPKdPdS1_ # -- Begin function _Z28__device_stub__xsigny_updateiPKdPdS1_
.p2align 4, 0x90
.type _Z28__device_stub__xsigny_updateiPKdPdS1_,@function
_Z28__device_stub__xsigny_updateiPKdPdS1_: # @_Z28__device_stub__xsigny_updateiPKdPdS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13xsigny_updateiPKdPdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__xsigny_updateiPKdPdS1_, .Lfunc_end0-_Z28__device_stub__xsigny_updateiPKdPdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13xsigny_updateiPKdPdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13xsigny_updateiPKdPdS1_,@object # @_Z13xsigny_updateiPKdPdS1_
.section .rodata,"a",@progbits
.globl _Z13xsigny_updateiPKdPdS1_
.p2align 3, 0x0
_Z13xsigny_updateiPKdPdS1_:
.quad _Z28__device_stub__xsigny_updateiPKdPdS1_
.size _Z13xsigny_updateiPKdPdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13xsigny_updateiPKdPdS1_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__xsigny_updateiPKdPdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13xsigny_updateiPKdPdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13xsigny_updateiPKdPdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ DSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f04000 */
/*00d0*/ @P0 BRA 0x150 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*00e0*/ DSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e1c0003f0e000 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0120*/ DADD R2, -R4, R2 ; /* 0x0000000004027229 */
/* 0x004e0e0000000102 */
/*0130*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0160*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea4000c1e1b00 */
/*0170*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x004e0e0000000002 */
/*0180*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x001fe2000c101b04 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13xsigny_updateiPKdPdS1_
.globl _Z13xsigny_updateiPKdPdS1_
.p2align 8
.type _Z13xsigny_updateiPKdPdS1_,@function
_Z13xsigny_updateiPKdPdS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f64_e32 0, v[3:4]
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_mov_b32 s3, exec_lo
v_cmpx_gt_f64_e32 0, v[3:4]
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[4:5], -v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13xsigny_updateiPKdPdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13xsigny_updateiPKdPdS1_, .Lfunc_end0-_Z13xsigny_updateiPKdPdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13xsigny_updateiPKdPdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13xsigny_updateiPKdPdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002f11b_00000000-6_xsigny_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
.type _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_, @function
_Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13xsigny_updateiPKdPdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_, .-_Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
.globl _Z13xsigny_updateiPKdPdS1_
.type _Z13xsigny_updateiPKdPdS1_, @function
_Z13xsigny_updateiPKdPdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13xsigny_updateiPKdPdS1_iPKdPdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13xsigny_updateiPKdPdS1_, .-_Z13xsigny_updateiPKdPdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13xsigny_updateiPKdPdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13xsigny_updateiPKdPdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "xsigny_update.hip"
.globl _Z28__device_stub__xsigny_updateiPKdPdS1_ # -- Begin function _Z28__device_stub__xsigny_updateiPKdPdS1_
.p2align 4, 0x90
.type _Z28__device_stub__xsigny_updateiPKdPdS1_,@function
_Z28__device_stub__xsigny_updateiPKdPdS1_: # @_Z28__device_stub__xsigny_updateiPKdPdS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13xsigny_updateiPKdPdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__xsigny_updateiPKdPdS1_, .Lfunc_end0-_Z28__device_stub__xsigny_updateiPKdPdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13xsigny_updateiPKdPdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13xsigny_updateiPKdPdS1_,@object # @_Z13xsigny_updateiPKdPdS1_
.section .rodata,"a",@progbits
.globl _Z13xsigny_updateiPKdPdS1_
.p2align 3, 0x0
_Z13xsigny_updateiPKdPdS1_:
.quad _Z28__device_stub__xsigny_updateiPKdPdS1_
.size _Z13xsigny_updateiPKdPdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13xsigny_updateiPKdPdS1_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__xsigny_updateiPKdPdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13xsigny_updateiPKdPdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} | code for sm_80
Function : _Z12pi_optimizedPfS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R23, RZ, RZ, 0x61a80 ; /* 0x00061a80ff177424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0060*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R7, R0, c[0x0][0x0], RZ ; /* 0x0000000000077a24 */
/* 0x001fc800078e02ff */
/*0090*/ IMAD.IADD R8, R7, 0x1, R6 ; /* 0x0000000107087824 */
/* 0x002fca00078e0206 */
/*00a0*/ IADD3 R22, R8, 0xaae60, RZ ; /* 0x000aae6008167810 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD.IADD R2, R6, 0x1, R7 ; /* 0x0000000106027824 */
/* 0x000fe200078e0207 */
/*00c0*/ IADD3 R10, R22, -0x927c0, RZ ; /* 0xfff6d840160a7810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*00e0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fe2000f8e00ff */
/*00f0*/ ISETP.GT.AND P5, PT, R2, 0x5f5e0ff, PT ; /* 0x05f5e0ff0200780c */
/* 0x000fe20003fa4270 */
/*0100*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe4000f8e00ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe4000f8e00ff */
/*0120*/ IMAD.WIDE R4, R8, 0x4, R4 ; /* 0x0000000408047825 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R2, R8, 0x4, R2 ; /* 0x0000000408027825 */
/* 0x000fe200078e0202 */
/*0140*/ ISETP.GT.AND P1, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fc60003f24270 */
/*0150*/ @!P5 LDG.E R12, [R4.64] ; /* 0x00000006040cd981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P5 LDG.E R13, [R2.64] ; /* 0x00000006020dd981 */
/* 0x000eec000c1e1900 */
/*0170*/ @!P1 LDG.E R16, [R4.64+0x61a80] ; /* 0x061a800604109981 */
/* 0x000f28000c1e1900 */
/*0180*/ @!P1 LDG.E R15, [R2.64+0x61a80] ; /* 0x061a8006020f9981 */
/* 0x000f62000c1e1900 */
/*0190*/ IADD3 R10, R22, -0x7a120, RZ ; /* 0xfff85ee0160a7810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3 R10, R22, -0x61a80, RZ ; /* 0xfff9e580160a7810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GT.AND P4, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fce0003f84270 */
/*01d0*/ @!P0 LDG.E R10, [R4.64+0xc3500] ; /* 0x0c350006040a8981 */
/* 0x000f62000c1e1900 */
/*01e0*/ IADD3 R17, R22, -0x493e0, RZ ; /* 0xfffb6c2016117810 */
/* 0x000fc60007ffe0ff */
/*01f0*/ @!P0 LDG.E R11, [R2.64+0xc3500] ; /* 0x0c350006020b8981 */
/* 0x000f62000c1e1900 */
/*0200*/ ISETP.GT.AND P3, PT, R17, 0x5f5e0ff, PT ; /* 0x05f5e0ff1100780c */
/* 0x000fe40003f64270 */
/*0210*/ IADD3 R17, R22, -0x186a0, RZ ; /* 0xfffe796016117810 */
/* 0x000fe20007ffe0ff */
/*0220*/ @!P5 FMUL R14, R12, R12 ; /* 0x0000000c0c0ed220 */
/* 0x004fe40000400000 */
/*0230*/ @!P4 LDG.E R12, [R4.64+0x124f80] ; /* 0x124f8006040cc981 */
/* 0x000ea4000c1e1900 */
/*0240*/ @!P5 FFMA R14, R13, R13, R14 ; /* 0x0000000d0d0ed223 */
/* 0x008fe4000000000e */
/*0250*/ @!P4 LDG.E R13, [R2.64+0x124f80] ; /* 0x124f8006020dc981 */
/* 0x0000e6000c1e1900 */
/*0260*/ FSETP.GEU.AND P6, PT, R14, 1, !P5 ; /* 0x3f8000000e00780b */
/* 0x000fe20006fce000 */
/*0270*/ @!P1 FMUL R18, R16, R16 ; /* 0x0000001010129220 */
/* 0x010fe20000400000 */
/*0280*/ IADD3 R14, R22, -0x30d40, RZ ; /* 0xfffcf2c0160e7810 */
/* 0x000fc80007ffe0ff */
/*0290*/ ISETP.GT.AND P2, PT, R14, 0x5f5e0ff, PT ; /* 0x05f5e0ff0e00780c */
/* 0x000fe20003f44270 */
/*02a0*/ @!P1 FFMA R18, R15, R15, R18 ; /* 0x0000000f0f129223 */
/* 0x020fe20000000012 */
/*02b0*/ @!P3 LDG.E R14, [R4.64+0x186a00] ; /* 0x186a0006040eb981 */
/* 0x000f22000c1e1900 */
/*02c0*/ @!P5 IADD3 R16, R9, 0x1, RZ ; /* 0x000000010910d810 */
/* 0x000fc60007ffe0ff */
/*02d0*/ @!P3 LDG.E R15, [R2.64+0x186a00] ; /* 0x186a0006020fb981 */
/* 0x000162000c1e1900 */
/*02e0*/ @P6 IMAD.MOV R16, RZ, RZ, R9 ; /* 0x000000ffff106224 */
/* 0x000fe200078e0209 */
/*02f0*/ FSETP.GEU.AND P6, PT, R18, 1, !P1 ; /* 0x3f8000001200780b */
/* 0x000fc60004fce000 */
/*0300*/ @!P5 IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff09d224 */
/* 0x000fe200078e0010 */
/*0310*/ ISETP.GT.AND P5, PT, R17, 0x5f5e0ff, PT ; /* 0x05f5e0ff1100780c */
/* 0x000fe20003fa4270 */
/*0320*/ @!P2 LDG.E R19, [R4.64+0x1e8480] ; /* 0x1e8480060413a981 */
/* 0x000f68000c1e1900 */
/*0330*/ @!P2 LDG.E R18, [R2.64+0x1e8480] ; /* 0x1e8480060212a981 */
/* 0x000162000c1e1900 */
/*0340*/ @!P1 IADD3 R24, R9, 0x1, RZ ; /* 0x0000000109189810 */
/* 0x000fc60007ffe0ff */
/*0350*/ @P6 IMAD.MOV R24, RZ, RZ, R9 ; /* 0x000000ffff186224 */
/* 0x000fe200078e0209 */
/*0360*/ ISETP.GT.AND P6, PT, R22, 0x5f5e0ff, PT ; /* 0x05f5e0ff1600780c */
/* 0x000fc60003fc4270 */
/*0370*/ @!P5 LDG.E R17, [R4.64+0x249f00] ; /* 0x249f00060411d981 */
/* 0x000f68000c1e1900 */
/*0380*/ @!P5 LDG.E R16, [R2.64+0x249f00] ; /* 0x249f00060210d981 */
/* 0x00016c000c1e1900 */
/*0390*/ @!P6 LDG.E R20, [R4.64+0x2ab980] ; /* 0x2ab980060414e981 */
/* 0x000f68000c1e1900 */
/*03a0*/ @!P6 LDG.E R21, [R2.64+0x2ab980] ; /* 0x2ab980060215e981 */
/* 0x000162000c1e1900 */
/*03b0*/ @!P0 FMUL R10, R10, R10 ; /* 0x0000000a0a0a8220 */
/* 0x000fe20000400000 */
/*03c0*/ IADD3 R23, R23, 0xc3500, RZ ; /* 0x000c350017177810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R24 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0018 */
/*03e0*/ UIADD3 UR8, UP0, UR8, 0x30d400, URZ ; /* 0x0030d40008087890 */
/* 0x000fe2000ff1e03f */
/*03f0*/ @!P0 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a8223 */
/* 0x000fe2000000000a */
/*0400*/ UIADD3 UR4, UP1, UR4, 0x30d400, URZ ; /* 0x0030d40004047890 */
/* 0x000fe2000ff3e03f */
/*0410*/ IADD3 R22, R22, 0xc3500, RZ ; /* 0x000c350016167810 */
/* 0x000fe20007ffe0ff */
/*0420*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3 R7, R7, 0xc3500, RZ ; /* 0x000c350007077810 */
/* 0x000fe20007ffe0ff */
/*0440*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*0450*/ FSETP.GEU.AND P1, PT, R10, 1, !P0 ; /* 0x3f8000000a00780b */
/* 0x000fc4000472e000 */
/*0460*/ @!P0 IADD3 R10, R9, 0x1, RZ ; /* 0x00000001090a8810 */
/* 0x000fd60007ffe0ff */
/*0470*/ @P1 IMAD.MOV R10, RZ, RZ, R9 ; /* 0x000000ffff0a1224 */
/* 0x000fc800078e0209 */
/*0480*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, R10 ; /* 0x000000ffff098224 */
/* 0x000fca00078e000a */
/*0490*/ @!P4 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902c810 */
/* 0x001fe20007ffe0ff */
/*04a0*/ @!P4 FMUL R12, R12, R12 ; /* 0x0000000c0c0cc220 */
/* 0x004fc80000400000 */
/*04b0*/ @!P4 FFMA R12, R13, R13, R12 ; /* 0x0000000d0d0cc223 */
/* 0x008fca000000000c */
/*04c0*/ FSETP.GEU.AND P1, PT, R12, 1, !P4 ; /* 0x3f8000000c00780b */
/* 0x000fe2000672e000 */
/*04d0*/ @!P3 FMUL R14, R14, R14 ; /* 0x0000000e0e0eb220 */
/* 0x010fc80000400000 */
/*04e0*/ @!P3 FFMA R14, R15, R15, R14 ; /* 0x0000000f0f0eb223 */
/* 0x020fd0000000000e */
/*04f0*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0209 */
/*0500*/ FSETP.GEU.AND P0, PT, R14, 1, !P3 ; /* 0x3f8000000e00780b */
/* 0x000fe20005f0e000 */
/*0510*/ @!P2 FMUL R19, R19, R19 ; /* 0x000000131313a220 */
/* 0x000fe40000400000 */
/*0520*/ @!P4 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09c224 */
/* 0x000fe400078e0002 */
/*0530*/ @!P2 FFMA R19, R18, R18, R19 ; /* 0x000000121213a223 */
/* 0x000fc60000000013 */
/*0540*/ @!P3 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902b810 */
/* 0x000fe40007ffe0ff */
/*0550*/ FSETP.GEU.AND P1, PT, R19, 1, !P2 ; /* 0x3f8000001300780b */
/* 0x000fc6000572e000 */
/*0560*/ @P0 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff020224 */
/* 0x000fe400078e0209 */
/*0570*/ @!P5 FMUL R17, R17, R17 ; /* 0x000000111111d220 */
/* 0x000fe40000400000 */
/*0580*/ @!P3 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09b224 */
/* 0x000fe400078e0002 */
/*0590*/ @!P5 FFMA R17, R16, R16, R17 ; /* 0x000000101011d223 */
/* 0x000fc60000000011 */
/*05a0*/ @!P2 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902a810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ FSETP.GEU.AND P0, PT, R17, 1, !P5 ; /* 0x3f8000001100780b */
/* 0x000fe20006f0e000 */
/*05c0*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0209 */
/*05d0*/ @!P6 FMUL R20, R20, R20 ; /* 0x000000141414e220 */
/* 0x000fe40000400000 */
/*05e0*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09a224 */
/* 0x000fe400078e0002 */
/*05f0*/ @!P6 FFMA R20, R21, R21, R20 ; /* 0x000000151514e223 */
/* 0x000fc60000000014 */
/*0600*/ @!P5 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902d810 */
/* 0x000fe40007ffe0ff */
/*0610*/ FSETP.GEU.AND P1, PT, R20, 1, !P6 ; /* 0x3f8000001400780b */
/* 0x000fe2000772e000 */
/*0620*/ @P0 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff020224 */
/* 0x000fe200078e0209 */
/*0630*/ ISETP.NE.AND P0, PT, R23, 0x5fbfb80, PT ; /* 0x05fbfb801700780c */
/* 0x000fc60003f05270 */
/*0640*/ @!P5 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09d224 */
/* 0x000fca00078e0002 */
/*0650*/ @!P6 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902e810 */
/* 0x000fc60007ffe0ff */
/*0660*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fc800078e0209 */
/*0670*/ @!P6 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09e224 */
/* 0x000fe200078e0002 */
/*0680*/ @P0 BRA 0xb0 ; /* 0xfffffa2000000947 */
/* 0x000fea000383ffff */
/*0690*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0001e80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fca0003f05270 */
/*06c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd00008000000 */
/*06d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x001fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0700*/ LDS.128 R16, [UR4] ; /* 0x00000004ff107984 */
/* 0x000e220008000c00 */
/*0710*/ IADD3 R2, R2, 0x190, RZ ; /* 0x0000019002027810 */
/* 0x000fc60007ffe0ff */
/*0720*/ LDS.128 R12, [UR4+0x10] ; /* 0x00001004ff0c7984 */
/* 0x000e620008000c00 */
/*0730*/ ISETP.NE.AND P0, PT, R2, 0x7d8, PT ; /* 0x000007d80200780c */
/* 0x000fc60003f05270 */
/*0740*/ LDS.128 R8, [UR4+0x20] ; /* 0x00002004ff087984 */
/* 0x000ea80008000c00 */
/*0750*/ LDS.128 R24, [UR4+0x30] ; /* 0x00003004ff187984 */
/* 0x000ee80008000c00 */
/*0760*/ LDS.128 R4, [UR4+0x40] ; /* 0x00004004ff047984 */
/* 0x000f220008000c00 */
/*0770*/ IADD3 R16, R17, R16, R21 ; /* 0x0000001011107210 */
/* 0x001fc60007ffe015 */
/*0780*/ LDS.128 R20, [UR4+0x50] ; /* 0x00005004ff147984 */
/* 0x000e220008000c00 */
/*0790*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*07a0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x002fe40007ffe010 */
/*07b0*/ LDS.128 R16, [UR4+0x60] ; /* 0x00006004ff107984 */
/* 0x000e640008000c00 */
/*07c0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*07d0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x004fe40007ffe00c */
/*07e0*/ LDS.128 R12, [UR4+0x70] ; /* 0x00007004ff0c7984 */
/* 0x000ea40008000c00 */
/*07f0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0800*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x008fe40007ffe008 */
/*0810*/ LDS.128 R8, [UR4+0x80] ; /* 0x00008004ff087984 */
/* 0x000ee40008000c00 */
/*0820*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0830*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x010fe40007ffe018 */
/*0840*/ LDS.128 R24, [UR4+0x90] ; /* 0x00009004ff187984 */
/* 0x000f240008000c00 */
/*0850*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0860*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x001fe40007ffe004 */
/*0870*/ LDS.128 R4, [UR4+0xa0] ; /* 0x0000a004ff047984 */
/* 0x000e240008000c00 */
/*0880*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*0890*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x002fe40007ffe014 */
/*08a0*/ LDS.128 R20, [UR4+0xb0] ; /* 0x0000b004ff147984 */
/* 0x000e640008000c00 */
/*08b0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*08c0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x004fe40007ffe010 */
/*08d0*/ LDS.128 R16, [UR4+0xc0] ; /* 0x0000c004ff107984 */
/* 0x000ea40008000c00 */
/*08e0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*08f0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x008fe40007ffe00c */
/*0900*/ LDS.128 R12, [UR4+0xd0] ; /* 0x0000d004ff0c7984 */
/* 0x000ee40008000c00 */
/*0910*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0920*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x010fe40007ffe008 */
/*0930*/ LDS.128 R8, [UR4+0xe0] ; /* 0x0000e004ff087984 */
/* 0x000f240008000c00 */
/*0940*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0950*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x001fe40007ffe018 */
/*0960*/ LDS.128 R24, [UR4+0xf0] ; /* 0x0000f004ff187984 */
/* 0x000e240008000c00 */
/*0970*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0980*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x002fe40007ffe004 */
/*0990*/ LDS.128 R4, [UR4+0x100] ; /* 0x00010004ff047984 */
/* 0x000e640008000c00 */
/*09a0*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*09b0*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x004fe40007ffe014 */
/*09c0*/ LDS.128 R20, [UR4+0x110] ; /* 0x00011004ff147984 */
/* 0x000ea40008000c00 */
/*09d0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*09e0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x008fe40007ffe010 */
/*09f0*/ LDS.128 R16, [UR4+0x120] ; /* 0x00012004ff107984 */
/* 0x000ee40008000c00 */
/*0a00*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*0a10*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x010fe40007ffe00c */
/*0a20*/ LDS.128 R12, [UR4+0x130] ; /* 0x00013004ff0c7984 */
/* 0x000f240008000c00 */
/*0a30*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0a40*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x001fe40007ffe008 */
/*0a50*/ LDS.128 R8, [UR4+0x140] ; /* 0x00014004ff087984 */
/* 0x000e240008000c00 */
/*0a60*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0a70*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x002fe40007ffe018 */
/*0a80*/ LDS.128 R24, [UR4+0x150] ; /* 0x00015004ff187984 */
/* 0x000e640008000c00 */
/*0a90*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0aa0*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x004fe40007ffe004 */
/*0ab0*/ LDS.128 R4, [UR4+0x160] ; /* 0x00016004ff047984 */
/* 0x000ea40008000c00 */
/*0ac0*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*0ad0*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x008fe40007ffe014 */
/*0ae0*/ LDS.128 R20, [UR4+0x170] ; /* 0x00017004ff147984 */
/* 0x000ee40008000c00 */
/*0af0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*0b00*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x010fe40007ffe010 */
/*0b10*/ LDS.128 R16, [UR4+0x180] ; /* 0x00018004ff107984 */
/* 0x000f220008000c00 */
/*0b20*/ UIADD3 UR4, UR4, 0x190, URZ ; /* 0x0000019004047890 */
/* 0x000fe2000fffe03f */
/*0b30*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*0b40*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x001fc80007ffe00c */
/*0b50*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0b60*/ IADD3 R8, R25, R24, R8 ; /* 0x0000001819087210 */
/* 0x002fc80007ffe008 */
/*0b70*/ IADD3 R8, R27, R26, R8 ; /* 0x0000001a1b087210 */
/* 0x000fc80007ffe008 */
/*0b80*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x004fc80007ffe008 */
/*0b90*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0ba0*/ IADD3 R4, R21, R20, R4 ; /* 0x0000001415047210 */
/* 0x008fc80007ffe004 */
/*0bb0*/ IADD3 R4, R23, R22, R4 ; /* 0x0000001617047210 */
/* 0x000fc80007ffe004 */
/*0bc0*/ IADD3 R16, R17, R16, R4 ; /* 0x0000001011107210 */
/* 0x010fc80007ffe004 */
/*0bd0*/ IADD3 R21, R19, R18, R16 ; /* 0x0000001213157210 */
/* 0x000fe20007ffe010 */
/*0be0*/ @P0 BRA 0x700 ; /* 0xfffffb1000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0c00*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0c10*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} | .file "tmpxft_000c1527_00000000-6_pi_optimized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
.type _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi, @function
_Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12pi_optimizedPfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi, .-_Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
.globl _Z12pi_optimizedPfS_Pi
.type _Z12pi_optimizedPfS_Pi, @function
_Z12pi_optimizedPfS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12pi_optimizedPfS_Pi, .-_Z12pi_optimizedPfS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12pi_optimizedPfS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12pi_optimizedPfS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12pi_optimizedPfS_Pi
.globl _Z12pi_optimizedPfS_Pi
.p2align 8
.type _Z12pi_optimizedPfS_Pi,@function
_Z12pi_optimizedPfS_Pi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s3, s3, 0x186a0
s_cmp_eq_u32 s3, 0x5f5e100
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s3, v1
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e32 0x5f5e100, v2
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, v5, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v2
v_cmpx_gt_f32_e32 1.0, v3
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v4, 1, v4
s_branch .LBB0_1
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
.LBB0_8:
v_mov_b32_e32 v1, s3
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s3, 0x7d0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12pi_optimizedPfS_Pi
.amdhsa_group_segment_fixed_size 2000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12pi_optimizedPfS_Pi, .Lfunc_end0-_Z12pi_optimizedPfS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2000
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12pi_optimizedPfS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12pi_optimizedPfS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pi_optimized(float* x, float* y, int* global_count) {
__shared__ int counts[nthreads];
//int globalId = blockIdx.x * blockDim.x + nitemsperthread * threadIdx.x;
int globalId = blockIdx.x * blockDim.x + threadIdx.x;
int thread_count=0;
for (int i=0; i<nitemsperthread; i++) {
int idx = globalId+(i*nthreads*nblocks);
if (idx < nsamples) {
if (x[idx]*x[idx] + y[idx]*y[idx] < 1.0) {
thread_count++;
}
}
}
counts[threadIdx.x] = thread_count;
__syncthreads();
if (threadIdx.x == 0) {
int block_count = 0;
for (int i=0; i<nthreads; i++) {
block_count += counts[i];
}
global_count[blockIdx.x] = block_count;
}
} | .text
.file "pi_optimized.hip"
.globl _Z27__device_stub__pi_optimizedPfS_Pi # -- Begin function _Z27__device_stub__pi_optimizedPfS_Pi
.p2align 4, 0x90
.type _Z27__device_stub__pi_optimizedPfS_Pi,@function
_Z27__device_stub__pi_optimizedPfS_Pi: # @_Z27__device_stub__pi_optimizedPfS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12pi_optimizedPfS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__pi_optimizedPfS_Pi, .Lfunc_end0-_Z27__device_stub__pi_optimizedPfS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12pi_optimizedPfS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12pi_optimizedPfS_Pi,@object # @_Z12pi_optimizedPfS_Pi
.section .rodata,"a",@progbits
.globl _Z12pi_optimizedPfS_Pi
.p2align 3, 0x0
_Z12pi_optimizedPfS_Pi:
.quad _Z27__device_stub__pi_optimizedPfS_Pi
.size _Z12pi_optimizedPfS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12pi_optimizedPfS_Pi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__pi_optimizedPfS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12pi_optimizedPfS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12pi_optimizedPfS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R23, RZ, RZ, 0x61a80 ; /* 0x00061a80ff177424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0060*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R7, R0, c[0x0][0x0], RZ ; /* 0x0000000000077a24 */
/* 0x001fc800078e02ff */
/*0090*/ IMAD.IADD R8, R7, 0x1, R6 ; /* 0x0000000107087824 */
/* 0x002fca00078e0206 */
/*00a0*/ IADD3 R22, R8, 0xaae60, RZ ; /* 0x000aae6008167810 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD.IADD R2, R6, 0x1, R7 ; /* 0x0000000106027824 */
/* 0x000fe200078e0207 */
/*00c0*/ IADD3 R10, R22, -0x927c0, RZ ; /* 0xfff6d840160a7810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*00e0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fe2000f8e00ff */
/*00f0*/ ISETP.GT.AND P5, PT, R2, 0x5f5e0ff, PT ; /* 0x05f5e0ff0200780c */
/* 0x000fe20003fa4270 */
/*0100*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe4000f8e00ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe4000f8e00ff */
/*0120*/ IMAD.WIDE R4, R8, 0x4, R4 ; /* 0x0000000408047825 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R2, R8, 0x4, R2 ; /* 0x0000000408027825 */
/* 0x000fe200078e0202 */
/*0140*/ ISETP.GT.AND P1, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fc60003f24270 */
/*0150*/ @!P5 LDG.E R12, [R4.64] ; /* 0x00000006040cd981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P5 LDG.E R13, [R2.64] ; /* 0x00000006020dd981 */
/* 0x000eec000c1e1900 */
/*0170*/ @!P1 LDG.E R16, [R4.64+0x61a80] ; /* 0x061a800604109981 */
/* 0x000f28000c1e1900 */
/*0180*/ @!P1 LDG.E R15, [R2.64+0x61a80] ; /* 0x061a8006020f9981 */
/* 0x000f62000c1e1900 */
/*0190*/ IADD3 R10, R22, -0x7a120, RZ ; /* 0xfff85ee0160a7810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3 R10, R22, -0x61a80, RZ ; /* 0xfff9e580160a7810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GT.AND P4, PT, R10, 0x5f5e0ff, PT ; /* 0x05f5e0ff0a00780c */
/* 0x000fce0003f84270 */
/*01d0*/ @!P0 LDG.E R10, [R4.64+0xc3500] ; /* 0x0c350006040a8981 */
/* 0x000f62000c1e1900 */
/*01e0*/ IADD3 R17, R22, -0x493e0, RZ ; /* 0xfffb6c2016117810 */
/* 0x000fc60007ffe0ff */
/*01f0*/ @!P0 LDG.E R11, [R2.64+0xc3500] ; /* 0x0c350006020b8981 */
/* 0x000f62000c1e1900 */
/*0200*/ ISETP.GT.AND P3, PT, R17, 0x5f5e0ff, PT ; /* 0x05f5e0ff1100780c */
/* 0x000fe40003f64270 */
/*0210*/ IADD3 R17, R22, -0x186a0, RZ ; /* 0xfffe796016117810 */
/* 0x000fe20007ffe0ff */
/*0220*/ @!P5 FMUL R14, R12, R12 ; /* 0x0000000c0c0ed220 */
/* 0x004fe40000400000 */
/*0230*/ @!P4 LDG.E R12, [R4.64+0x124f80] ; /* 0x124f8006040cc981 */
/* 0x000ea4000c1e1900 */
/*0240*/ @!P5 FFMA R14, R13, R13, R14 ; /* 0x0000000d0d0ed223 */
/* 0x008fe4000000000e */
/*0250*/ @!P4 LDG.E R13, [R2.64+0x124f80] ; /* 0x124f8006020dc981 */
/* 0x0000e6000c1e1900 */
/*0260*/ FSETP.GEU.AND P6, PT, R14, 1, !P5 ; /* 0x3f8000000e00780b */
/* 0x000fe20006fce000 */
/*0270*/ @!P1 FMUL R18, R16, R16 ; /* 0x0000001010129220 */
/* 0x010fe20000400000 */
/*0280*/ IADD3 R14, R22, -0x30d40, RZ ; /* 0xfffcf2c0160e7810 */
/* 0x000fc80007ffe0ff */
/*0290*/ ISETP.GT.AND P2, PT, R14, 0x5f5e0ff, PT ; /* 0x05f5e0ff0e00780c */
/* 0x000fe20003f44270 */
/*02a0*/ @!P1 FFMA R18, R15, R15, R18 ; /* 0x0000000f0f129223 */
/* 0x020fe20000000012 */
/*02b0*/ @!P3 LDG.E R14, [R4.64+0x186a00] ; /* 0x186a0006040eb981 */
/* 0x000f22000c1e1900 */
/*02c0*/ @!P5 IADD3 R16, R9, 0x1, RZ ; /* 0x000000010910d810 */
/* 0x000fc60007ffe0ff */
/*02d0*/ @!P3 LDG.E R15, [R2.64+0x186a00] ; /* 0x186a0006020fb981 */
/* 0x000162000c1e1900 */
/*02e0*/ @P6 IMAD.MOV R16, RZ, RZ, R9 ; /* 0x000000ffff106224 */
/* 0x000fe200078e0209 */
/*02f0*/ FSETP.GEU.AND P6, PT, R18, 1, !P1 ; /* 0x3f8000001200780b */
/* 0x000fc60004fce000 */
/*0300*/ @!P5 IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff09d224 */
/* 0x000fe200078e0010 */
/*0310*/ ISETP.GT.AND P5, PT, R17, 0x5f5e0ff, PT ; /* 0x05f5e0ff1100780c */
/* 0x000fe20003fa4270 */
/*0320*/ @!P2 LDG.E R19, [R4.64+0x1e8480] ; /* 0x1e8480060413a981 */
/* 0x000f68000c1e1900 */
/*0330*/ @!P2 LDG.E R18, [R2.64+0x1e8480] ; /* 0x1e8480060212a981 */
/* 0x000162000c1e1900 */
/*0340*/ @!P1 IADD3 R24, R9, 0x1, RZ ; /* 0x0000000109189810 */
/* 0x000fc60007ffe0ff */
/*0350*/ @P6 IMAD.MOV R24, RZ, RZ, R9 ; /* 0x000000ffff186224 */
/* 0x000fe200078e0209 */
/*0360*/ ISETP.GT.AND P6, PT, R22, 0x5f5e0ff, PT ; /* 0x05f5e0ff1600780c */
/* 0x000fc60003fc4270 */
/*0370*/ @!P5 LDG.E R17, [R4.64+0x249f00] ; /* 0x249f00060411d981 */
/* 0x000f68000c1e1900 */
/*0380*/ @!P5 LDG.E R16, [R2.64+0x249f00] ; /* 0x249f00060210d981 */
/* 0x00016c000c1e1900 */
/*0390*/ @!P6 LDG.E R20, [R4.64+0x2ab980] ; /* 0x2ab980060414e981 */
/* 0x000f68000c1e1900 */
/*03a0*/ @!P6 LDG.E R21, [R2.64+0x2ab980] ; /* 0x2ab980060215e981 */
/* 0x000162000c1e1900 */
/*03b0*/ @!P0 FMUL R10, R10, R10 ; /* 0x0000000a0a0a8220 */
/* 0x000fe20000400000 */
/*03c0*/ IADD3 R23, R23, 0xc3500, RZ ; /* 0x000c350017177810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R24 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0018 */
/*03e0*/ UIADD3 UR8, UP0, UR8, 0x30d400, URZ ; /* 0x0030d40008087890 */
/* 0x000fe2000ff1e03f */
/*03f0*/ @!P0 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a8223 */
/* 0x000fe2000000000a */
/*0400*/ UIADD3 UR4, UP1, UR4, 0x30d400, URZ ; /* 0x0030d40004047890 */
/* 0x000fe2000ff3e03f */
/*0410*/ IADD3 R22, R22, 0xc3500, RZ ; /* 0x000c350016167810 */
/* 0x000fe20007ffe0ff */
/*0420*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3 R7, R7, 0xc3500, RZ ; /* 0x000c350007077810 */
/* 0x000fe20007ffe0ff */
/*0440*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*0450*/ FSETP.GEU.AND P1, PT, R10, 1, !P0 ; /* 0x3f8000000a00780b */
/* 0x000fc4000472e000 */
/*0460*/ @!P0 IADD3 R10, R9, 0x1, RZ ; /* 0x00000001090a8810 */
/* 0x000fd60007ffe0ff */
/*0470*/ @P1 IMAD.MOV R10, RZ, RZ, R9 ; /* 0x000000ffff0a1224 */
/* 0x000fc800078e0209 */
/*0480*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, R10 ; /* 0x000000ffff098224 */
/* 0x000fca00078e000a */
/*0490*/ @!P4 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902c810 */
/* 0x001fe20007ffe0ff */
/*04a0*/ @!P4 FMUL R12, R12, R12 ; /* 0x0000000c0c0cc220 */
/* 0x004fc80000400000 */
/*04b0*/ @!P4 FFMA R12, R13, R13, R12 ; /* 0x0000000d0d0cc223 */
/* 0x008fca000000000c */
/*04c0*/ FSETP.GEU.AND P1, PT, R12, 1, !P4 ; /* 0x3f8000000c00780b */
/* 0x000fe2000672e000 */
/*04d0*/ @!P3 FMUL R14, R14, R14 ; /* 0x0000000e0e0eb220 */
/* 0x010fc80000400000 */
/*04e0*/ @!P3 FFMA R14, R15, R15, R14 ; /* 0x0000000f0f0eb223 */
/* 0x020fd0000000000e */
/*04f0*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0209 */
/*0500*/ FSETP.GEU.AND P0, PT, R14, 1, !P3 ; /* 0x3f8000000e00780b */
/* 0x000fe20005f0e000 */
/*0510*/ @!P2 FMUL R19, R19, R19 ; /* 0x000000131313a220 */
/* 0x000fe40000400000 */
/*0520*/ @!P4 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09c224 */
/* 0x000fe400078e0002 */
/*0530*/ @!P2 FFMA R19, R18, R18, R19 ; /* 0x000000121213a223 */
/* 0x000fc60000000013 */
/*0540*/ @!P3 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902b810 */
/* 0x000fe40007ffe0ff */
/*0550*/ FSETP.GEU.AND P1, PT, R19, 1, !P2 ; /* 0x3f8000001300780b */
/* 0x000fc6000572e000 */
/*0560*/ @P0 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff020224 */
/* 0x000fe400078e0209 */
/*0570*/ @!P5 FMUL R17, R17, R17 ; /* 0x000000111111d220 */
/* 0x000fe40000400000 */
/*0580*/ @!P3 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09b224 */
/* 0x000fe400078e0002 */
/*0590*/ @!P5 FFMA R17, R16, R16, R17 ; /* 0x000000101011d223 */
/* 0x000fc60000000011 */
/*05a0*/ @!P2 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902a810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ FSETP.GEU.AND P0, PT, R17, 1, !P5 ; /* 0x3f8000001100780b */
/* 0x000fe20006f0e000 */
/*05c0*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0209 */
/*05d0*/ @!P6 FMUL R20, R20, R20 ; /* 0x000000141414e220 */
/* 0x000fe40000400000 */
/*05e0*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09a224 */
/* 0x000fe400078e0002 */
/*05f0*/ @!P6 FFMA R20, R21, R21, R20 ; /* 0x000000151514e223 */
/* 0x000fc60000000014 */
/*0600*/ @!P5 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902d810 */
/* 0x000fe40007ffe0ff */
/*0610*/ FSETP.GEU.AND P1, PT, R20, 1, !P6 ; /* 0x3f8000001400780b */
/* 0x000fe2000772e000 */
/*0620*/ @P0 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff020224 */
/* 0x000fe200078e0209 */
/*0630*/ ISETP.NE.AND P0, PT, R23, 0x5fbfb80, PT ; /* 0x05fbfb801700780c */
/* 0x000fc60003f05270 */
/*0640*/ @!P5 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09d224 */
/* 0x000fca00078e0002 */
/*0650*/ @!P6 IADD3 R2, R9, 0x1, RZ ; /* 0x000000010902e810 */
/* 0x000fc60007ffe0ff */
/*0660*/ @P1 IMAD.MOV R2, RZ, RZ, R9 ; /* 0x000000ffff021224 */
/* 0x000fc800078e0209 */
/*0670*/ @!P6 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff09e224 */
/* 0x000fe200078e0002 */
/*0680*/ @P0 BRA 0xb0 ; /* 0xfffffa2000000947 */
/* 0x000fea000383ffff */
/*0690*/ STS [R6.X4], R9 ; /* 0x0000000906007388 */
/* 0x0001e80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fca0003f05270 */
/*06c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd00008000000 */
/*06d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x001fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0700*/ LDS.128 R16, [UR4] ; /* 0x00000004ff107984 */
/* 0x000e220008000c00 */
/*0710*/ IADD3 R2, R2, 0x190, RZ ; /* 0x0000019002027810 */
/* 0x000fc60007ffe0ff */
/*0720*/ LDS.128 R12, [UR4+0x10] ; /* 0x00001004ff0c7984 */
/* 0x000e620008000c00 */
/*0730*/ ISETP.NE.AND P0, PT, R2, 0x7d8, PT ; /* 0x000007d80200780c */
/* 0x000fc60003f05270 */
/*0740*/ LDS.128 R8, [UR4+0x20] ; /* 0x00002004ff087984 */
/* 0x000ea80008000c00 */
/*0750*/ LDS.128 R24, [UR4+0x30] ; /* 0x00003004ff187984 */
/* 0x000ee80008000c00 */
/*0760*/ LDS.128 R4, [UR4+0x40] ; /* 0x00004004ff047984 */
/* 0x000f220008000c00 */
/*0770*/ IADD3 R16, R17, R16, R21 ; /* 0x0000001011107210 */
/* 0x001fc60007ffe015 */
/*0780*/ LDS.128 R20, [UR4+0x50] ; /* 0x00005004ff147984 */
/* 0x000e220008000c00 */
/*0790*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*07a0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x002fe40007ffe010 */
/*07b0*/ LDS.128 R16, [UR4+0x60] ; /* 0x00006004ff107984 */
/* 0x000e640008000c00 */
/*07c0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*07d0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x004fe40007ffe00c */
/*07e0*/ LDS.128 R12, [UR4+0x70] ; /* 0x00007004ff0c7984 */
/* 0x000ea40008000c00 */
/*07f0*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0800*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x008fe40007ffe008 */
/*0810*/ LDS.128 R8, [UR4+0x80] ; /* 0x00008004ff087984 */
/* 0x000ee40008000c00 */
/*0820*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0830*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x010fe40007ffe018 */
/*0840*/ LDS.128 R24, [UR4+0x90] ; /* 0x00009004ff187984 */
/* 0x000f240008000c00 */
/*0850*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0860*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x001fe40007ffe004 */
/*0870*/ LDS.128 R4, [UR4+0xa0] ; /* 0x0000a004ff047984 */
/* 0x000e240008000c00 */
/*0880*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*0890*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x002fe40007ffe014 */
/*08a0*/ LDS.128 R20, [UR4+0xb0] ; /* 0x0000b004ff147984 */
/* 0x000e640008000c00 */
/*08b0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*08c0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x004fe40007ffe010 */
/*08d0*/ LDS.128 R16, [UR4+0xc0] ; /* 0x0000c004ff107984 */
/* 0x000ea40008000c00 */
/*08e0*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*08f0*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x008fe40007ffe00c */
/*0900*/ LDS.128 R12, [UR4+0xd0] ; /* 0x0000d004ff0c7984 */
/* 0x000ee40008000c00 */
/*0910*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0920*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x010fe40007ffe008 */
/*0930*/ LDS.128 R8, [UR4+0xe0] ; /* 0x0000e004ff087984 */
/* 0x000f240008000c00 */
/*0940*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0950*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x001fe40007ffe018 */
/*0960*/ LDS.128 R24, [UR4+0xf0] ; /* 0x0000f004ff187984 */
/* 0x000e240008000c00 */
/*0970*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0980*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x002fe40007ffe004 */
/*0990*/ LDS.128 R4, [UR4+0x100] ; /* 0x00010004ff047984 */
/* 0x000e640008000c00 */
/*09a0*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*09b0*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x004fe40007ffe014 */
/*09c0*/ LDS.128 R20, [UR4+0x110] ; /* 0x00011004ff147984 */
/* 0x000ea40008000c00 */
/*09d0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*09e0*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x008fe40007ffe010 */
/*09f0*/ LDS.128 R16, [UR4+0x120] ; /* 0x00012004ff107984 */
/* 0x000ee40008000c00 */
/*0a00*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*0a10*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x010fe40007ffe00c */
/*0a20*/ LDS.128 R12, [UR4+0x130] ; /* 0x00013004ff0c7984 */
/* 0x000f240008000c00 */
/*0a30*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0a40*/ IADD3 R24, R25, R24, R8 ; /* 0x0000001819187210 */
/* 0x001fe40007ffe008 */
/*0a50*/ LDS.128 R8, [UR4+0x140] ; /* 0x00014004ff087984 */
/* 0x000e240008000c00 */
/*0a60*/ IADD3 R24, R27, R26, R24 ; /* 0x0000001a1b187210 */
/* 0x000fc80007ffe018 */
/*0a70*/ IADD3 R4, R5, R4, R24 ; /* 0x0000000405047210 */
/* 0x002fe40007ffe018 */
/*0a80*/ LDS.128 R24, [UR4+0x150] ; /* 0x00015004ff187984 */
/* 0x000e640008000c00 */
/*0a90*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0aa0*/ IADD3 R20, R21, R20, R4 ; /* 0x0000001415147210 */
/* 0x004fe40007ffe004 */
/*0ab0*/ LDS.128 R4, [UR4+0x160] ; /* 0x00016004ff047984 */
/* 0x000ea40008000c00 */
/*0ac0*/ IADD3 R20, R23, R22, R20 ; /* 0x0000001617147210 */
/* 0x000fc80007ffe014 */
/*0ad0*/ IADD3 R16, R17, R16, R20 ; /* 0x0000001011107210 */
/* 0x008fe40007ffe014 */
/*0ae0*/ LDS.128 R20, [UR4+0x170] ; /* 0x00017004ff147984 */
/* 0x000ee40008000c00 */
/*0af0*/ IADD3 R16, R19, R18, R16 ; /* 0x0000001213107210 */
/* 0x000fc80007ffe010 */
/*0b00*/ IADD3 R12, R13, R12, R16 ; /* 0x0000000c0d0c7210 */
/* 0x010fe40007ffe010 */
/*0b10*/ LDS.128 R16, [UR4+0x180] ; /* 0x00018004ff107984 */
/* 0x000f220008000c00 */
/*0b20*/ UIADD3 UR4, UR4, 0x190, URZ ; /* 0x0000019004047890 */
/* 0x000fe2000fffe03f */
/*0b30*/ IADD3 R12, R15, R14, R12 ; /* 0x0000000e0f0c7210 */
/* 0x000fc80007ffe00c */
/*0b40*/ IADD3 R8, R9, R8, R12 ; /* 0x0000000809087210 */
/* 0x001fc80007ffe00c */
/*0b50*/ IADD3 R8, R11, R10, R8 ; /* 0x0000000a0b087210 */
/* 0x000fc80007ffe008 */
/*0b60*/ IADD3 R8, R25, R24, R8 ; /* 0x0000001819087210 */
/* 0x002fc80007ffe008 */
/*0b70*/ IADD3 R8, R27, R26, R8 ; /* 0x0000001a1b087210 */
/* 0x000fc80007ffe008 */
/*0b80*/ IADD3 R4, R5, R4, R8 ; /* 0x0000000405047210 */
/* 0x004fc80007ffe008 */
/*0b90*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0ba0*/ IADD3 R4, R21, R20, R4 ; /* 0x0000001415047210 */
/* 0x008fc80007ffe004 */
/*0bb0*/ IADD3 R4, R23, R22, R4 ; /* 0x0000001617047210 */
/* 0x000fc80007ffe004 */
/*0bc0*/ IADD3 R16, R17, R16, R4 ; /* 0x0000001011107210 */
/* 0x010fc80007ffe004 */
/*0bd0*/ IADD3 R21, R19, R18, R16 ; /* 0x0000001213157210 */
/* 0x000fe20007ffe010 */
/*0be0*/ @P0 BRA 0x700 ; /* 0xfffffb1000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0c00*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0c10*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12pi_optimizedPfS_Pi
.globl _Z12pi_optimizedPfS_Pi
.p2align 8
.type _Z12pi_optimizedPfS_Pi,@function
_Z12pi_optimizedPfS_Pi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s3, s3, 0x186a0
s_cmp_eq_u32 s3, 0x5f5e100
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s3, v1
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e32 0x5f5e100, v2
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, v5, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v2
v_cmpx_gt_f32_e32 1.0, v3
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v4, 1, v4
s_branch .LBB0_1
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
.LBB0_8:
v_mov_b32_e32 v1, s3
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s3, 0x7d0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12pi_optimizedPfS_Pi
.amdhsa_group_segment_fixed_size 2000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12pi_optimizedPfS_Pi, .Lfunc_end0-_Z12pi_optimizedPfS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2000
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12pi_optimizedPfS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12pi_optimizedPfS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1527_00000000-6_pi_optimized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
.type _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi, @function
_Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12pi_optimizedPfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi, .-_Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
.globl _Z12pi_optimizedPfS_Pi
.type _Z12pi_optimizedPfS_Pi, @function
_Z12pi_optimizedPfS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12pi_optimizedPfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12pi_optimizedPfS_Pi, .-_Z12pi_optimizedPfS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12pi_optimizedPfS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12pi_optimizedPfS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi_optimized.hip"
.globl _Z27__device_stub__pi_optimizedPfS_Pi # -- Begin function _Z27__device_stub__pi_optimizedPfS_Pi
.p2align 4, 0x90
.type _Z27__device_stub__pi_optimizedPfS_Pi,@function
_Z27__device_stub__pi_optimizedPfS_Pi: # @_Z27__device_stub__pi_optimizedPfS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12pi_optimizedPfS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__pi_optimizedPfS_Pi, .Lfunc_end0-_Z27__device_stub__pi_optimizedPfS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12pi_optimizedPfS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12pi_optimizedPfS_Pi,@object # @_Z12pi_optimizedPfS_Pi
.section .rodata,"a",@progbits
.globl _Z12pi_optimizedPfS_Pi
.p2align 3, 0x0
_Z12pi_optimizedPfS_Pi:
.quad _Z27__device_stub__pi_optimizedPfS_Pi
.size _Z12pi_optimizedPfS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12pi_optimizedPfS_Pi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__pi_optimizedPfS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12pi_optimizedPfS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <malloc.h>
__global__ void add(int *x, int *y, int *z)
{
*z = *x + *y;
printf("z is %d\n", *z);
}
int main()
{
//Declaration
int *a, *b, *c;
int *deva, *devb, *devc;
//Dynamic Memory Allocation in Host
a = (int *)malloc(sizeof(int));
b = (int *)malloc(sizeof(int));
c = (int *)malloc(sizeof(int));
//Reserving Memory in Device
cudaMalloc((int **)&deva, sizeof(int));
cudaMalloc((int **)&devb, sizeof(int));
cudaMalloc((int **)&devc, sizeof(int));
//Inputting values from user
printf("Enter value of a and b\n");
scanf("%d %d", a, b);
/**c = *a + *b;
printf("answer: %d\n", *c);*/
//Coping values from HostToDevice
cudaMemcpy(deva, a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(devb, b, sizeof(int), cudaMemcpyHostToDevice);
//Calling Kernel
add<<<1,1>>>(deva, devb, devc);
//Coping values from DeviceToHost
cudaMemcpy(c, devc, sizeof(int), cudaMemcpyDeviceToHost);
printf("Result is: %d\n", *c);
//Free-up the memory
cudaFree(deva), cudaFree(devb), cudaFree(devc);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fc600078e00ff */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R12, 0x0 ; /* 0x00000000000c7802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ LDC.64 R12, c[0x4][R12] ; /* 0x010000000c0c7b82 */
/* 0x000e220000000a00 */
/*00f0*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fc40000000f00 */
/*0100*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0110*/ IMAD.IADD R0, R0, 0x1, R9 ; /* 0x0000000100007824 */
/* 0x004fca00078e0209 */
/*0120*/ STG.E [R10.64], R0 ; /* 0x000000000a007986 */
/* 0x0003e8000c101904 */
/*0130*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*0140*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe40000000000 */
/*0150*/ MOV R9, 0x1c0 ; /* 0x000001c000097802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fc40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01a0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01b0*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <malloc.h>
__global__ void add(int *x, int *y, int *z)
{
*z = *x + *y;
printf("z is %d\n", *z);
}
int main()
{
//Declaration
int *a, *b, *c;
int *deva, *devb, *devc;
//Dynamic Memory Allocation in Host
a = (int *)malloc(sizeof(int));
b = (int *)malloc(sizeof(int));
c = (int *)malloc(sizeof(int));
//Reserving Memory in Device
cudaMalloc((int **)&deva, sizeof(int));
cudaMalloc((int **)&devb, sizeof(int));
cudaMalloc((int **)&devc, sizeof(int));
//Inputting values from user
printf("Enter value of a and b\n");
scanf("%d %d", a, b);
/**c = *a + *b;
printf("answer: %d\n", *c);*/
//Coping values from HostToDevice
cudaMemcpy(deva, a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(devb, b, sizeof(int), cudaMemcpyHostToDevice);
//Calling Kernel
add<<<1,1>>>(deva, devb, devc);
//Coping values from DeviceToHost
cudaMemcpy(c, devc, sizeof(int), cudaMemcpyDeviceToHost);
printf("Result is: %d\n", *c);
//Free-up the memory
cudaFree(deva), cudaFree(devb), cudaFree(devc);
return 0;
} | .file "tmpxft_0004d3e8_00000000-6_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of a and b\n"
.LC1:
.string "%d %d"
.LC2:
.string "Result is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r12, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <malloc.h>
__global__ void add(int *x, int *y, int *z)
{
*z = *x + *y;
printf("z is %d\n", *z);
}
int main()
{
//Declaration
int *a, *b, *c;
int *deva, *devb, *devc;
//Dynamic Memory Allocation in Host
a = (int *)malloc(sizeof(int));
b = (int *)malloc(sizeof(int));
c = (int *)malloc(sizeof(int));
//Reserving Memory in Device
cudaMalloc((int **)&deva, sizeof(int));
cudaMalloc((int **)&devb, sizeof(int));
cudaMalloc((int **)&devc, sizeof(int));
//Inputting values from user
printf("Enter value of a and b\n");
scanf("%d %d", a, b);
/**c = *a + *b;
printf("answer: %d\n", *c);*/
//Coping values from HostToDevice
cudaMemcpy(deva, a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(devb, b, sizeof(int), cudaMemcpyHostToDevice);
//Calling Kernel
add<<<1,1>>>(deva, devb, devc);
//Coping values from DeviceToHost
cudaMemcpy(c, devc, sizeof(int), cudaMemcpyDeviceToHost);
printf("Result is: %d\n", *c);
//Free-up the memory
cudaFree(deva), cudaFree(devb), cudaFree(devc);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <malloc.h>
__global__ void add(int *x, int *y, int *z)
{
*z = *x + *y;
printf("z is %d\n", *z);
}
int main()
{
//Declaration
int *a, *b, *c;
int *deva, *devb, *devc;
//Dynamic Memory Allocation in Host
a = (int *)malloc(sizeof(int));
b = (int *)malloc(sizeof(int));
c = (int *)malloc(sizeof(int));
//Reserving Memory in Device
hipMalloc((int **)&deva, sizeof(int));
hipMalloc((int **)&devb, sizeof(int));
hipMalloc((int **)&devc, sizeof(int));
//Inputting values from user
printf("Enter value of a and b\n");
scanf("%d %d", a, b);
/**c = *a + *b;
printf("answer: %d\n", *c);*/
//Coping values from HostToDevice
hipMemcpy(deva, a, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(devb, b, sizeof(int), hipMemcpyHostToDevice);
//Calling Kernel
add<<<1,1>>>(deva, devb, devc);
//Coping values from DeviceToHost
hipMemcpy(c, devc, sizeof(int), hipMemcpyDeviceToHost);
printf("Result is: %d\n", *c);
//Free-up the memory
hipFree(deva), hipFree(devb), hipFree(devc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <malloc.h>
__global__ void add(int *x, int *y, int *z)
{
*z = *x + *y;
printf("z is %d\n", *z);
}
int main()
{
//Declaration
int *a, *b, *c;
int *deva, *devb, *devc;
//Dynamic Memory Allocation in Host
a = (int *)malloc(sizeof(int));
b = (int *)malloc(sizeof(int));
c = (int *)malloc(sizeof(int));
//Reserving Memory in Device
hipMalloc((int **)&deva, sizeof(int));
hipMalloc((int **)&devb, sizeof(int));
hipMalloc((int **)&devc, sizeof(int));
//Inputting values from user
printf("Enter value of a and b\n");
scanf("%d %d", a, b);
/**c = *a + *b;
printf("answer: %d\n", *c);*/
//Coping values from HostToDevice
hipMemcpy(deva, a, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(devb, b, sizeof(int), hipMemcpyHostToDevice);
//Calling Kernel
add<<<1,1>>>(deva, devb, devc);
//Coping values from DeviceToHost
hipMemcpy(c, devc, sizeof(int), hipMemcpyDeviceToHost);
printf("Result is: %d\n", *c);
//Free-up the memory
hipFree(deva), hipFree(devb), hipFree(devc);
return 0;
} | .text
.file "Addition.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4, %edi
callq malloc
movq %rax, %r15
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %r15, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_scanf
movq 16(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Result is: %d\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter value of a and b"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d3e8_00000000-6_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of a and b\n"
.LC1:
.string "%d %d"
.LC2:
.string "Result is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r12, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Addition.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4, %edi
callq malloc
movq %rax, %r15
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %r15, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_scanf
movq 16(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Result is: %d\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter value of a and b"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H | .file "tmpxft_00049bee_00000000-6_Phase.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_PHASE_H
#define AXONBITS_PHASE_H
enum Phase { ExpectationPhase, OutcomePhase };
#endif //AXONBITS_PHASE_H | .text
.file "Phase.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00049bee_00000000-6_Phase.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Phase.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<cuda.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
cudaMalloc(&d_a, sizeof(int)); //malloc space in device
cudaMalloc(&d_b, sizeof(int)); //malloc space in device
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
cudaMemcpy(d_b, &b, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost); //copy the result from device ram back to main memory
cudaFree(d_a); //free device space
cudaFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R2, R7, RZ ; /* 0x0000000702077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<cuda.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
cudaMalloc(&d_a, sizeof(int)); //malloc space in device
cudaMalloc(&d_b, sizeof(int)); //malloc space in device
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
cudaMemcpy(d_b, &b, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost); //copy the result from device ram back to main memory
cudaFree(d_a); //free device space
cudaFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} | .file "tmpxft_001ab10f_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12time_elapsedP8timespecS0_
.type _Z12time_elapsedP8timespecS0_, @function
_Z12time_elapsedP8timespecS0_:
.LFB2057:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq 8(%rsi), %rax
subq 8(%rdi), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
addsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z12time_elapsedP8timespecS0_, .-_Z12time_elapsedP8timespecS0_
.globl _Z7CPU_ADDii
.type _Z7CPU_ADDii, @function
_Z7CPU_ADDii:
.LFB2059:
.cfi_startproc
endbr64
leal (%rdi,%rsi), %eax
ret
.cfi_endproc
.LFE2059:
.size _Z7CPU_ADDii, .-_Z7CPU_ADDii
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z3addPiS_, .-_Z3addPiS_
.globl _Z7GPU_ADDii
.type _Z7GPU_ADDii, @function
_Z7GPU_ADDii:
.LFB2058:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 12(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7GPU_ADDii, .-_Z7GPU_ADDii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\nThe sum of the two numbers using GPU is: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time taken by GPU is: %E\n\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "The sum of the two numbers using CPU is: %d\n"
.section .rodata.str1.1
.LC4:
.string "Time taken by CPU is: %E\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %r13
movq %r13, %rsi
movl $0, %edi
call clock_gettime@PLT
movl $10000, %esi
movl $10000, %edi
call _Z7GPU_ADDii
movl %eax, %ebx
leaq 16(%rsp), %r14
movq %r14, %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 32(%rsp), %rbp
movq %rbp, %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 48(%rsp), %r12
movq %r12, %rsi
movl $0, %edi
call clock_gettime@PLT
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movq %r13, %rdi
call _Z12time_elapsedP8timespecS0_
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $20000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %rbp, %rdi
call _Z12time_elapsedP8timespecS0_
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<cuda.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
cudaMalloc(&d_a, sizeof(int)); //malloc space in device
cudaMalloc(&d_b, sizeof(int)); //malloc space in device
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
cudaMemcpy(d_b, &b, sizeof(int), cudaMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost); //copy the result from device ram back to main memory
cudaFree(d_a); //free device space
cudaFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
hipMalloc(&d_a, sizeof(int)); //malloc space in device
hipMalloc(&d_b, sizeof(int)); //malloc space in device
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
hipMemcpy(d_b, &b, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost); //copy the result from device ram back to main memory
hipFree(d_a); //free device space
hipFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
hipMalloc(&d_a, sizeof(int)); //malloc space in device
hipMalloc(&d_b, sizeof(int)); //malloc space in device
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
hipMemcpy(d_b, &b, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost); //copy the result from device ram back to main memory
hipFree(d_a); //free device space
hipFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Program to add two integers using the GPU instead of the CPU.
This program does not use shared memory.
Terrible example to start with as the CPU can execute the opertaion 100x faster than the GPU.
Benchmarking timings to compare speeds of execution.
*/
/*
Note that there is a considerable dependency of the ratio of execution times of the CPU and GPU on the
hardware which is being used to execute the run the program.
*/
// Importing the required headers
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
// Returns the duration from start to end times in sec
double time_elapsed(struct timespec *start, struct timespec *end)
{
double t;
t = (end->tv_sec - start->tv_sec); // diff in seconds
t += (end->tv_nsec - start->tv_nsec) * 0.000000001; //diff in nanoseconds
return t;
}
// GPU Kernel to add two numbers
__global__ void add(int *a, int *b)
{
a[0] += b[0]; //add the numbers and store the result in 'a'.
}
int GPU_ADD(int a, int b)
{
int *d_a; //pointer to device memory
int *d_b; //pointer to device memory
hipMalloc(&d_a, sizeof(int)); //malloc space in device
hipMalloc(&d_b, sizeof(int)); //malloc space in device
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
hipMemcpy(d_b, &b, sizeof(int), hipMemcpyHostToDevice); //copy value of variable to device memory/ram
add<<<1,1>>>(d_a, d_b); //call to the gpu function with the launch configuration
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost); //copy the result from device ram back to main memory
hipFree(d_a); //free device space
hipFree(d_b); //free device space
return a; //return result
}
// CPU function to add two numbers
int CPU_ADD(int a, int b)
{
return a+b; //return result
}
// Code execution begins here
int main()
{
struct timespec start1, end1; //variables to store time for GPU
struct timespec start2, end2; //variables to store time for CPU
int a = 10000;
int b = 10000;
//printf("Enter the value of a: "); //get value of a
//scanf("%d", &a);
//printf("Enter the value of b: "); //get value of b
//scanf("%d", &b);
clock_gettime(CLOCK_REALTIME, &start1); //start timestamp
int sum1 = GPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end1); //end timestamp
clock_gettime(CLOCK_REALTIME, &start2); //start timestamp
int sum2 = CPU_ADD(a, b);
clock_gettime(CLOCK_REALTIME, &end2); //end timestamp
printf("\nThe sum of the two numbers using GPU is: %d\n", sum1);
printf("Time taken by GPU is: %E\n\n", time_elapsed(&start1, &end1)); //print result for GPU
printf("The sum of the two numbers using CPU is: %d\n", sum2);
printf("Time taken by CPU is: %E\n", time_elapsed(&start2, &end2)); //print result for CPU
return 0;
} | .text
.file "Add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12time_elapsedP8timespecS0_
.LCPI0_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z12time_elapsedP8timespecS0_
.p2align 4, 0x90
.type _Z12time_elapsedP8timespecS0_,@function
_Z12time_elapsedP8timespecS0_: # @_Z12time_elapsedP8timespecS0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdi), %rax
cvtsi2sd %rax, %xmm1
subq 8(%rdi), %rcx
cvtsi2sd %rcx, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z12time_elapsedP8timespecS0_, .Lfunc_end0-_Z12time_elapsedP8timespecS0_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_, .Lfunc_end1-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.globl _Z7GPU_ADDii # -- Begin function _Z7GPU_ADDii
.p2align 4, 0x90
.type _Z7GPU_ADDii,@function
_Z7GPU_ADDii: # @_Z7GPU_ADDii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, 28(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl 4(%rsp), %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7GPU_ADDii, .Lfunc_end2-_Z7GPU_ADDii
.cfi_endproc
# -- End function
.globl _Z7CPU_ADDii # -- Begin function _Z7CPU_ADDii
.p2align 4, 0x90
.type _Z7CPU_ADDii,@function
_Z7CPU_ADDii: # @_Z7CPU_ADDii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
retq
.Lfunc_end3:
.size _Z7CPU_ADDii, .Lfunc_end3-_Z7CPU_ADDii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $10000, %edi # imm = 0x2710
movl $10000, %esi # imm = 0x2710
callq _Z7GPU_ADDii
movl %eax, %ebx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 16(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq %rsp, %rsi
xorl %edi, %edi
callq clock_gettime
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 56(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $20000, %esi # imm = 0x4E20
xorl %eax, %eax
callq printf
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 16(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 24(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nThe sum of the two numbers using GPU is: %d\n"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time taken by GPU is: %E\n\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The sum of the two numbers using CPU is: %d\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time taken by CPU is: %E\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R2, R7, RZ ; /* 0x0000000702077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ab10f_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12time_elapsedP8timespecS0_
.type _Z12time_elapsedP8timespecS0_, @function
_Z12time_elapsedP8timespecS0_:
.LFB2057:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq 8(%rsi), %rax
subq 8(%rdi), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
addsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z12time_elapsedP8timespecS0_, .-_Z12time_elapsedP8timespecS0_
.globl _Z7CPU_ADDii
.type _Z7CPU_ADDii, @function
_Z7CPU_ADDii:
.LFB2059:
.cfi_startproc
endbr64
leal (%rdi,%rsi), %eax
ret
.cfi_endproc
.LFE2059:
.size _Z7CPU_ADDii, .-_Z7CPU_ADDii
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z3addPiS_, .-_Z3addPiS_
.globl _Z7GPU_ADDii
.type _Z7GPU_ADDii, @function
_Z7GPU_ADDii:
.LFB2058:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 12(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7GPU_ADDii, .-_Z7GPU_ADDii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\nThe sum of the two numbers using GPU is: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time taken by GPU is: %E\n\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "The sum of the two numbers using CPU is: %d\n"
.section .rodata.str1.1
.LC4:
.string "Time taken by CPU is: %E\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %r13
movq %r13, %rsi
movl $0, %edi
call clock_gettime@PLT
movl $10000, %esi
movl $10000, %edi
call _Z7GPU_ADDii
movl %eax, %ebx
leaq 16(%rsp), %r14
movq %r14, %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 32(%rsp), %rbp
movq %rbp, %rsi
movl $0, %edi
call clock_gettime@PLT
leaq 48(%rsp), %r12
movq %r12, %rsi
movl $0, %edi
call clock_gettime@PLT
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movq %r13, %rdi
call _Z12time_elapsedP8timespecS0_
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $20000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %rbp, %rdi
call _Z12time_elapsedP8timespecS0_
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12time_elapsedP8timespecS0_
.LCPI0_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z12time_elapsedP8timespecS0_
.p2align 4, 0x90
.type _Z12time_elapsedP8timespecS0_,@function
_Z12time_elapsedP8timespecS0_: # @_Z12time_elapsedP8timespecS0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdi), %rax
cvtsi2sd %rax, %xmm1
subq 8(%rdi), %rcx
cvtsi2sd %rcx, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z12time_elapsedP8timespecS0_, .Lfunc_end0-_Z12time_elapsedP8timespecS0_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_, .Lfunc_end1-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.globl _Z7GPU_ADDii # -- Begin function _Z7GPU_ADDii
.p2align 4, 0x90
.type _Z7GPU_ADDii,@function
_Z7GPU_ADDii: # @_Z7GPU_ADDii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, 28(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl 4(%rsp), %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7GPU_ADDii, .Lfunc_end2-_Z7GPU_ADDii
.cfi_endproc
# -- End function
.globl _Z7CPU_ADDii # -- Begin function _Z7CPU_ADDii
.p2align 4, 0x90
.type _Z7CPU_ADDii,@function
_Z7CPU_ADDii: # @_Z7CPU_ADDii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
retq
.Lfunc_end3:
.size _Z7CPU_ADDii, .Lfunc_end3-_Z7CPU_ADDii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $10000, %edi # imm = 0x2710
movl $10000, %esi # imm = 0x2710
callq _Z7GPU_ADDii
movl %eax, %ebx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leaq 16(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq %rsp, %rsi
xorl %edi, %edi
callq clock_gettime
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 56(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $20000, %esi # imm = 0x4E20
xorl %eax, %eax
callq printf
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 16(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 24(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nThe sum of the two numbers using GPU is: %d\n"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time taken by GPU is: %E\n\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The sum of the two numbers using CPU is: %d\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time taken by CPU is: %E\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x + (blockIdx.x*blockDim.x));
}
int main()
{
/*
* When refactoring `loop` to launch as a kernel, be sure
* to use the execution configuration to control how many
* "iterations" to perform.
*
* For this exercise, be sure to use more than 1 block in
* the execution configuration.
*/
int NUM_BLOCKS = 2;
int NUM_THREADS = 5;
loop<<<NUM_BLOCKS, NUM_THREADS>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z4loopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x + (blockIdx.x*blockDim.x));
}
int main()
{
/*
* When refactoring `loop` to launch as a kernel, be sure
* to use the execution configuration to control how many
* "iterations" to perform.
*
* For this exercise, be sure to use more than 1 block in
* the execution configuration.
*/
int NUM_BLOCKS = 2;
int NUM_THREADS = 5;
loop<<<NUM_BLOCKS, NUM_THREADS>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00167122_00000000-6_05-multi-block-loop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x + (blockIdx.x*blockDim.x));
}
int main()
{
/*
* When refactoring `loop` to launch as a kernel, be sure
* to use the execution configuration to control how many
* "iterations" to perform.
*
* For this exercise, be sure to use more than 1 block in
* the execution configuration.
*/
int NUM_BLOCKS = 2;
int NUM_THREADS = 5;
loop<<<NUM_BLOCKS, NUM_THREADS>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x + (blockIdx.x*blockDim.x));
}
int main()
{
/*
* When refactoring `loop` to launch as a kernel, be sure
* to use the execution configuration to control how many
* "iterations" to perform.
*
* For this exercise, be sure to use more than 1 block in
* the execution configuration.
*/
int NUM_BLOCKS = 2;
int NUM_THREADS = 5;
loop<<<NUM_BLOCKS, NUM_THREADS>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x + (blockIdx.x*blockDim.x));
}
int main()
{
/*
* When refactoring `loop` to launch as a kernel, be sure
* to use the execution configuration to control how many
* "iterations" to perform.
*
* For this exercise, be sure to use more than 1 block in
* the execution configuration.
*/
int NUM_BLOCKS = 2;
int NUM_THREADS = 5;
loop<<<NUM_BLOCKS, NUM_THREADS>>>();
hipDeviceSynchronize();
} | .text
.file "05-multi-block-loop.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167122_00000000-6_05-multi-block-loop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "05-multi-block-loop.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .file "tmpxft_001ad4ad_00000000-6_00-naive_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " elapsed"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 4194304(%rax), %rdx
.L4:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movl $4, %eax
.L5:
movl 0(%rbp,%rax), %edx
addl -4(%rbx,%rax), %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L5
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4194300(%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main() {
const int block_size = 1024;
const int array_size = 1 << 20;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .text
.file "00-naive_scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_1
# %bb.2:
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB0_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB0_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB0_8
.LBB0_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 4194300(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r15)
je .LBB0_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB0_12
.LBB0_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " elapsed"
.size .L.str, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ad4ad_00000000-6_00-naive_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " elapsed"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 4194304(%rax), %rdx
.L4:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movl $4, %eax
.L5:
movl 0(%rbp,%rax), %edx
addl -4(%rbx,%rax), %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L5
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4194300(%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "00-naive_scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_1
# %bb.2:
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB0_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB0_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB0_8
.LBB0_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 4194300(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r15)
je .LBB0_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB0_12
.LBB0_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " elapsed"
.size .L.str, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} | code for sm_80
Function : _Z13kernelForAPSPPiS_S_S_PbS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*0050*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0060*/ ULDC UR8, c[0x0][0xc] ; /* 0x0000030000087ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe20000000800 */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ UIMAD UR5, UR8, UR5, URZ ; /* 0x00000005080572a4 */
/* 0x000fc6000f8e023f */
/*00b0*/ S2UR UR7, SR_CTAID.X ; /* 0x00000000000779c3 */
/* 0x000e220000002500 */
/*00c0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*00d0*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000ee60000002300 */
/*00e0*/ S2UR UR6, SR_CTAID.Z ; /* 0x00000000000679c3 */
/* 0x000f220000002700 */
/*00f0*/ UIMAD UR4, UR4, UR8, UR7 ; /* 0x00000008040472a4 */
/* 0x001fe2000f8e0207 */
/*0100*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fc400078e0200 */
/*0110*/ IMAD R0, R6, c[0x0][0x4], RZ ; /* 0x0000010006007a24 */
/* 0x000fe200078e02ff */
/*0120*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x010fcc000f8e0204 */
/*0130*/ ISETP.LE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x004fda000bf03270 */
/*0140*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0150*/ IMAD R8, R0, R8, R3 ; /* 0x0000000800087224 */
/* 0x008fe200078e0203 */
/*0160*/ UMOV UR6, UR4 ; /* 0x0000000400067c82 */
/* 0x000fe40008000000 */
/*0170*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0x6e0 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD R9, R2, UR6, RZ ; /* 0x0000000602097c24 */
/* 0x000fe2000f8e02ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01b0*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*01c0*/ ISETP.GE.AND P0, PT, R8, R2, PT ; /* 0x000000020800720c */
/* 0x000fda0003f06270 */
/*01d0*/ @P0 BRA 0x470 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fca0000000f00 */
/*01f0*/ IMAD.IADD R15, R9, 0x1, R10 ; /* 0x00000001090f7824 */
/* 0x000fca00078e020a */
/*0200*/ SHF.R.S32.HI R18, RZ, 0x1f, R15 ; /* 0x0000001fff127819 */
/* 0x000fe4000001140f */
/*0210*/ IADD3 R2, P0, R15, c[0x0][0x180], RZ ; /* 0x000060000f027a10 */
/* 0x000fc80007f1e0ff */
/*0220*/ IADD3.X R3, R18, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610012037a10 */
/* 0x000fca00007fe4ff */
/*0230*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1100 */
/*0240*/ BSSY B0, 0x430 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0260*/ @!P0 BRA 0x420 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0280*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c10110a */
/*0290*/ IMAD.WIDE R6, R10, R11, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fca00078e020b */
/*02a0*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R13, [R6.64+0x4] ; /* 0x0000040a060d7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ ISETP.GE.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fda0003f06270 */
/*02d0*/ @P0 BRA 0x420 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LEA R2, P0, R15, c[0x0][0x188], 0x2 ; /* 0x000062000f027a11 */
/* 0x001fe200078010ff */
/*02f0*/ IMAD.WIDE R12, R14, R11, c[0x0][0x170] ; /* 0x00005c000e0c7625 */
/* 0x000fc600078e020b */
/*0300*/ LEA.HI.X R3, R15, c[0x0][0x18c], R18, 0x2, P0 ; /* 0x000063000f037a11 */
/* 0x000fe200000f1412 */
/*0310*/ IMAD.WIDE R16, R14, R11, c[0x0][0x168] ; /* 0x00005a000e107625 */
/* 0x000fca00078e020b */
/*0320*/ LDG.E R18, [R16.64] ; /* 0x0000000a10127981 */
/* 0x000ea8000c1e1900 */
/*0330*/ LDG.E R15, [R12.64] ; /* 0x0000000a0c0f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R20, [R2.64] ; /* 0x0000000a02147981 */
/* 0x000ee2000c1e1900 */
/*0350*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.IADD R18, R9, 0x1, R18 ; /* 0x0000000109127824 */
/* 0x004fc800078e0212 */
/*0370*/ IMAD.WIDE R18, R18, R11, c[0x0][0x190] ; /* 0x0000640012127625 */
/* 0x000fe200078e020b */
/*0380*/ IADD3 R15, R15, R20, RZ ; /* 0x000000140f0f7210 */
/* 0x008fca0007ffe0ff */
/*0390*/ RED.E.MIN.S32.STRONG.GPU [R18.64], R15 ; /* 0x0000000f1200798e */
/* 0x0001e8000c90e38a */
/*03a0*/ LDG.E R21, [R6.64+0x4] ; /* 0x0000040a06157981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*03d0*/ IADD3 R16, P2, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007f5e0ff */
/*03e0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*03f0*/ IMAD.X R17, RZ, RZ, R17, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0611 */
/*0400*/ ISETP.GE.AND P0, PT, R14, R21, PT ; /* 0x000000150e00720c */
/* 0x004fda0003f06270 */
/*0410*/ @!P0 BRA 0x320 ; /* 0xffffff0000008947 */
/* 0x001fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0430*/ LDG.E R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD R10, R0, c[0x0][0x8], R10 ; /* 0x00000200000a7a24 */
/* 0x000fca00078e020a */
/*0450*/ ISETP.GE.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x004fda0003f06270 */
/*0460*/ @!P0 BRA 0x1f0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0470*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ LDG.E R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ BSSY B0, 0x660 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*04b0*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x004fda0003f06270 */
/*04c0*/ @P0 BRA 0x650 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0003 */
/*04e0*/ MOV R11, R8 ; /* 0x00000008000b7202 */
/* 0x000fca0000000f00 */
/*04f0*/ IMAD.IADD R13, R9, 0x1, R11 ; /* 0x00000001090d7824 */
/* 0x001fe400078e020b */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.WIDE R6, R13, R2, c[0x0][0x190] ; /* 0x000064000d067625 */
/* 0x000fc800078e0202 */
/*0520*/ IMAD.WIDE R2, R13, R2, c[0x0][0x188] ; /* 0x000062000d027625 */
/* 0x000fe200078e0202 */
/*0530*/ LDG.E R15, [R6.64] ; /* 0x0000000a060f7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R12, [R2.64] ; /* 0x0000000a020c7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ BSSY B1, 0x630 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0560*/ IMAD R11, R0, c[0x0][0x8], R11 ; /* 0x00000200000b7a24 */
/* 0x000fe200078e020b */
/*0570*/ ISETP.GE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f06270 */
/*0580*/ @P0 BRA 0x620 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.S32.HI R7, RZ, 0x1f, R13 ; /* 0x0000001fff077819 */
/* 0x000fe2000001140d */
/*05a0*/ HFMA2.MMA R12, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0c7435 */
/* 0x000fe200000001ff */
/*05b0*/ IADD3 R6, P0, R13, c[0x0][0x180], RZ ; /* 0x000060000d067a10 */
/* 0x000fe20007f1e0ff */
/*05c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e6000c10190a */
/*05d0*/ IADD3.X R7, R7, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610007077a10 */
/* 0x000fca00007fe4ff */
/*05e0*/ STG.E.U8 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e8000c10110a */
/*05f0*/ LDG.E R10, [R4.64] ; /* 0x0000000a040a7981 */
/* 0x000162000c1e1900 */
/*0600*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fca00078e00ff */
/*0610*/ STS [RZ], R13 ; /* 0x0000000dff007388 */
/* 0x0001e40000000800 */
/*0620*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x020fda0003f06270 */
/*0640*/ @!P0 BRA 0x4f0 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x001e240000000800 */
/*0680*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fda0003f05270 */
/*0690*/ @!P0 BRA 0x6e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06a0*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*06c0*/ ISETP.LE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x004fda000bf03270 */
/*06d0*/ @!P0 BRA 0x1b0 ; /* 0xfffffad000008947 */
/* 0x000fea000383ffff */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*0700*/ ULDC UR4, c[0x0][0x14] ; /* 0x0000050000047ab9 */
/* 0x000fe40000000800 */
/*0710*/ UIMAD UR6, UR5, UR4, UR6 ; /* 0x00000004050672a4 */
/* 0x000fcc000f8e0206 */
/*0720*/ ISETP.LE.AND P0, PT, R2, UR6, PT ; /* 0x0000000602007c0c */
/* 0x004fda000bf03270 */
/*0730*/ @!P0 BRA 0x170 ; /* 0xfffffa3000008947 */
/* 0x000fea000383ffff */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} | .file "tmpxft_0006d48e_00000000-6_spfa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
.type _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_, @function
_Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13kernelForAPSPPiS_S_S_PbS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_, .-_Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.type _Z13kernelForAPSPPiS_S_S_PbS_S_, @function
_Z13kernelForAPSPPiS_S_S_PbS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, .-_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13kernelForAPSPPiS_S_S_PbS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelForAPSPPiS_S_S_PbS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} | #include <hip/hip_runtime.h>
__global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelForAPSPPiS_S_S_PbS_S_
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.p2align 8
.type _Z13kernelForAPSPPiS_S_S_PbS_S_,@function
_Z13kernelForAPSPPiS_S_S_PbS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x38
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s16, s[2:3], 0x0
s_mul_i32 s18, s7, s6
s_mul_i32 s6, s6, s14
s_mul_i32 s7, s18, s15
s_add_i32 s6, s6, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s20, s6, s7
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s20, s16
s_cbranch_scc1 .LBB0_20
s_clause 0x1
s_load_b64 s[22:23], s[4:5], 0x8
s_load_b32 s17, s[4:5], 0x10
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b64 s[14:15], s[0:1], 0x30
v_bfe_u32 v1, v0, 20, 10
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v0, s16 :: v_dual_and_b32 v3, 0x3ff, v0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s23, 0xffff
s_lshr_b32 s1, s23, 16
v_mul_u32_u24_e32 v2, s0, v2
s_mul_i32 s1, s1, s0
s_and_b32 s0, s17, 0xffff
v_mul_lo_u32 v1, s1, v1
s_mul_i32 s16, s1, s0
s_mul_i32 s1, s22, s18
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[18:19], s[16:17], 2
v_add3_u32 v15, v2, v3, v1
s_branch .LBB0_3
.LBB0_2:
s_barrier
buffer_gl0_inv
global_load_b32 v0, v14, s[2:3]
s_add_i32 s20, s20, s1
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s20, v0
s_cbranch_vccz .LBB0_20
.LBB0_3:
global_load_b32 v1, v14, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB0_2
v_mul_lo_u32 v17, v0, s20
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v15, v17
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_branch .LBB0_6
.LBB0_5:
s_branch .LBB0_2
.LBB0_6:
global_load_b32 v4, v14, s[2:3]
s_mov_b32 s22, exec_lo
ds_store_b32 v14, v14
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v15, v4
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v4, v15
s_mov_b32 s23, 0
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s24
global_load_b32 v5, v14, s[2:3]
v_add_nc_u32_e32 v4, s16, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s23, vcc_lo, s23
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_13
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v4, v17
s_mov_b32 s24, exec_lo
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
global_load_u8 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v5
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[4:5]
global_store_b8 v[7:8], v11, off
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v7, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_mov_b32 s25, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s10, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
.p2align 6
.LBB0_12:
global_load_b32 v18, v[10:11], off
global_load_b32 v20, v[8:9], off
global_load_b32 v21, v[12:13], off
v_add_nc_u32_e32 v7, 1, v7
v_add_co_u32 v12, s0, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v18, v18, v17
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v20, v21, v20
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_u32 v18, vcc_lo, s14, v18
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, 4
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
global_atomic_min_i32 v[18:19], v20, off
global_load_b32 v18, v[5:6], off offset:4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v7, v18
s_or_b32 s25, vcc_lo, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_12
s_branch .LBB0_8
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s22
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v4, v14, s[2:3]
s_mov_b32 s22, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v15, v4
s_cbranch_execz .LBB0_18
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
v_mov_b32_e32 v10, v15
s_mov_b32 s23, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v8, v14, s[2:3]
v_add_nc_u32_e32 v10, s16, v10
v_add_co_u32 v6, vcc_lo, v6, s18
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
v_add_co_u32 v4, s0, v4, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s0, s17, v5, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v10, v8
s_or_b32 s23, vcc_lo, s23
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_18
.LBB0_16:
v_add_co_u32 v11, vcc_lo, s14, v6
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v11, v12
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v12, 1
global_store_b32 v[8:9], v11, off
global_store_b8 v[4:5], v12, off
ds_store_b32 v14, v16
s_branch .LBB0_15
.LBB0_18:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v14
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_cbranch_vccz .LBB0_5
global_load_b32 v4, v14, s[2:3]
s_add_i32 s21, s21, 1
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e64 s0, s21, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_6
s_branch .LBB0_2
.LBB0_20:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelForAPSPPiS_S_S_PbS_S_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, .Lfunc_end0-_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelForAPSPPiS_S_S_PbS_S_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z13kernelForAPSPPiS_S_S_PbS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernelForAPSP(int *V, int *E, int *W, int *n, bool *visit, int *dist, int *predist){
const int blockId = blockIdx.z *(gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
const int blockSize =blockDim.x * blockDim.y * blockDim.z;
const int gridSize = gridDim.x * gridDim.y * gridDim.z;
__shared__ int QuickExit;
int u=0, st=0, align=0, old=0;
st = blockId;
while(st < (*n))
{
align = (st * (*n));
for(int rnd=0;rnd<(*n);rnd++){
QuickExit = 0;
u = threadId;
while(u < (*n)){
if(visit[u + align]){
visit[u + align]=0;
for(int adj = V[u];adj<V[u+1];adj++){
old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
}
}
u+=blockSize;
}
__syncthreads();
u=threadId;
while(u < (*n)){
if(predist[align + u] < dist[align + u]){
dist[align + u] = predist[align + u];
visit[align + u] = 1;
QuickExit = 1;
}
u+=blockSize;
}
__syncthreads();
if(QuickExit==0){
break;
}
}
__syncthreads();
st += gridSize;
}
} | .text
.file "spfa.hip"
.globl _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_ # -- Begin function _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.p2align 4, 0x90
.type _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_,@function
_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_: # @_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13kernelForAPSPPiS_S_S_PbS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_, .Lfunc_end0-_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelForAPSPPiS_S_S_PbS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelForAPSPPiS_S_S_PbS_S_,@object # @_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .rodata,"a",@progbits
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.p2align 3, 0x0
_Z13kernelForAPSPPiS_S_S_PbS_S_:
.quad _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelForAPSPPiS_S_S_PbS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelForAPSPPiS_S_S_PbS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kernelForAPSPPiS_S_S_PbS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*0050*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0060*/ ULDC UR8, c[0x0][0xc] ; /* 0x0000030000087ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe20000000800 */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ UIMAD UR5, UR8, UR5, URZ ; /* 0x00000005080572a4 */
/* 0x000fc6000f8e023f */
/*00b0*/ S2UR UR7, SR_CTAID.X ; /* 0x00000000000779c3 */
/* 0x000e220000002500 */
/*00c0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*00d0*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000ee60000002300 */
/*00e0*/ S2UR UR6, SR_CTAID.Z ; /* 0x00000000000679c3 */
/* 0x000f220000002700 */
/*00f0*/ UIMAD UR4, UR4, UR8, UR7 ; /* 0x00000008040472a4 */
/* 0x001fe2000f8e0207 */
/*0100*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fc400078e0200 */
/*0110*/ IMAD R0, R6, c[0x0][0x4], RZ ; /* 0x0000010006007a24 */
/* 0x000fe200078e02ff */
/*0120*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x010fcc000f8e0204 */
/*0130*/ ISETP.LE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x004fda000bf03270 */
/*0140*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0150*/ IMAD R8, R0, R8, R3 ; /* 0x0000000800087224 */
/* 0x008fe200078e0203 */
/*0160*/ UMOV UR6, UR4 ; /* 0x0000000400067c82 */
/* 0x000fe40008000000 */
/*0170*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0x6e0 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD R9, R2, UR6, RZ ; /* 0x0000000602097c24 */
/* 0x000fe2000f8e02ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01b0*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*01c0*/ ISETP.GE.AND P0, PT, R8, R2, PT ; /* 0x000000020800720c */
/* 0x000fda0003f06270 */
/*01d0*/ @P0 BRA 0x470 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fca0000000f00 */
/*01f0*/ IMAD.IADD R15, R9, 0x1, R10 ; /* 0x00000001090f7824 */
/* 0x000fca00078e020a */
/*0200*/ SHF.R.S32.HI R18, RZ, 0x1f, R15 ; /* 0x0000001fff127819 */
/* 0x000fe4000001140f */
/*0210*/ IADD3 R2, P0, R15, c[0x0][0x180], RZ ; /* 0x000060000f027a10 */
/* 0x000fc80007f1e0ff */
/*0220*/ IADD3.X R3, R18, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610012037a10 */
/* 0x000fca00007fe4ff */
/*0230*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1100 */
/*0240*/ BSSY B0, 0x430 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0260*/ @!P0 BRA 0x420 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0280*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c10110a */
/*0290*/ IMAD.WIDE R6, R10, R11, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fca00078e020b */
/*02a0*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R13, [R6.64+0x4] ; /* 0x0000040a060d7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ ISETP.GE.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720c */
/* 0x004fda0003f06270 */
/*02d0*/ @P0 BRA 0x420 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LEA R2, P0, R15, c[0x0][0x188], 0x2 ; /* 0x000062000f027a11 */
/* 0x001fe200078010ff */
/*02f0*/ IMAD.WIDE R12, R14, R11, c[0x0][0x170] ; /* 0x00005c000e0c7625 */
/* 0x000fc600078e020b */
/*0300*/ LEA.HI.X R3, R15, c[0x0][0x18c], R18, 0x2, P0 ; /* 0x000063000f037a11 */
/* 0x000fe200000f1412 */
/*0310*/ IMAD.WIDE R16, R14, R11, c[0x0][0x168] ; /* 0x00005a000e107625 */
/* 0x000fca00078e020b */
/*0320*/ LDG.E R18, [R16.64] ; /* 0x0000000a10127981 */
/* 0x000ea8000c1e1900 */
/*0330*/ LDG.E R15, [R12.64] ; /* 0x0000000a0c0f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R20, [R2.64] ; /* 0x0000000a02147981 */
/* 0x000ee2000c1e1900 */
/*0350*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.IADD R18, R9, 0x1, R18 ; /* 0x0000000109127824 */
/* 0x004fc800078e0212 */
/*0370*/ IMAD.WIDE R18, R18, R11, c[0x0][0x190] ; /* 0x0000640012127625 */
/* 0x000fe200078e020b */
/*0380*/ IADD3 R15, R15, R20, RZ ; /* 0x000000140f0f7210 */
/* 0x008fca0007ffe0ff */
/*0390*/ RED.E.MIN.S32.STRONG.GPU [R18.64], R15 ; /* 0x0000000f1200798e */
/* 0x0001e8000c90e38a */
/*03a0*/ LDG.E R21, [R6.64+0x4] ; /* 0x0000040a06157981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*03d0*/ IADD3 R16, P2, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007f5e0ff */
/*03e0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*03f0*/ IMAD.X R17, RZ, RZ, R17, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0611 */
/*0400*/ ISETP.GE.AND P0, PT, R14, R21, PT ; /* 0x000000150e00720c */
/* 0x004fda0003f06270 */
/*0410*/ @!P0 BRA 0x320 ; /* 0xffffff0000008947 */
/* 0x001fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0430*/ LDG.E R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD R10, R0, c[0x0][0x8], R10 ; /* 0x00000200000a7a24 */
/* 0x000fca00078e020a */
/*0450*/ ISETP.GE.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x004fda0003f06270 */
/*0460*/ @!P0 BRA 0x1f0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0470*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ LDG.E R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ BSSY B0, 0x660 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*04b0*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x004fda0003f06270 */
/*04c0*/ @P0 BRA 0x650 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0003 */
/*04e0*/ MOV R11, R8 ; /* 0x00000008000b7202 */
/* 0x000fca0000000f00 */
/*04f0*/ IMAD.IADD R13, R9, 0x1, R11 ; /* 0x00000001090d7824 */
/* 0x001fe400078e020b */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.WIDE R6, R13, R2, c[0x0][0x190] ; /* 0x000064000d067625 */
/* 0x000fc800078e0202 */
/*0520*/ IMAD.WIDE R2, R13, R2, c[0x0][0x188] ; /* 0x000062000d027625 */
/* 0x000fe200078e0202 */
/*0530*/ LDG.E R15, [R6.64] ; /* 0x0000000a060f7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R12, [R2.64] ; /* 0x0000000a020c7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ BSSY B1, 0x630 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0560*/ IMAD R11, R0, c[0x0][0x8], R11 ; /* 0x00000200000b7a24 */
/* 0x000fe200078e020b */
/*0570*/ ISETP.GE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fda0003f06270 */
/*0580*/ @P0 BRA 0x620 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.S32.HI R7, RZ, 0x1f, R13 ; /* 0x0000001fff077819 */
/* 0x000fe2000001140d */
/*05a0*/ HFMA2.MMA R12, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0c7435 */
/* 0x000fe200000001ff */
/*05b0*/ IADD3 R6, P0, R13, c[0x0][0x180], RZ ; /* 0x000060000d067a10 */
/* 0x000fe20007f1e0ff */
/*05c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e6000c10190a */
/*05d0*/ IADD3.X R7, R7, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610007077a10 */
/* 0x000fca00007fe4ff */
/*05e0*/ STG.E.U8 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e8000c10110a */
/*05f0*/ LDG.E R10, [R4.64] ; /* 0x0000000a040a7981 */
/* 0x000162000c1e1900 */
/*0600*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fca00078e00ff */
/*0610*/ STS [RZ], R13 ; /* 0x0000000dff007388 */
/* 0x0001e40000000800 */
/*0620*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x020fda0003f06270 */
/*0640*/ @!P0 BRA 0x4f0 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x001e240000000800 */
/*0680*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fda0003f05270 */
/*0690*/ @!P0 BRA 0x6e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06a0*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*06c0*/ ISETP.LE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x004fda000bf03270 */
/*06d0*/ @!P0 BRA 0x1b0 ; /* 0xfffffad000008947 */
/* 0x000fea000383ffff */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ LDG.E R2, [R4.64] ; /* 0x0000000a04027981 */
/* 0x000ea2000c1e1900 */
/*0700*/ ULDC UR4, c[0x0][0x14] ; /* 0x0000050000047ab9 */
/* 0x000fe40000000800 */
/*0710*/ UIMAD UR6, UR5, UR4, UR6 ; /* 0x00000004050672a4 */
/* 0x000fcc000f8e0206 */
/*0720*/ ISETP.LE.AND P0, PT, R2, UR6, PT ; /* 0x0000000602007c0c */
/* 0x004fda000bf03270 */
/*0730*/ @!P0 BRA 0x170 ; /* 0xfffffa3000008947 */
/* 0x000fea000383ffff */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelForAPSPPiS_S_S_PbS_S_
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.p2align 8
.type _Z13kernelForAPSPPiS_S_S_PbS_S_,@function
_Z13kernelForAPSPPiS_S_S_PbS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x38
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s16, s[2:3], 0x0
s_mul_i32 s18, s7, s6
s_mul_i32 s6, s6, s14
s_mul_i32 s7, s18, s15
s_add_i32 s6, s6, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s20, s6, s7
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s20, s16
s_cbranch_scc1 .LBB0_20
s_clause 0x1
s_load_b64 s[22:23], s[4:5], 0x8
s_load_b32 s17, s[4:5], 0x10
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b64 s[14:15], s[0:1], 0x30
v_bfe_u32 v1, v0, 20, 10
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v0, s16 :: v_dual_and_b32 v3, 0x3ff, v0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s23, 0xffff
s_lshr_b32 s1, s23, 16
v_mul_u32_u24_e32 v2, s0, v2
s_mul_i32 s1, s1, s0
s_and_b32 s0, s17, 0xffff
v_mul_lo_u32 v1, s1, v1
s_mul_i32 s16, s1, s0
s_mul_i32 s1, s22, s18
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[18:19], s[16:17], 2
v_add3_u32 v15, v2, v3, v1
s_branch .LBB0_3
.LBB0_2:
s_barrier
buffer_gl0_inv
global_load_b32 v0, v14, s[2:3]
s_add_i32 s20, s20, s1
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s20, v0
s_cbranch_vccz .LBB0_20
.LBB0_3:
global_load_b32 v1, v14, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB0_2
v_mul_lo_u32 v17, v0, s20
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v15, v17
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_branch .LBB0_6
.LBB0_5:
s_branch .LBB0_2
.LBB0_6:
global_load_b32 v4, v14, s[2:3]
s_mov_b32 s22, exec_lo
ds_store_b32 v14, v14
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v15, v4
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v4, v15
s_mov_b32 s23, 0
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s24
global_load_b32 v5, v14, s[2:3]
v_add_nc_u32_e32 v4, s16, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s23, vcc_lo, s23
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_13
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v4, v17
s_mov_b32 s24, exec_lo
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
global_load_u8 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v5
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[4:5]
global_store_b8 v[7:8], v11, off
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v7, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_mov_b32 s25, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s10, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
.p2align 6
.LBB0_12:
global_load_b32 v18, v[10:11], off
global_load_b32 v20, v[8:9], off
global_load_b32 v21, v[12:13], off
v_add_nc_u32_e32 v7, 1, v7
v_add_co_u32 v12, s0, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v18, v18, v17
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v20, v21, v20
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_u32 v18, vcc_lo, s14, v18
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, 4
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
global_atomic_min_i32 v[18:19], v20, off
global_load_b32 v18, v[5:6], off offset:4
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v7, v18
s_or_b32 s25, vcc_lo, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_12
s_branch .LBB0_8
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s22
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v4, v14, s[2:3]
s_mov_b32 s22, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v15, v4
s_cbranch_execz .LBB0_18
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
v_mov_b32_e32 v10, v15
s_mov_b32 s23, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v8, v14, s[2:3]
v_add_nc_u32_e32 v10, s16, v10
v_add_co_u32 v6, vcc_lo, v6, s18
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
v_add_co_u32 v4, s0, v4, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s0, s17, v5, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v10, v8
s_or_b32 s23, vcc_lo, s23
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_18
.LBB0_16:
v_add_co_u32 v11, vcc_lo, s14, v6
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v11, v12
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v12, 1
global_store_b32 v[8:9], v11, off
global_store_b8 v[4:5], v12, off
ds_store_b32 v14, v16
s_branch .LBB0_15
.LBB0_18:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v14
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_cbranch_vccz .LBB0_5
global_load_b32 v4, v14, s[2:3]
s_add_i32 s21, s21, 1
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e64 s0, s21, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_6
s_branch .LBB0_2
.LBB0_20:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelForAPSPPiS_S_S_PbS_S_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, .Lfunc_end0-_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelForAPSPPiS_S_S_PbS_S_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z13kernelForAPSPPiS_S_S_PbS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006d48e_00000000-6_spfa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
.type _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_, @function
_Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13kernelForAPSPPiS_S_S_PbS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_, .-_Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.type _Z13kernelForAPSPPiS_S_S_PbS_S_, @function
_Z13kernelForAPSPPiS_S_S_PbS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13kernelForAPSPPiS_S_S_PbS_S_PiS_S_S_PbS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, .-_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13kernelForAPSPPiS_S_S_PbS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelForAPSPPiS_S_S_PbS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spfa.hip"
.globl _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_ # -- Begin function _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.p2align 4, 0x90
.type _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_,@function
_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_: # @_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13kernelForAPSPPiS_S_S_PbS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_, .Lfunc_end0-_Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelForAPSPPiS_S_S_PbS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelForAPSPPiS_S_S_PbS_S_,@object # @_Z13kernelForAPSPPiS_S_S_PbS_S_
.section .rodata,"a",@progbits
.globl _Z13kernelForAPSPPiS_S_S_PbS_S_
.p2align 3, 0x0
_Z13kernelForAPSPPiS_S_S_PbS_S_:
.quad _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.size _Z13kernelForAPSPPiS_S_S_PbS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelForAPSPPiS_S_S_PbS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelForAPSPPiS_S_S_PbS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelForAPSPPiS_S_S_PbS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void profileLevelDown_kernel() {} | code for sm_80
Function : _Z23profileLevelDown_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void profileLevelDown_kernel() {} | .file "tmpxft_0014ab9c_00000000-6_profileLevelDown_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z23profileLevelDown_kernelvv
.type _Z42__device_stub__Z23profileLevelDown_kernelvv, @function
_Z42__device_stub__Z23profileLevelDown_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z23profileLevelDown_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z23profileLevelDown_kernelvv, .-_Z42__device_stub__Z23profileLevelDown_kernelvv
.globl _Z23profileLevelDown_kernelv
.type _Z23profileLevelDown_kernelv, @function
_Z23profileLevelDown_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z23profileLevelDown_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23profileLevelDown_kernelv, .-_Z23profileLevelDown_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z23profileLevelDown_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23profileLevelDown_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void profileLevelDown_kernel() {} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profileLevelDown_kernel() {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profileLevelDown_kernel() {} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23profileLevelDown_kernelv
.globl _Z23profileLevelDown_kernelv
.p2align 8
.type _Z23profileLevelDown_kernelv,@function
_Z23profileLevelDown_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23profileLevelDown_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23profileLevelDown_kernelv, .Lfunc_end0-_Z23profileLevelDown_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23profileLevelDown_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z23profileLevelDown_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profileLevelDown_kernel() {} | .text
.file "profileLevelDown_kernel.hip"
.globl _Z38__device_stub__profileLevelDown_kernelv # -- Begin function _Z38__device_stub__profileLevelDown_kernelv
.p2align 4, 0x90
.type _Z38__device_stub__profileLevelDown_kernelv,@function
_Z38__device_stub__profileLevelDown_kernelv: # @_Z38__device_stub__profileLevelDown_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z23profileLevelDown_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z38__device_stub__profileLevelDown_kernelv, .Lfunc_end0-_Z38__device_stub__profileLevelDown_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23profileLevelDown_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23profileLevelDown_kernelv,@object # @_Z23profileLevelDown_kernelv
.section .rodata,"a",@progbits
.globl _Z23profileLevelDown_kernelv
.p2align 3, 0x0
_Z23profileLevelDown_kernelv:
.quad _Z38__device_stub__profileLevelDown_kernelv
.size _Z23profileLevelDown_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23profileLevelDown_kernelv"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__profileLevelDown_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23profileLevelDown_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23profileLevelDown_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23profileLevelDown_kernelv
.globl _Z23profileLevelDown_kernelv
.p2align 8
.type _Z23profileLevelDown_kernelv,@function
_Z23profileLevelDown_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23profileLevelDown_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23profileLevelDown_kernelv, .Lfunc_end0-_Z23profileLevelDown_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23profileLevelDown_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z23profileLevelDown_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014ab9c_00000000-6_profileLevelDown_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z23profileLevelDown_kernelvv
.type _Z42__device_stub__Z23profileLevelDown_kernelvv, @function
_Z42__device_stub__Z23profileLevelDown_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z23profileLevelDown_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z23profileLevelDown_kernelvv, .-_Z42__device_stub__Z23profileLevelDown_kernelvv
.globl _Z23profileLevelDown_kernelv
.type _Z23profileLevelDown_kernelv, @function
_Z23profileLevelDown_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z23profileLevelDown_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23profileLevelDown_kernelv, .-_Z23profileLevelDown_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z23profileLevelDown_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23profileLevelDown_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "profileLevelDown_kernel.hip"
.globl _Z38__device_stub__profileLevelDown_kernelv # -- Begin function _Z38__device_stub__profileLevelDown_kernelv
.p2align 4, 0x90
.type _Z38__device_stub__profileLevelDown_kernelv,@function
_Z38__device_stub__profileLevelDown_kernelv: # @_Z38__device_stub__profileLevelDown_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z23profileLevelDown_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z38__device_stub__profileLevelDown_kernelv, .Lfunc_end0-_Z38__device_stub__profileLevelDown_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23profileLevelDown_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23profileLevelDown_kernelv,@object # @_Z23profileLevelDown_kernelv
.section .rodata,"a",@progbits
.globl _Z23profileLevelDown_kernelv
.p2align 3, 0x0
_Z23profileLevelDown_kernelv:
.quad _Z38__device_stub__profileLevelDown_kernelv
.size _Z23profileLevelDown_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23profileLevelDown_kernelv"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__profileLevelDown_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23profileLevelDown_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //////////////////////////////////////////////////////////////////////////
////This is the code implementation for GPU Premier League Round 1
//////////////////////////////////////////////////////////////////////////
#include <iostream>
#include <fstream>
#include <vector>
#include <chrono>
#include <cuda_runtime.h>
using namespace std;
//////////////////////////////////////////////////////////////////////////
////TODO 0: Please replace the following strings with your team name and author names
////Note: Please do not use space in the string, use "_" instead
//////////////////////////////////////////////////////////////////////////
namespace name
{
std::string team="slim_shaders";
std::string author_1="Andrw_Yang";
std::string author_2="Matthew_Kenney";
};
////This is a matrix class to carry out linear algebra operations on both GPU and CPU
////It is the same as the sample code I showed in class on Week 3.
////NOTICE: You do not have to change the implementation in this class.
////But if you do want to change part of it for performance reasons, please let us known by writting a submission note on Canvas.
class Matrix{
public:
int m=0; ////number of rows
int n=0; ////number of columns
vector<float> elements_on_host; ////we use a std::vector for the element array on host
float* elements_on_dev=0; ////we use a pointer for the element array on device
bool on_host=true;
////constructors
__host__ Matrix(){}
__host__ Matrix(const int _m,const int _n,bool _on_host=true)
{
on_host=_on_host;
if(on_host)Resize_On_Host(_m,_n);
else Resize_On_Device(_m,_n);
}
////destructor
__host__ ~Matrix()
{
if(!on_host&&elements_on_dev!=0) cudaFree(elements_on_dev);
}
////Resize on host or device
__host__ void Resize_On_Host(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
elements_on_host.resize(m*n);
}
__host__ void Resize_On_Device(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
if(elements_on_dev!=0)cudaFree(elements_on_dev);
cudaMalloc((void**)&elements_on_dev,m*n*sizeof(float));
}
////random access a matrix element
inline __host__ float& operator() (const int i,const int j)
{
return elements_on_host[i*n+j];
}
inline __host__ const float& operator() (const int i,const int j) const
{
return elements_on_host[i*n+j];
}
////copy data with four cases (CPU->CPU, GPU->CPU, GPU->GPU, CPU->GPU)
__host__ Matrix& operator= (const Matrix& mtx)
{
if(on_host&&mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
elements_on_host=mtx.elements_on_host;
}
else if(on_host&&!mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
cudaMemcpy(&elements_on_host[0],mtx.elements_on_dev,m*n*sizeof(float),cudaMemcpyDeviceToHost);
}
else if(!on_host&&!mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
cudaMemcpy(elements_on_dev,mtx.elements_on_dev,mtx.m*n*sizeof(float),cudaMemcpyDeviceToDevice);
}
else if(!on_host&&mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
cudaMemcpy(elements_on_dev,&mtx.elements_on_host[0],m*n*sizeof(float),cudaMemcpyHostToDevice);
}
return *this;
}
////print matrix elements on screen
__host__ friend ostream & operator << (ostream &out,const Matrix &mtx)
{
if(!mtx.on_host)
cout<<"Print for matrix on device is not supported."<<endl;
for(int i=0;i<mtx.m;i++){
for(int j=0;j<mtx.n;j++){
out<<mtx(i,j)<<", ";
}
out<<std::endl;
}
return out;
}
};
//////////////////////////////////////////////////////////////////////////
////Your tasks start!
////This is a sample implementation without using any memory hierarchy
////The function calculates C=A*B, with dimA=[Am,An], dimB=[Bm,Bn], dimC=[Am,bn], and An=Bm
__global__ void Matrix_Multiplication_AB_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int k=0;k<An;k++)
val+=Ae[i*An+k]*Be[k*Bn+j];
Ce[i*Bn+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 1: implement your fast matrix-matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
/*Your may want to declare your global variables here*/
__global__ void Matrix_Multiplication_AB_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[Bn * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
// iterate over matrix to tile
for (int m = 0; m < (An / blockSize); ++m) {
const float* A_tile = &Ae[An * tileRow * blockSize + m * blockSize]; // tile A and B matrices
const float* B_tile = &Be[Bn * blockSize * m + tileCol *blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col]; // load into shared memory
B_s[row][col] = B_tile[row * Bn + col];
__syncthreads();
// Perform multiplication of the tile
for (int e = 0; e < blockSize; ++e)
{
Cvalue += A_s[row][e] * B_s[e][col];
}
__syncthreads();
}
C_tile[row * Bn + col] = Cvalue;
}
////This is a sample implementation without using any memory hierarchy
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
__global__ void Matrix_Multiplication_ATBA_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int l=0;l<Am;l++)
for(int k=0;k<Am;k++)
val+=Ae[l*An+i]*Be[l*Am+k]*Ae[k*An+j];
Ce[i*An+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 2: calculate the matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
__global__ void Matrix_Multiplication_ATBA_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[An * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
for (int m = 0; m < (Am / blockSize); ++m) { // find transpose
const float* A_tile_transpose = &Ae[Am * blockSize * m + tileCol *blockSize];
__shared__ float A_s_tranpose[blockSize][blockSize];
A_s_tranpose[row][col] = A_tile_transpose[row * An + col];
__syncthreads();
for(int i = 0; i < (Am / blockSize); ++i)
{ // order of operations around As Bs
const float* A_tile = &Ae[An * blockSize * i + blockSize * tileRow];
const float* B_tile = &Be[Am * blockSize * m + i * blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col];
B_s[row][col] = B_tile[row * Am + col];
__syncthreads();
for (int l = 0; l < blockSize; ++l)
{
for (int k = 0; k < blockSize; ++k)
{
Cvalue += A_s_tranpose[row][l] * B_s[l][k] * A_s[k][col];
}
}
}
__syncthreads();
}
C_tile[row * An + col] = Cvalue;
/*Your implementation ends*/
}
//////////////////////////////////////////////////////////////////////////
////Task 3: calculate the Frobenius norm of a matrix
////The definition of F-norm for a matrix is square root of (the sum of squares of all the matrix elements), i.e., F=sqrt(sum_(A_ij^2))
////See the definition: https://mathworld.wolfram.com/FrobeniusNorm.html
//////////////////////////////////////////////////////////////////////////
////Please write your own kernel function here, and call it in the function Test_F_Norm_On_GPU to test its correctness and performance
/*Your implementation starts*/
__global__ void Test_F_Norm_On_GPU(const float *Ae, const int An, const int Am, float* norm)
{
const int blockSize = 16;
const int num_threads = blockSize * blockSize;
int global_thread_id = (blockIdx.y * gridDim.x + blockDim.x) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x)+ threadIdx.x;
int local_thread_id = threadIdx.y * blockDim.x+ threadIdx.x;
__shared__ float block_sum[blockSize * blockSize];
block_sum[local_thread_id]= Ae[global_thread_id]; // load into shared memory
block_sum[local_thread_id] *= block_sum[local_thread_id]; // compute the square
__syncthreads();
for(unsigned int i=num_threads/2; i> 0; i/=2){
if(local_thread_id < i) {
block_sum[local_thread_id]+=block_sum[local_thread_id + i];
}
__syncthreads();
}
if(local_thread_id==0) {
atomicAdd(norm, block_sum[0]);
}
}
/*Your implementation ends*/
////Congratulations, your tasks are all finished!
//////////////////////////////////////////////////////////////////////////
////Here are the test functions for your three kernel implementations
ofstream out;
__host__ void Test_Matrix_Multiplication_AB_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.m,B_on_dev.n,false);
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
float gpu_time=0.0f;
cudaDeviceSynchronize();
cudaEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_AB_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
////TODO: Uncomment this to test your own implementation
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_AB_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication AB: %.4f ms\n",gpu_time);
cudaEventDestroy(start);
cudaEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T1: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_Multiplication_ATBA_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.n,A_on_dev.n,false);
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
float gpu_time=0.0f;
cudaDeviceSynchronize();
cudaEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_ATBA_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
////TODO: Uncomment this to test your own implementation.
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_ATBA_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication ATBA: %.4f ms\n",gpu_time);
cudaEventDestroy(start);
cudaEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T2: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_F_Norm_On_GPU(const Matrix& A,/*result*/float& norm)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
float gpu_time=0.0f;
cudaDeviceSynchronize();
cudaEventRecord(start);
//// Invoke kernel
////TODO: call the F norm kernel you implemented, and return the value to the passed-in variable norm
const int block_size = 16;
const int block_num_x = A.m/block_size;
const int block_num_y = A.n/block_size;
float* norm_dev;
cudaMalloc((void **)&norm_dev, sizeof(float));
cudaMemcpy(norm_dev, &norm, sizeof(float), cudaMemcpyHostToDevice);
Test_F_Norm_On_GPU<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev, A_on_dev.n, A_on_dev.m, norm_dev);
cudaMemcpy(&norm, norm_dev, sizeof(float), cudaMemcpyDeviceToHost);
// Calculate the SQRT on host, since this computation is inexpensive
norm = sqrt(norm);
cudaFree(norm_dev);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for F norm: %.4f ms\n",gpu_time);
cudaEventDestroy(start);
cudaEventDestroy(end);
out<<"T3: "<<gpu_time<<endl;
}
int main()
{
if(name::team=="Team_X"){
printf("\nPlease specify your team name and team member names in name::team and name::author to start.\n");
return 0;
}
std::string file_name=name::team+"_competition_1_matrix.dat";
out.open(file_name.c_str());
if(out.fail()){
printf("\ncannot open file %s to record results\n",file_name.c_str());
return 0;
}
//////////////////////////////////////////////////////////////////////////
////NOTICE: We may use a different set of parameters to evaluate your code.
////So please test your functions with different size and initial values.
//////////////////////////////////////////////////////////////////////////
const int m=512;
const int n=2048;
const int p=1024;
Matrix h_A(m,n);
for(int i=0;i<m;i++){
for(int j=0;j<n;j++){
h_A(i,j)=1.f;
}
}
Matrix h_B(n,p);
for(int i=0;i<n;i++){
for(int j=0;j<p;j++){
h_B(i,j)=1.f;
}
}
Matrix h_C(m,p);
Matrix h_B2(m,m);
for(int i=0;i<m;i++){
for(int j=0;j<m;j++){
h_B2(i,j)=1.f;
}
}
Matrix h_C2(n,n);
Test_Matrix_Multiplication_AB_On_GPU(h_A,h_B,h_C);
cout<<"AB result: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
out<<"R1: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
Test_Matrix_Multiplication_ATBA_On_GPU(h_A,h_B2,h_C2);
cout<<"ATBA result: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
out<<"R2: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
float f_norm=0.f;
Test_Matrix_F_Norm_On_GPU(h_A,f_norm);
cout<<"F-norm result: "<<f_norm<<endl;
out<<"R3: "<<f_norm<<endl;
return 0;
} | //////////////////////////////////////////////////////////////////////////
////This is the code implementation for GPU Premier League Round 1
//////////////////////////////////////////////////////////////////////////
#include <iostream>
#include <fstream>
#include <vector>
#include <chrono>
#include <hip/hip_runtime.h>
using namespace std;
//////////////////////////////////////////////////////////////////////////
////TODO 0: Please replace the following strings with your team name and author names
////Note: Please do not use space in the string, use "_" instead
//////////////////////////////////////////////////////////////////////////
namespace name
{
std::string team="slim_shaders";
std::string author_1="Andrw_Yang";
std::string author_2="Matthew_Kenney";
};
////This is a matrix class to carry out linear algebra operations on both GPU and CPU
////It is the same as the sample code I showed in class on Week 3.
////NOTICE: You do not have to change the implementation in this class.
////But if you do want to change part of it for performance reasons, please let us known by writting a submission note on Canvas.
class Matrix{
public:
int m=0; ////number of rows
int n=0; ////number of columns
vector<float> elements_on_host; ////we use a std::vector for the element array on host
float* elements_on_dev=0; ////we use a pointer for the element array on device
bool on_host=true;
////constructors
__host__ Matrix(){}
__host__ Matrix(const int _m,const int _n,bool _on_host=true)
{
on_host=_on_host;
if(on_host)Resize_On_Host(_m,_n);
else Resize_On_Device(_m,_n);
}
////destructor
__host__ ~Matrix()
{
if(!on_host&&elements_on_dev!=0) hipFree(elements_on_dev);
}
////Resize on host or device
__host__ void Resize_On_Host(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
elements_on_host.resize(m*n);
}
__host__ void Resize_On_Device(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
if(elements_on_dev!=0)hipFree(elements_on_dev);
hipMalloc((void**)&elements_on_dev,m*n*sizeof(float));
}
////random access a matrix element
inline __host__ float& operator() (const int i,const int j)
{
return elements_on_host[i*n+j];
}
inline __host__ const float& operator() (const int i,const int j) const
{
return elements_on_host[i*n+j];
}
////copy data with four cases (CPU->CPU, GPU->CPU, GPU->GPU, CPU->GPU)
__host__ Matrix& operator= (const Matrix& mtx)
{
if(on_host&&mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
elements_on_host=mtx.elements_on_host;
}
else if(on_host&&!mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
hipMemcpy(&elements_on_host[0],mtx.elements_on_dev,m*n*sizeof(float),hipMemcpyDeviceToHost);
}
else if(!on_host&&!mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
hipMemcpy(elements_on_dev,mtx.elements_on_dev,mtx.m*n*sizeof(float),hipMemcpyDeviceToDevice);
}
else if(!on_host&&mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
hipMemcpy(elements_on_dev,&mtx.elements_on_host[0],m*n*sizeof(float),hipMemcpyHostToDevice);
}
return *this;
}
////print matrix elements on screen
__host__ friend ostream & operator << (ostream &out,const Matrix &mtx)
{
if(!mtx.on_host)
cout<<"Print for matrix on device is not supported."<<endl;
for(int i=0;i<mtx.m;i++){
for(int j=0;j<mtx.n;j++){
out<<mtx(i,j)<<", ";
}
out<<std::endl;
}
return out;
}
};
//////////////////////////////////////////////////////////////////////////
////Your tasks start!
////This is a sample implementation without using any memory hierarchy
////The function calculates C=A*B, with dimA=[Am,An], dimB=[Bm,Bn], dimC=[Am,bn], and An=Bm
__global__ void Matrix_Multiplication_AB_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int k=0;k<An;k++)
val+=Ae[i*An+k]*Be[k*Bn+j];
Ce[i*Bn+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 1: implement your fast matrix-matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
/*Your may want to declare your global variables here*/
__global__ void Matrix_Multiplication_AB_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[Bn * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
// iterate over matrix to tile
for (int m = 0; m < (An / blockSize); ++m) {
const float* A_tile = &Ae[An * tileRow * blockSize + m * blockSize]; // tile A and B matrices
const float* B_tile = &Be[Bn * blockSize * m + tileCol *blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col]; // load into shared memory
B_s[row][col] = B_tile[row * Bn + col];
__syncthreads();
// Perform multiplication of the tile
for (int e = 0; e < blockSize; ++e)
{
Cvalue += A_s[row][e] * B_s[e][col];
}
__syncthreads();
}
C_tile[row * Bn + col] = Cvalue;
}
////This is a sample implementation without using any memory hierarchy
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
__global__ void Matrix_Multiplication_ATBA_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int l=0;l<Am;l++)
for(int k=0;k<Am;k++)
val+=Ae[l*An+i]*Be[l*Am+k]*Ae[k*An+j];
Ce[i*An+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 2: calculate the matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
__global__ void Matrix_Multiplication_ATBA_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[An * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
for (int m = 0; m < (Am / blockSize); ++m) { // find transpose
const float* A_tile_transpose = &Ae[Am * blockSize * m + tileCol *blockSize];
__shared__ float A_s_tranpose[blockSize][blockSize];
A_s_tranpose[row][col] = A_tile_transpose[row * An + col];
__syncthreads();
for(int i = 0; i < (Am / blockSize); ++i)
{ // order of operations around As Bs
const float* A_tile = &Ae[An * blockSize * i + blockSize * tileRow];
const float* B_tile = &Be[Am * blockSize * m + i * blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col];
B_s[row][col] = B_tile[row * Am + col];
__syncthreads();
for (int l = 0; l < blockSize; ++l)
{
for (int k = 0; k < blockSize; ++k)
{
Cvalue += A_s_tranpose[row][l] * B_s[l][k] * A_s[k][col];
}
}
}
__syncthreads();
}
C_tile[row * An + col] = Cvalue;
/*Your implementation ends*/
}
//////////////////////////////////////////////////////////////////////////
////Task 3: calculate the Frobenius norm of a matrix
////The definition of F-norm for a matrix is square root of (the sum of squares of all the matrix elements), i.e., F=sqrt(sum_(A_ij^2))
////See the definition: https://mathworld.wolfram.com/FrobeniusNorm.html
//////////////////////////////////////////////////////////////////////////
////Please write your own kernel function here, and call it in the function Test_F_Norm_On_GPU to test its correctness and performance
/*Your implementation starts*/
__global__ void Test_F_Norm_On_GPU(const float *Ae, const int An, const int Am, float* norm)
{
const int blockSize = 16;
const int num_threads = blockSize * blockSize;
int global_thread_id = (blockIdx.y * gridDim.x + blockDim.x) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x)+ threadIdx.x;
int local_thread_id = threadIdx.y * blockDim.x+ threadIdx.x;
__shared__ float block_sum[blockSize * blockSize];
block_sum[local_thread_id]= Ae[global_thread_id]; // load into shared memory
block_sum[local_thread_id] *= block_sum[local_thread_id]; // compute the square
__syncthreads();
for(unsigned int i=num_threads/2; i> 0; i/=2){
if(local_thread_id < i) {
block_sum[local_thread_id]+=block_sum[local_thread_id + i];
}
__syncthreads();
}
if(local_thread_id==0) {
atomicAdd(norm, block_sum[0]);
}
}
/*Your implementation ends*/
////Congratulations, your tasks are all finished!
//////////////////////////////////////////////////////////////////////////
////Here are the test functions for your three kernel implementations
ofstream out;
__host__ void Test_Matrix_Multiplication_AB_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.m,B_on_dev.n,false);
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_AB_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
////TODO: Uncomment this to test your own implementation
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_AB_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication AB: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T1: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_Multiplication_ATBA_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.n,A_on_dev.n,false);
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_ATBA_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
////TODO: Uncomment this to test your own implementation.
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_ATBA_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication ATBA: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T2: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_F_Norm_On_GPU(const Matrix& A,/*result*/float& norm)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
////TODO: call the F norm kernel you implemented, and return the value to the passed-in variable norm
const int block_size = 16;
const int block_num_x = A.m/block_size;
const int block_num_y = A.n/block_size;
float* norm_dev;
hipMalloc((void **)&norm_dev, sizeof(float));
hipMemcpy(norm_dev, &norm, sizeof(float), hipMemcpyHostToDevice);
Test_F_Norm_On_GPU<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev, A_on_dev.n, A_on_dev.m, norm_dev);
hipMemcpy(&norm, norm_dev, sizeof(float), hipMemcpyDeviceToHost);
// Calculate the SQRT on host, since this computation is inexpensive
norm = sqrt(norm);
hipFree(norm_dev);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for F norm: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
out<<"T3: "<<gpu_time<<endl;
}
int main()
{
if(name::team=="Team_X"){
printf("\nPlease specify your team name and team member names in name::team and name::author to start.\n");
return 0;
}
std::string file_name=name::team+"_competition_1_matrix.dat";
out.open(file_name.c_str());
if(out.fail()){
printf("\ncannot open file %s to record results\n",file_name.c_str());
return 0;
}
//////////////////////////////////////////////////////////////////////////
////NOTICE: We may use a different set of parameters to evaluate your code.
////So please test your functions with different size and initial values.
//////////////////////////////////////////////////////////////////////////
const int m=512;
const int n=2048;
const int p=1024;
Matrix h_A(m,n);
for(int i=0;i<m;i++){
for(int j=0;j<n;j++){
h_A(i,j)=1.f;
}
}
Matrix h_B(n,p);
for(int i=0;i<n;i++){
for(int j=0;j<p;j++){
h_B(i,j)=1.f;
}
}
Matrix h_C(m,p);
Matrix h_B2(m,m);
for(int i=0;i<m;i++){
for(int j=0;j<m;j++){
h_B2(i,j)=1.f;
}
}
Matrix h_C2(n,n);
Test_Matrix_Multiplication_AB_On_GPU(h_A,h_B,h_C);
cout<<"AB result: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
out<<"R1: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
Test_Matrix_Multiplication_ATBA_On_GPU(h_A,h_B2,h_C2);
cout<<"ATBA result: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
out<<"R2: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
float f_norm=0.f;
Test_Matrix_F_Norm_On_GPU(h_A,f_norm);
cout<<"F-norm result: "<<f_norm<<endl;
out<<"R3: "<<f_norm<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //////////////////////////////////////////////////////////////////////////
////This is the code implementation for GPU Premier League Round 1
//////////////////////////////////////////////////////////////////////////
#include <iostream>
#include <fstream>
#include <vector>
#include <chrono>
#include <hip/hip_runtime.h>
using namespace std;
//////////////////////////////////////////////////////////////////////////
////TODO 0: Please replace the following strings with your team name and author names
////Note: Please do not use space in the string, use "_" instead
//////////////////////////////////////////////////////////////////////////
namespace name
{
std::string team="slim_shaders";
std::string author_1="Andrw_Yang";
std::string author_2="Matthew_Kenney";
};
////This is a matrix class to carry out linear algebra operations on both GPU and CPU
////It is the same as the sample code I showed in class on Week 3.
////NOTICE: You do not have to change the implementation in this class.
////But if you do want to change part of it for performance reasons, please let us known by writting a submission note on Canvas.
class Matrix{
public:
int m=0; ////number of rows
int n=0; ////number of columns
vector<float> elements_on_host; ////we use a std::vector for the element array on host
float* elements_on_dev=0; ////we use a pointer for the element array on device
bool on_host=true;
////constructors
__host__ Matrix(){}
__host__ Matrix(const int _m,const int _n,bool _on_host=true)
{
on_host=_on_host;
if(on_host)Resize_On_Host(_m,_n);
else Resize_On_Device(_m,_n);
}
////destructor
__host__ ~Matrix()
{
if(!on_host&&elements_on_dev!=0) hipFree(elements_on_dev);
}
////Resize on host or device
__host__ void Resize_On_Host(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
elements_on_host.resize(m*n);
}
__host__ void Resize_On_Device(const int _m,const int _n)
{
if(m==_m&&n==_n)return;
m=_m;
n=_n;
if(elements_on_dev!=0)hipFree(elements_on_dev);
hipMalloc((void**)&elements_on_dev,m*n*sizeof(float));
}
////random access a matrix element
inline __host__ float& operator() (const int i,const int j)
{
return elements_on_host[i*n+j];
}
inline __host__ const float& operator() (const int i,const int j) const
{
return elements_on_host[i*n+j];
}
////copy data with four cases (CPU->CPU, GPU->CPU, GPU->GPU, CPU->GPU)
__host__ Matrix& operator= (const Matrix& mtx)
{
if(on_host&&mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
elements_on_host=mtx.elements_on_host;
}
else if(on_host&&!mtx.on_host){
Resize_On_Host(mtx.m,mtx.n);
hipMemcpy(&elements_on_host[0],mtx.elements_on_dev,m*n*sizeof(float),hipMemcpyDeviceToHost);
}
else if(!on_host&&!mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
hipMemcpy(elements_on_dev,mtx.elements_on_dev,mtx.m*n*sizeof(float),hipMemcpyDeviceToDevice);
}
else if(!on_host&&mtx.on_host){
Resize_On_Device(mtx.m,mtx.n);
hipMemcpy(elements_on_dev,&mtx.elements_on_host[0],m*n*sizeof(float),hipMemcpyHostToDevice);
}
return *this;
}
////print matrix elements on screen
__host__ friend ostream & operator << (ostream &out,const Matrix &mtx)
{
if(!mtx.on_host)
cout<<"Print for matrix on device is not supported."<<endl;
for(int i=0;i<mtx.m;i++){
for(int j=0;j<mtx.n;j++){
out<<mtx(i,j)<<", ";
}
out<<std::endl;
}
return out;
}
};
//////////////////////////////////////////////////////////////////////////
////Your tasks start!
////This is a sample implementation without using any memory hierarchy
////The function calculates C=A*B, with dimA=[Am,An], dimB=[Bm,Bn], dimC=[Am,bn], and An=Bm
__global__ void Matrix_Multiplication_AB_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int k=0;k<An;k++)
val+=Ae[i*An+k]*Be[k*Bn+j];
Ce[i*Bn+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 1: implement your fast matrix-matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
/*Your may want to declare your global variables here*/
__global__ void Matrix_Multiplication_AB_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An,const int Bn)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[Bn * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
// iterate over matrix to tile
for (int m = 0; m < (An / blockSize); ++m) {
const float* A_tile = &Ae[An * tileRow * blockSize + m * blockSize]; // tile A and B matrices
const float* B_tile = &Be[Bn * blockSize * m + tileCol *blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col]; // load into shared memory
B_s[row][col] = B_tile[row * Bn + col];
__syncthreads();
// Perform multiplication of the tile
for (int e = 0; e < blockSize; ++e)
{
Cvalue += A_s[row][e] * B_s[e][col];
}
__syncthreads();
}
C_tile[row * Bn + col] = Cvalue;
}
////This is a sample implementation without using any memory hierarchy
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
__global__ void Matrix_Multiplication_ATBA_Kernel_Poorman(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
int i=blockIdx.x*blockDim.x+threadIdx.x;
int j=blockIdx.y*blockDim.y+threadIdx.y;
float val=0.f;
for(int l=0;l<Am;l++)
for(int k=0;k<Am;k++)
val+=Ae[l*An+i]*Be[l*Am+k]*Ae[k*An+j];
Ce[i*An+j]=val;
}
//////////////////////////////////////////////////////////////////////////
////Task 2: calculate the matrix multiplication in the following kernel function.
////The function parameters are the same as the sample function:
////The function calculates the matrix multiplication, with C=A^T*B*A, A^T is the transpose of A, dimA=[Am,An], dimB=[Am,Am], and dimC=[An,An]
//////////////////////////////////////////////////////////////////////////
__global__ void Matrix_Multiplication_ATBA_Kernel_Your_Version(const float* Ae,const float* Be,float* Ce,const int Am,const int An)
{
/*Your implementation starts*/
const int blockSize = 16;
int tileRow = blockIdx.x;
int tileCol = blockIdx.y;
int row = threadIdx.x;
int col = threadIdx.y;
float* C_tile = &Ce[An * blockSize * tileRow + blockSize * tileCol];
float Cvalue = 0;
for (int m = 0; m < (Am / blockSize); ++m) { // find transpose
const float* A_tile_transpose = &Ae[Am * blockSize * m + tileCol *blockSize];
__shared__ float A_s_tranpose[blockSize][blockSize];
A_s_tranpose[row][col] = A_tile_transpose[row * An + col];
__syncthreads();
for(int i = 0; i < (Am / blockSize); ++i)
{ // order of operations around As Bs
const float* A_tile = &Ae[An * blockSize * i + blockSize * tileRow];
const float* B_tile = &Be[Am * blockSize * m + i * blockSize];
__shared__ float A_s[blockSize][blockSize];
__shared__ float B_s[blockSize][blockSize];
A_s[row][col] = A_tile[row * An + col];
B_s[row][col] = B_tile[row * Am + col];
__syncthreads();
for (int l = 0; l < blockSize; ++l)
{
for (int k = 0; k < blockSize; ++k)
{
Cvalue += A_s_tranpose[row][l] * B_s[l][k] * A_s[k][col];
}
}
}
__syncthreads();
}
C_tile[row * An + col] = Cvalue;
/*Your implementation ends*/
}
//////////////////////////////////////////////////////////////////////////
////Task 3: calculate the Frobenius norm of a matrix
////The definition of F-norm for a matrix is square root of (the sum of squares of all the matrix elements), i.e., F=sqrt(sum_(A_ij^2))
////See the definition: https://mathworld.wolfram.com/FrobeniusNorm.html
//////////////////////////////////////////////////////////////////////////
////Please write your own kernel function here, and call it in the function Test_F_Norm_On_GPU to test its correctness and performance
/*Your implementation starts*/
__global__ void Test_F_Norm_On_GPU(const float *Ae, const int An, const int Am, float* norm)
{
const int blockSize = 16;
const int num_threads = blockSize * blockSize;
int global_thread_id = (blockIdx.y * gridDim.x + blockDim.x) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x)+ threadIdx.x;
int local_thread_id = threadIdx.y * blockDim.x+ threadIdx.x;
__shared__ float block_sum[blockSize * blockSize];
block_sum[local_thread_id]= Ae[global_thread_id]; // load into shared memory
block_sum[local_thread_id] *= block_sum[local_thread_id]; // compute the square
__syncthreads();
for(unsigned int i=num_threads/2; i> 0; i/=2){
if(local_thread_id < i) {
block_sum[local_thread_id]+=block_sum[local_thread_id + i];
}
__syncthreads();
}
if(local_thread_id==0) {
atomicAdd(norm, block_sum[0]);
}
}
/*Your implementation ends*/
////Congratulations, your tasks are all finished!
//////////////////////////////////////////////////////////////////////////
////Here are the test functions for your three kernel implementations
ofstream out;
__host__ void Test_Matrix_Multiplication_AB_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.m,B_on_dev.n,false);
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_AB_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
////TODO: Uncomment this to test your own implementation
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_AB_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n,B_on_dev.n);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication AB: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T1: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_Multiplication_ATBA_On_GPU(const Matrix& A,const Matrix& B,Matrix& C)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
Matrix B_on_dev(B.m,B.n,false);
B_on_dev=B;
//// Allocate C in device memory
Matrix C_on_dev(A_on_dev.n,A_on_dev.n,false);
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
const int block_size=16;
const int block_num_x=C.m/block_size;
const int block_num_y=C.n/block_size;
////TODO: this is a sample implementation. Comment it out to test your own code.
// Matrix_Multiplication_ATBA_Kernel_Poorman<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
// (A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
////TODO: Uncomment this to test your own implementation.
////NOTICE: You do not have to use the block_size I specified here. You may customize the size of your grid and blocks for better performance.
Matrix_Multiplication_ATBA_Kernel_Your_Version<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev,B_on_dev.elements_on_dev,C_on_dev.elements_on_dev,A_on_dev.m,A_on_dev.n);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for matrix multiplication ATBA: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
//// Transfer data back to CPU
C=C_on_dev;
out<<"T2: "<<gpu_time<<endl;
}
__host__ void Test_Matrix_F_Norm_On_GPU(const Matrix& A,/*result*/float& norm)
{
//// Load A and B to device memory
Matrix A_on_dev(A.m,A.n,false);
A_on_dev=A;
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
float gpu_time=0.0f;
hipDeviceSynchronize();
hipEventRecord(start);
//// Invoke kernel
////TODO: call the F norm kernel you implemented, and return the value to the passed-in variable norm
const int block_size = 16;
const int block_num_x = A.m/block_size;
const int block_num_y = A.n/block_size;
float* norm_dev;
hipMalloc((void **)&norm_dev, sizeof(float));
hipMemcpy(norm_dev, &norm, sizeof(float), hipMemcpyHostToDevice);
Test_F_Norm_On_GPU<<<dim3(block_num_x,block_num_y),dim3(block_size,block_size)>>>
(A_on_dev.elements_on_dev, A_on_dev.n, A_on_dev.m, norm_dev);
hipMemcpy(&norm, norm_dev, sizeof(float), hipMemcpyDeviceToHost);
// Calculate the SQRT on host, since this computation is inexpensive
norm = sqrt(norm);
hipFree(norm_dev);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&gpu_time,start,end);
printf("\nGPU runtime for F norm: %.4f ms\n",gpu_time);
hipEventDestroy(start);
hipEventDestroy(end);
out<<"T3: "<<gpu_time<<endl;
}
int main()
{
if(name::team=="Team_X"){
printf("\nPlease specify your team name and team member names in name::team and name::author to start.\n");
return 0;
}
std::string file_name=name::team+"_competition_1_matrix.dat";
out.open(file_name.c_str());
if(out.fail()){
printf("\ncannot open file %s to record results\n",file_name.c_str());
return 0;
}
//////////////////////////////////////////////////////////////////////////
////NOTICE: We may use a different set of parameters to evaluate your code.
////So please test your functions with different size and initial values.
//////////////////////////////////////////////////////////////////////////
const int m=512;
const int n=2048;
const int p=1024;
Matrix h_A(m,n);
for(int i=0;i<m;i++){
for(int j=0;j<n;j++){
h_A(i,j)=1.f;
}
}
Matrix h_B(n,p);
for(int i=0;i<n;i++){
for(int j=0;j<p;j++){
h_B(i,j)=1.f;
}
}
Matrix h_C(m,p);
Matrix h_B2(m,m);
for(int i=0;i<m;i++){
for(int j=0;j<m;j++){
h_B2(i,j)=1.f;
}
}
Matrix h_C2(n,n);
Test_Matrix_Multiplication_AB_On_GPU(h_A,h_B,h_C);
cout<<"AB result: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
out<<"R1: "<<h_C(h_C.m/2,h_C.n/2)<<endl;
Test_Matrix_Multiplication_ATBA_On_GPU(h_A,h_B2,h_C2);
cout<<"ATBA result: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
out<<"R2: "<<h_C2(h_C2.m/3,h_C2.n/3)<<endl;
float f_norm=0.f;
Test_Matrix_F_Norm_On_GPU(h_A,f_norm);
cout<<"F-norm result: "<<f_norm<<endl;
out<<"R3: "<<f_norm<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii
.globl _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii
.p2align 8
.type _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii,@function
_Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii, .Lfunc_end0-_Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii
.globl _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii
.p2align 8
.type _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii,@function
_Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s4, s15, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s5, s3, 4
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB1_5
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[6:7], null, v3, s3, v[0:1]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_lshlrev_b32_e32 v4, 6, v3
s_ashr_i32 s6, s2, 31
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
s_lshr_b32 s6, s6, 28
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_nc_u32_e32 v1, v4, v5
v_add_nc_u32_e32 v5, 0x400, v5
v_lshlrev_b64 v[10:11], 2, v[6:7]
s_add_i32 s6, s2, s6
s_mul_i32 s2, s14, s2
s_ashr_i32 s6, s6, 4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v11, vcc_lo
v_add_nc_u32_e32 v10, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_add_i32 s8, s7, s2
s_mul_i32 s9, s7, s5
s_lshl_b32 s8, s8, 4
s_add_i32 s10, s9, s4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v1, v12
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v12, s8, v4
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB1_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_mul_i32 s2, s5, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[2:3], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii, .Lfunc_end1-_Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii
.globl _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii
.p2align 8
.type _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii,@function
_Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s8, s9
s_mov_b32 s12, s9
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_2:
v_mad_u64_u32 v[2:3], null, s12, s3, v[0:1]
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s13, s2
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[2:3], off
v_mov_b32_e32 v2, v1
.p2align 6
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s14, s[10:11], 0x0
s_add_i32 s13, s13, -1
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s3, v2
s_cmp_eq_u32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f32_e32 v6, s14, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
s_cbranch_scc0 .LBB2_3
s_add_i32 s12, s12, 1
s_add_i32 s8, s8, s2
s_cmp_eq_u32 s12, s2
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_6
.LBB2_5:
v_mov_b32_e32 v4, 0
.LBB2_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii, .Lfunc_end2-_Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii
.globl _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii
.p2align 8
.type _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii,@function
_Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii:
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s6, s15, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s7, s3, 4
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB3_9
s_load_b128 s[16:19], s[0:1], 0x0
v_mad_u64_u32 v[5:6], null, v3, s3, v[0:1]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_lshlrev_b32_e32 v8, 2, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b32_e32 v4, 6, v3
s_ashr_i32 s4, s2, 31
v_ashrrev_i32_e32 v6, 31, v5
s_lshr_b32 s4, s4, 28
s_lshl_b32 s8, s2, 4
s_add_i32 s2, s2, s4
s_lshl_b32 s9, s14, 4
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_nc_u32_e32 v5, 0x400, v8
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_ashr_i32 s2, s2, 4
s_mov_b32 s5, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s16, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v7, vcc_lo
v_add_nc_u32_e32 v7, v4, v8
v_add_co_u32 v9, vcc_lo, s18, v9
v_add_nc_u32_e32 v8, v5, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v11, 0x800, v7
.LBB3_2:
s_mul_i32 s11, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, s6
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v12, vcc_lo, v1, s12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v6, vcc_lo
s_mov_b32 s12, s5
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB3_3:
s_mul_i32 s4, s12, s7
s_movk_i32 s13, 0x800
s_add_i32 s16, s4, s9
s_lshl_b32 s4, s12, 4
s_ashr_i32 s17, s16, 31
s_add_i32 s4, s4, s11
s_lshl_b64 s[16:17], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v12, vcc_lo, v1, s16
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v6, vcc_lo
s_lshl_b64 s[16:17], s[4:5], 2
s_mov_b32 s4, 0
v_add_co_u32 v14, vcc_lo, v9, s16
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v10, vcc_lo
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
s_waitcnt vmcnt(1)
ds_store_b32 v8, v12
s_waitcnt vmcnt(0)
ds_store_b32 v11, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB3_4:
v_lshl_add_u32 v12, s4, 2, v4
v_mov_b32_e32 v13, v5
s_mov_b32 s15, 0
ds_load_b32 v12, v12
.LBB3_5:
s_add_i32 s16, s13, s15
s_add_i32 s15, s15, 4
v_mov_b32_e32 v14, s16
s_cmp_eq_u32 s15, 64
ds_load_b32 v14, v14
ds_load_b32 v15, v13
s_waitcnt lgkmcnt(1)
v_dual_mul_f32 v14, v12, v14 :: v_dual_add_nc_u32 v13, 64, v13
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB3_5
s_add_i32 s4, s4, 1
s_add_i32 s13, s13, 64
s_cmp_eq_u32 s4, 16
s_cbranch_scc0 .LBB3_4
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s2
s_cbranch_scc0 .LBB3_3
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB3_2
.LBB3_9:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_mul_i32 s2, s7, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s6
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[2:3], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii, .Lfunc_end3-_Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18Test_F_Norm_On_GPUPKfiiPf
.globl _Z18Test_F_Norm_On_GPUPKfiiPf
.p2align 8
.type _Z18Test_F_Norm_On_GPUPKfiiPf,@function
_Z18Test_F_Norm_On_GPUPKfiiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mul_i32 s5, s5, s15
v_mad_u32_u24 v0, v0, s6, v1
s_lshr_b32 s4, s4, 16
s_add_i32 s5, s5, s6
s_mul_i32 s4, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_movk_i32 s2, 0x80
global_load_b32 v2, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v2, v2 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB4_2
.p2align 6
.LBB4_1:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_4
.LBB4_2:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB4_1
v_add_lshl_u32 v2, s2, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB4_1
.LBB4_4:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB4_8
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_ubyte0_e32 v1, s2
v_mov_b32_e32 v2, 0
s_mov_b32 s2, 0
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
v_mul_f32_e32 v3, v0, v1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB4_7:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB4_7
.LBB4_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18Test_F_Norm_On_GPUPKfiiPf
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z18Test_F_Norm_On_GPUPKfiiPf, .Lfunc_end4-_Z18Test_F_Norm_On_GPUPKfiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z39Matrix_Multiplication_AB_Kernel_PoormanPKfS0_Pfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z44Matrix_Multiplication_AB_Kernel_Your_VersionPKfS0_Pfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z41Matrix_Multiplication_ATBA_Kernel_PoormanPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z46Matrix_Multiplication_ATBA_Kernel_Your_VersionPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18Test_F_Norm_On_GPUPKfiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18Test_F_Norm_On_GPUPKfiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} | code for sm_80
Function : _Z11OPT_4_SIZESPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000168000c1e1900 */
/*00d0*/ @P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402060981 */
/* 0x000168000c1e1900 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x3d0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fd200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe20003f05270 */
/*0140*/ BSSY B0, 0x390 ; /* 0x0000024000007945 */
/* 0x000fd80003800000 */
/*0150*/ @!P0 BRA 0x380 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0160*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.WIDE R2, R11, R2, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fca00078e0202 */
/*01a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ @P0 LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402080981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ BSSY B1, 0x370 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fc80003f06270 */
/*01f0*/ ISETP.GE.OR P0, PT, R6, R9, P0 ; /* 0x000000090600720c */
/* 0x020fda0000706670 */
/*0200*/ @P0 BRA 0x360 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0205 */
/*0240*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe400078e0205 */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0270*/ BSSY B2, 0x320 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0280*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f06270 */
/*0290*/ @!P0 BRA 0x300 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe40003f06270 */
/*02b0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fd60007ffe0ff */
/*02c0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*02d0*/ @!P0 BRA 0x310 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02f0*/ BRA 0x360 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06270 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.LT.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f21270 */
/*0350*/ @!P0 BRA P1, 0x220 ; /* 0xfffffec000008947 */
/* 0x000fea000083ffff */
/*0360*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R7, R7, R4, RZ ; /* 0x0000000407077210 */
/* 0x000fe40007ffe0ff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03a0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fda0003f06270 */
/*03c0*/ @!P0 BRA 0x130 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} | .file "tmpxft_00017b30_00000000-6_OPT_4_SIZES.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11OPT_4_SIZESPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
.globl _Z11OPT_4_SIZESPiS_S_i
.type _Z11OPT_4_SIZESPiS_S_i, @function
_Z11OPT_4_SIZESPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11OPT_4_SIZESPiS_S_i, .-_Z11OPT_4_SIZESPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11OPT_4_SIZESPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11OPT_4_SIZESPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11OPT_4_SIZESPiS_S_i
.globl _Z11OPT_4_SIZESPiS_S_i
.p2align 8
.type _Z11OPT_4_SIZESPiS_S_i,@function
_Z11OPT_4_SIZESPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_24
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s10, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_22
s_load_b64 s[6:7], s[0:1], 0x0
v_cmp_lt_i32_e32 vcc_lo, v0, v8
v_mov_b32_e32 v7, 0
s_mov_b32 s9, 0
s_add_u32 s11, s4, -4
s_addc_u32 s12, s5, -1
s_mov_b32 s8, s9
s_branch .LBB0_8
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s18, exec_lo
s_or_b32 s14, s2, s3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s15
v_cndmask_b32_e64 v3, 0, 1, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s10
s_cbranch_scc1 .LBB0_23
.LBB0_8:
s_mov_b32 s13, exec_lo
v_cmpx_ne_u32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_cmp_eq_u32 s8, 0
s_mov_b32 s2, 0
s_cbranch_scc1 .LBB0_11
s_lshl_b64 s[2:3], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s11, s2
s_addc_u32 s3, s12, s3
s_load_b32 s2, s[2:3], 0x0
.LBB0_11:
s_lshl_b64 s[14:15], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s4, s14
s_addc_u32 s15, s5, s15
s_load_b32 s16, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, s16
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, vcc_lo, s3
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v3, s2
v_mov_b32_e32 v5, v0
s_mov_b32 s17, 0
s_mov_b32 s3, s14
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_or_b32 s17, s2, s17
s_and_not1_b32 s2, s18, exec_lo
s_and_b32 s18, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s18, s2, s18
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_5
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s20, 0
s_mov_b32 s22, exec_lo
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_co_u32 v9, s2, s6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_clause 0x1
global_load_b32 v4, v[9:10], off
global_load_b32 v6, v[11:12], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v4, v6
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_18
v_cmp_lt_i32_e64 s2, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s21, s2
s_xor_b32 s2, exec_lo, s21
s_mov_b32 s20, exec_lo
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s3, s3, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s21, s3, exec_lo
s_and_b32 s20, s20, exec_lo
.LBB0_18:
s_and_not1_saveexec_b32 s2, s22
v_add_nc_u32_e32 v5, 1, v5
s_and_not1_b32 s21, s21, exec_lo
s_or_b32 s20, s20, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s3, s19, exec_lo
s_and_b32 s19, s21, exec_lo
s_mov_b32 s2, -1
s_or_b32 s19, s3, s19
s_and_saveexec_b32 s21, s20
s_cbranch_execz .LBB0_13
v_cmp_lt_i32_e64 s2, v5, v8
v_cmp_gt_i32_e64 s3, s16, v3
s_and_not1_b32 s19, s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 s3, s2, exec_lo
s_xor_b32 s2, s2, -1
s_or_b32 s19, s19, s3
s_or_not1_b32 s2, s2, exec_lo
s_branch .LBB0_13
.LBB0_22:
v_mov_b32_e32 v7, 0
.LBB0_23:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11OPT_4_SIZESPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11OPT_4_SIZESPiS_S_i, .Lfunc_end0-_Z11OPT_4_SIZESPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11OPT_4_SIZESPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z11OPT_4_SIZESPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_SIZES(int *d_adjList, int *d_sizeAdj, int *d_LCMSize, int n_vertices)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i<n_vertices)
{
int indexUsed = 0;
int iStart = 0, iEnd = 0;
int k = 0;
if(i > 0)
{
k = d_sizeAdj[i-1];
}
iEnd = d_sizeAdj[i];
__syncthreads();
for(int j = 0; j < n_vertices; j++) {
if(i==j)
continue;
iStart = k;
int jStart = 0, jEnd = 0;
if(j > 0)
jStart = d_sizeAdj[j-1];
jEnd = d_sizeAdj[j];
int compVec = 0;
while (iStart < iEnd && jStart < jEnd)
{
if(d_adjList[iStart] < d_adjList[jStart])
iStart++;
else if (d_adjList[jStart] < d_adjList[iStart])
jStart++;
else // if arr1[i] == arr2[j]
{
jStart++;
iStart++;
compVec++;
break;
}
}
if (compVec > 0)
{
indexUsed++;
}
}
__syncthreads();
d_LCMSize[i] = indexUsed;
// __syncthreads();
}
} | .text
.file "OPT_4_SIZES.hip"
.globl _Z26__device_stub__OPT_4_SIZESPiS_S_i # -- Begin function _Z26__device_stub__OPT_4_SIZESPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__OPT_4_SIZESPiS_S_i,@function
_Z26__device_stub__OPT_4_SIZESPiS_S_i: # @_Z26__device_stub__OPT_4_SIZESPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11OPT_4_SIZESPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__OPT_4_SIZESPiS_S_i, .Lfunc_end0-_Z26__device_stub__OPT_4_SIZESPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11OPT_4_SIZESPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11OPT_4_SIZESPiS_S_i,@object # @_Z11OPT_4_SIZESPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11OPT_4_SIZESPiS_S_i
.p2align 3, 0x0
_Z11OPT_4_SIZESPiS_S_i:
.quad _Z26__device_stub__OPT_4_SIZESPiS_S_i
.size _Z11OPT_4_SIZESPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11OPT_4_SIZESPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__OPT_4_SIZESPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11OPT_4_SIZESPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11OPT_4_SIZESPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000168000c1e1900 */
/*00d0*/ @P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402060981 */
/* 0x000168000c1e1900 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x3d0 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fd200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe20003f05270 */
/*0140*/ BSSY B0, 0x390 ; /* 0x0000024000007945 */
/* 0x000fd80003800000 */
/*0150*/ @!P0 BRA 0x380 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0160*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.WIDE R2, R11, R2, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fca00078e0202 */
/*01a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ @P0 LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402080981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ BSSY B1, 0x370 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fc80003f06270 */
/*01f0*/ ISETP.GE.OR P0, PT, R6, R9, P0 ; /* 0x000000090600720c */
/* 0x020fda0000706670 */
/*0200*/ @P0 BRA 0x360 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0205 */
/*0240*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe400078e0205 */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0270*/ BSSY B2, 0x320 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0280*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f06270 */
/*0290*/ @!P0 BRA 0x300 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe40003f06270 */
/*02b0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fd60007ffe0ff */
/*02c0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*02d0*/ @!P0 BRA 0x310 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02f0*/ BRA 0x360 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06270 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.LT.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f21270 */
/*0350*/ @!P0 BRA P1, 0x220 ; /* 0xfffffec000008947 */
/* 0x000fea000083ffff */
/*0360*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R7, R7, R4, RZ ; /* 0x0000000407077210 */
/* 0x000fe40007ffe0ff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03a0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fda0003f06270 */
/*03c0*/ @!P0 BRA 0x130 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11OPT_4_SIZESPiS_S_i
.globl _Z11OPT_4_SIZESPiS_S_i
.p2align 8
.type _Z11OPT_4_SIZESPiS_S_i,@function
_Z11OPT_4_SIZESPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_24
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s10, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_22
s_load_b64 s[6:7], s[0:1], 0x0
v_cmp_lt_i32_e32 vcc_lo, v0, v8
v_mov_b32_e32 v7, 0
s_mov_b32 s9, 0
s_add_u32 s11, s4, -4
s_addc_u32 s12, s5, -1
s_mov_b32 s8, s9
s_branch .LBB0_8
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s18, exec_lo
s_or_b32 s14, s2, s3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s15
v_cndmask_b32_e64 v3, 0, 1, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s10
s_cbranch_scc1 .LBB0_23
.LBB0_8:
s_mov_b32 s13, exec_lo
v_cmpx_ne_u32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_cmp_eq_u32 s8, 0
s_mov_b32 s2, 0
s_cbranch_scc1 .LBB0_11
s_lshl_b64 s[2:3], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s11, s2
s_addc_u32 s3, s12, s3
s_load_b32 s2, s[2:3], 0x0
.LBB0_11:
s_lshl_b64 s[14:15], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s4, s14
s_addc_u32 s15, s5, s15
s_load_b32 s16, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, s16
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, vcc_lo, s3
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v3, s2
v_mov_b32_e32 v5, v0
s_mov_b32 s17, 0
s_mov_b32 s3, s14
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_or_b32 s17, s2, s17
s_and_not1_b32 s2, s18, exec_lo
s_and_b32 s18, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s18, s2, s18
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_5
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s20, 0
s_mov_b32 s22, exec_lo
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_co_u32 v9, s2, s6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_clause 0x1
global_load_b32 v4, v[9:10], off
global_load_b32 v6, v[11:12], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v4, v6
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_18
v_cmp_lt_i32_e64 s2, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s21, s2
s_xor_b32 s2, exec_lo, s21
s_mov_b32 s20, exec_lo
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s3, s3, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s21, s3, exec_lo
s_and_b32 s20, s20, exec_lo
.LBB0_18:
s_and_not1_saveexec_b32 s2, s22
v_add_nc_u32_e32 v5, 1, v5
s_and_not1_b32 s21, s21, exec_lo
s_or_b32 s20, s20, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s3, s19, exec_lo
s_and_b32 s19, s21, exec_lo
s_mov_b32 s2, -1
s_or_b32 s19, s3, s19
s_and_saveexec_b32 s21, s20
s_cbranch_execz .LBB0_13
v_cmp_lt_i32_e64 s2, v5, v8
v_cmp_gt_i32_e64 s3, s16, v3
s_and_not1_b32 s19, s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 s3, s2, exec_lo
s_xor_b32 s2, s2, -1
s_or_b32 s19, s19, s3
s_or_not1_b32 s2, s2, exec_lo
s_branch .LBB0_13
.LBB0_22:
v_mov_b32_e32 v7, 0
.LBB0_23:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11OPT_4_SIZESPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11OPT_4_SIZESPiS_S_i, .Lfunc_end0-_Z11OPT_4_SIZESPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11OPT_4_SIZESPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z11OPT_4_SIZESPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017b30_00000000-6_OPT_4_SIZES.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11OPT_4_SIZESPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
.globl _Z11OPT_4_SIZESPiS_S_i
.type _Z11OPT_4_SIZESPiS_S_i, @function
_Z11OPT_4_SIZESPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11OPT_4_SIZESPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11OPT_4_SIZESPiS_S_i, .-_Z11OPT_4_SIZESPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11OPT_4_SIZESPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11OPT_4_SIZESPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "OPT_4_SIZES.hip"
.globl _Z26__device_stub__OPT_4_SIZESPiS_S_i # -- Begin function _Z26__device_stub__OPT_4_SIZESPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__OPT_4_SIZESPiS_S_i,@function
_Z26__device_stub__OPT_4_SIZESPiS_S_i: # @_Z26__device_stub__OPT_4_SIZESPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11OPT_4_SIZESPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__OPT_4_SIZESPiS_S_i, .Lfunc_end0-_Z26__device_stub__OPT_4_SIZESPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11OPT_4_SIZESPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11OPT_4_SIZESPiS_S_i,@object # @_Z11OPT_4_SIZESPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11OPT_4_SIZESPiS_S_i
.p2align 3, 0x0
_Z11OPT_4_SIZESPiS_S_i:
.quad _Z26__device_stub__OPT_4_SIZESPiS_S_i
.size _Z11OPT_4_SIZESPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11OPT_4_SIZESPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__OPT_4_SIZESPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11OPT_4_SIZESPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void bhsm_forward_backward(
const float *x,
const float *w,
const int *ts,
const int *paths,
const float *codes,
const int *begins,
const int n_in,
const int max_len,
const int n_ex,
float *ls,
float *gx,
float *gW
) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n_ex * max_len) {
int idx = i / max_len;
int offset = i - idx * max_len;
int t = ts[idx];
int begin = begins[t];
int length = begins[t+1] - begin;
if (offset < length) {
int p = begin + offset;
int node = paths[p];
float wx = 0;
int w_start = n_in * node;
int x_start = n_in * idx;
for (int j = 0; j < n_in; ++j) {
// int w_i = w_start + j;
// int x_i = x_start + j;
// wx += (w[w_i] * x[x_i]);
wx +=(w[w_start + j] * x[x_start + j]);
}
wx *= codes[p];
float g = -codes[p] / (1.0f + exp(wx));
ls[i] = log(1 + exp(-wx));
for (int j = 0; j < n_in; ++j) {
int w_i = w_start + j;
int x_i = x_start + j;
// gx[x_i] += g * w[w_i];
// gW[w_i] += g * x[x_i];
atomicAdd(gx + x_i, g * w[w_i]);
atomicAdd(gW + w_i, g * x[x_i]);
}
}
}
} | .file "tmpxft_000b0ba7_00000000-6_bhsm_forward_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
.type _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_, @function
_Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 296(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq bhsm_forward_backward(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_, .-_Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
.globl bhsm_forward_backward
.type bhsm_forward_backward, @function
bhsm_forward_backward:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size bhsm_forward_backward, .-bhsm_forward_backward
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "bhsm_forward_backward"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq bhsm_forward_backward(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void bhsm_forward_backward(
const float *x,
const float *w,
const int *ts,
const int *paths,
const float *codes,
const int *begins,
const int n_in,
const int max_len,
const int n_ex,
float *ls,
float *gx,
float *gW
) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n_ex * max_len) {
int idx = i / max_len;
int offset = i - idx * max_len;
int t = ts[idx];
int begin = begins[t];
int length = begins[t+1] - begin;
if (offset < length) {
int p = begin + offset;
int node = paths[p];
float wx = 0;
int w_start = n_in * node;
int x_start = n_in * idx;
for (int j = 0; j < n_in; ++j) {
// int w_i = w_start + j;
// int x_i = x_start + j;
// wx += (w[w_i] * x[x_i]);
wx +=(w[w_start + j] * x[x_start + j]);
}
wx *= codes[p];
float g = -codes[p] / (1.0f + exp(wx));
ls[i] = log(1 + exp(-wx));
for (int j = 0; j < n_in; ++j) {
int w_i = w_start + j;
int x_i = x_start + j;
// gx[x_i] += g * w[w_i];
// gW[w_i] += g * x[x_i];
atomicAdd(gx + x_i, g * w[w_i]);
atomicAdd(gW + w_i, g * x[x_i]);
}
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void bhsm_forward_backward(
const float *x,
const float *w,
const int *ts,
const int *paths,
const float *codes,
const int *begins,
const int n_in,
const int max_len,
const int n_ex,
float *ls,
float *gx,
float *gW
) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n_ex * max_len) {
int idx = i / max_len;
int offset = i - idx * max_len;
int t = ts[idx];
int begin = begins[t];
int length = begins[t+1] - begin;
if (offset < length) {
int p = begin + offset;
int node = paths[p];
float wx = 0;
int w_start = n_in * node;
int x_start = n_in * idx;
for (int j = 0; j < n_in; ++j) {
// int w_i = w_start + j;
// int x_i = x_start + j;
// wx += (w[w_i] * x[x_i]);
wx +=(w[w_start + j] * x[x_start + j]);
}
wx *= codes[p];
float g = -codes[p] / (1.0f + exp(wx));
ls[i] = log(1 + exp(-wx));
for (int j = 0; j < n_in; ++j) {
int w_i = w_start + j;
int x_i = x_start + j;
// gx[x_i] += g * w[w_i];
// gW[w_i] += g * x[x_i];
atomicAdd(gx + x_i, g * w[w_i]);
atomicAdd(gW + w_i, g * x[x_i]);
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void bhsm_forward_backward(
const float *x,
const float *w,
const int *ts,
const int *paths,
const float *codes,
const int *begins,
const int n_in,
const int max_len,
const int n_ex,
float *ls,
float *gx,
float *gW
) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n_ex * max_len) {
int idx = i / max_len;
int offset = i - idx * max_len;
int t = ts[idx];
int begin = begins[t];
int length = begins[t+1] - begin;
if (offset < length) {
int p = begin + offset;
int node = paths[p];
float wx = 0;
int w_start = n_in * node;
int x_start = n_in * idx;
for (int j = 0; j < n_in; ++j) {
// int w_i = w_start + j;
// int x_i = x_start + j;
// wx += (w[w_i] * x[x_i]);
wx +=(w[w_start + j] * x[x_start + j]);
}
wx *= codes[p];
float g = -codes[p] / (1.0f + exp(wx));
ls[i] = log(1 + exp(-wx));
for (int j = 0; j < n_in; ++j) {
int w_i = w_start + j;
int x_i = x_start + j;
// gx[x_i] += g * w[w_i];
// gW[w_i] += g * x[x_i];
atomicAdd(gx + x_i, g * w[w_i]);
atomicAdd(gW + w_i, g * x[x_i]);
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected bhsm_forward_backward
.globl bhsm_forward_backward
.p2align 8
.type bhsm_forward_backward,@function
bhsm_forward_backward:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x64
s_load_b64 s[2:3], s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s3, s3, s2
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_13
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v2, 31, v4
s_add_i32 s4, s2, s3
s_load_b64 s[6:7], s[0:1], 0x28
s_xor_b32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v0, s4
v_add_nc_u32_e32 v3, v4, v2
s_sub_i32 s5, 0, s4
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v2
v_xor_b32_e32 v2, s3, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s5, v0
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s4
v_sub_nc_u32_e32 v1, v3, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v0, v0, v3 :: v_dual_cndmask_b32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_sub_nc_u32_e32 v0, v4, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v3, v2
v_cmp_lt_i32_e32 vcc_lo, v0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x18
v_add_nc_u32_e32 v5, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_clause 0x1
s_load_b32 s8, s[0:1], 0x30
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s8
s_cmp_lt_i32 s8, 1
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, s8
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s2, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
.LBB0_4:
global_load_b32 v1, v[9:10], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v1, v11
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
.LBB0_6:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[10:11], s[0:1], 0x40
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_cmp_lt_i32 s8, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0xbfb8aa3b, v3
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v3
v_fma_f32 v6, v3, 0xbfb8aa3b, -v5
v_rndne_f32_e32 v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v6, v3, 0xb2a5705f, v6 :: v_dual_sub_f32 v5, v5, v7
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
v_add_f32_e32 v5, 1.0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v5
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
v_mul_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_log_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x3f317217, v6
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
v_fma_f32 v7, v6, 0x3f317217, -v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v6, 0x3377d1cf, v7
v_add_f32_e32 v7, v5, v7
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v8
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_13
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
s_load_b128 s[0:3], s[0:1], 0x48
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v3, 0x3fb8aa3b, -v4
v_sub_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v6, v3, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
v_add_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
v_add_f32_e32 v3, 1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, -v1
v_div_scale_f32 v7, vcc_lo, -v1, v3, -v1
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v4, v3, -v1
.LBB0_8:
v_add_nc_u32_e32 v3, s9, v0
v_add_nc_u32_e32 v5, s9, v2
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v10, v[7:8], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v11, v1, v9
.LBB0_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v9, v10, v11
global_atomic_cmpswap_b32 v9, v[7:8], v[9:10], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v9, v10
v_mov_b32_e32 v10, v9
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s10
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s10, 0
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, v1, v5
.LBB0_11:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v7
global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_11
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, s8
s_cbranch_scc1 .LBB0_8
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel bhsm_forward_backward
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size bhsm_forward_backward, .Lfunc_end0-bhsm_forward_backward
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: bhsm_forward_backward
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: bhsm_forward_backward.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void bhsm_forward_backward(
const float *x,
const float *w,
const int *ts,
const int *paths,
const float *codes,
const int *begins,
const int n_in,
const int max_len,
const int n_ex,
float *ls,
float *gx,
float *gW
) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n_ex * max_len) {
int idx = i / max_len;
int offset = i - idx * max_len;
int t = ts[idx];
int begin = begins[t];
int length = begins[t+1] - begin;
if (offset < length) {
int p = begin + offset;
int node = paths[p];
float wx = 0;
int w_start = n_in * node;
int x_start = n_in * idx;
for (int j = 0; j < n_in; ++j) {
// int w_i = w_start + j;
// int x_i = x_start + j;
// wx += (w[w_i] * x[x_i]);
wx +=(w[w_start + j] * x[x_start + j]);
}
wx *= codes[p];
float g = -codes[p] / (1.0f + exp(wx));
ls[i] = log(1 + exp(-wx));
for (int j = 0; j < n_in; ++j) {
int w_i = w_start + j;
int x_i = x_start + j;
// gx[x_i] += g * w[w_i];
// gW[w_i] += g * x[x_i];
atomicAdd(gx + x_i, g * w[w_i]);
atomicAdd(gW + w_i, g * x[x_i]);
}
}
}
} | .text
.file "bhsm_forward_backward.hip"
.globl __device_stub__bhsm_forward_backward # -- Begin function __device_stub__bhsm_forward_backward
.p2align 4, 0x90
.type __device_stub__bhsm_forward_backward,@function
__device_stub__bhsm_forward_backward: # @__device_stub__bhsm_forward_backward
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $bhsm_forward_backward, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__bhsm_forward_backward, .Lfunc_end0-__device_stub__bhsm_forward_backward
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bhsm_forward_backward, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type bhsm_forward_backward,@object # @bhsm_forward_backward
.section .rodata,"a",@progbits
.globl bhsm_forward_backward
.p2align 3, 0x0
bhsm_forward_backward:
.quad __device_stub__bhsm_forward_backward
.size bhsm_forward_backward, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "bhsm_forward_backward"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__bhsm_forward_backward
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bhsm_forward_backward
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b0ba7_00000000-6_bhsm_forward_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
.type _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_, @function
_Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 296(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq bhsm_forward_backward(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_, .-_Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
.globl bhsm_forward_backward
.type bhsm_forward_backward, @function
bhsm_forward_backward:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z68__device_stub__Z21bhsm_forward_backwardPKfS0_PKiS2_S0_S2_iiiPfS3_S3_PKfS0_PKiS2_S0_S2_iiiPfS3_S3_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size bhsm_forward_backward, .-bhsm_forward_backward
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "bhsm_forward_backward"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq bhsm_forward_backward(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bhsm_forward_backward.hip"
.globl __device_stub__bhsm_forward_backward # -- Begin function __device_stub__bhsm_forward_backward
.p2align 4, 0x90
.type __device_stub__bhsm_forward_backward,@function
__device_stub__bhsm_forward_backward: # @__device_stub__bhsm_forward_backward
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $bhsm_forward_backward, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__bhsm_forward_backward, .Lfunc_end0-__device_stub__bhsm_forward_backward
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bhsm_forward_backward, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type bhsm_forward_backward,@object # @bhsm_forward_backward
.section .rodata,"a",@progbits
.globl bhsm_forward_backward
.p2align 3, 0x0
bhsm_forward_backward:
.quad __device_stub__bhsm_forward_backward
.size bhsm_forward_backward, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "bhsm_forward_backward"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__bhsm_forward_backward
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bhsm_forward_backward
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} | code for sm_80
Function : _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x1b4] ; /* 0x00006d0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x3, URZ ; /* 0xfffffffd04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, 0x40, R0 ; /* 0x0000004003007824 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R16, R5, 0xa000, R0 ; /* 0x0000a00005107824 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.AND P0, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc8000bf04270 */
/*0090*/ ISETP.LT.OR P0, PT, R16, 0x2, P0 ; /* 0x000000021000780c */
/* 0x000fda0000701670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R27, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1b7435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R8, R16, R27, c[0x0][0x188] ; /* 0x0000620010087625 */
/* 0x000fc800078e021b */
/*00e0*/ IMAD.WIDE R10, R16.reuse, R27.reuse, c[0x0][0x160] ; /* 0x00005800100a7625 */
/* 0x0c0fe200078e021b */
/*00f0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x0000a8000c1e1900 */
/*0100*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R22, R16, R27, c[0x0][0x190] ; /* 0x0000640010167625 */
/* 0x000fc800078e021b */
/*0120*/ IMAD.WIDE R2, R16.reuse, R27.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x0c0fe200078e021b */
/*0130*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ee6000c1e1900 */
/*0140*/ IMAD.WIDE R20, R16.reuse, R27.reuse, c[0x0][0x1a0] ; /* 0x0000680010147625 */
/* 0x0c0fe200078e021b */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ee6000c1e1900 */
/*0160*/ IMAD.WIDE R14, R16.reuse, R27.reuse, c[0x0][0x1a8] ; /* 0x00006a00100e7625 */
/* 0x0c0fe400078e021b */
/*0170*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000324000c1e1900 */
/*0180*/ IMAD.WIDE R24, R16, R27, c[0x0][0x198] ; /* 0x0000660010187625 */
/* 0x000fc400078e021b */
/*0190*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f64000c1e1900 */
/*01a0*/ IMAD.WIDE R4, R16.reuse, R27.reuse, c[0x0][0x170] ; /* 0x00005c0010047625 */
/* 0x0c0fe400078e021b */
/*01b0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x000324000c1e1900 */
/*01c0*/ IMAD.WIDE R6, R16.reuse, R27.reuse, c[0x0][0x178] ; /* 0x00005e0010067625 */
/* 0x0c0fe400078e021b */
/*01d0*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x000f24000c1e1900 */
/*01e0*/ IMAD.WIDE R8, R16, R27, c[0x0][0x180] ; /* 0x0000600010087625 */
/* 0x001fc400078e021b */
/*01f0*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000f62000c1e1900 */
/*0210*/ BSSY B0, 0x340 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0220*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fc80000000000 */
/*0230*/ MUFU.RCP R24, R13 ; /* 0x0000000d00187308 */
/* 0x002e220000001000 */
/*0240*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0003e2000c101904 */
/*0250*/ FFMA R22, R17, R0, R12 ; /* 0x0000000011167223 */
/* 0x008fcc000000000c */
/*0260*/ FCHK P0, R22, R13 ; /* 0x0000000d16007302 */
/* 0x000ea20000000000 */
/*0270*/ FFMA R23, -R13, R24, 1 ; /* 0x3f8000000d177423 */
/* 0x001fc80000000118 */
/*0280*/ FFMA R23, R24, R23, R24 ; /* 0x0000001718177223 */
/* 0x000fc80000000018 */
/*0290*/ FFMA R20, R22, R23, RZ ; /* 0x0000001716147223 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R17, -R13, R20, R22 ; /* 0x000000140d117223 */
/* 0x000fe40000000116 */
/*02b0*/ FFMA R12, R0.reuse, R26, R19 ; /* 0x0000001a000c7223 */
/* 0x050fe40000000013 */
/*02c0*/ FFMA R16, R0.reuse, R16, R21 ; /* 0x0000001000107223 */
/* 0x040fe40000000015 */
/*02d0*/ FFMA R17, R23, R17, R20 ; /* 0x0000001117117223 */
/* 0x000fe40000000014 */
/*02e0*/ FFMA R18, R0, R18, R15 ; /* 0x0000001200127223 */
/* 0x020fe2000000000f */
/*02f0*/ @!P0 BRA 0x330 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0300*/ MOV R0, 0x320 ; /* 0x0000032000007802 */
/* 0x002fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0x630 ; /* 0x0000031000007944 */
/* 0x000fea0003c00000 */
/*0320*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x001fe400078e000e */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0340*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0350*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e2000c101904 */
/*0360*/ BSSY B0, 0x430 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0370*/ FCHK P0, R12, R13 ; /* 0x0000000d0c007302 */
/* 0x000ea20000000000 */
/*0380*/ FFMA R11, -R13, R0, 1 ; /* 0x3f8000000d0b7423 */
/* 0x001fc80000000100 */
/*0390*/ FFMA R15, R0, R11, R0 ; /* 0x0000000b000f7223 */
/* 0x000fc80000000000 */
/*03a0*/ FFMA R0, R12, R15, RZ ; /* 0x0000000f0c007223 */
/* 0x000fc800000000ff */
/*03b0*/ FFMA R11, -R13, R0, R12 ; /* 0x000000000d0b7223 */
/* 0x000fc8000000010c */
/*03c0*/ FFMA R11, R15, R11, R0 ; /* 0x0000000b0f0b7223 */
/* 0x000fe20000000000 */
/*03d0*/ @!P0 BRA 0x420 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R22, RZ, RZ, R12 ; /* 0x000000ffff167224 */
/* 0x002fe200078e000c */
/*03f0*/ MOV R0, 0x410 ; /* 0x0000041000007802 */
/* 0x000fe40000000f00 */
/*0400*/ CALL.REL.NOINC 0x630 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0410*/ MOV R11, R14 ; /* 0x0000000e000b7202 */
/* 0x001fe40000000f00 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0430*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0440*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e2000c101904 */
/*0450*/ BSSY B0, 0x520 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0460*/ FCHK P0, R16, R13 ; /* 0x0000000d10007302 */
/* 0x000ea20000000000 */
/*0470*/ FFMA R3, -R13, R0, 1 ; /* 0x3f8000000d037423 */
/* 0x001fc80000000100 */
/*0480*/ FFMA R15, R0, R3, R0 ; /* 0x00000003000f7223 */
/* 0x000fc80000000000 */
/*0490*/ FFMA R0, R16, R15, RZ ; /* 0x0000000f10007223 */
/* 0x000fc800000000ff */
/*04a0*/ FFMA R3, -R13, R0, R16 ; /* 0x000000000d037223 */
/* 0x000fc80000000110 */
/*04b0*/ FFMA R3, R15, R3, R0 ; /* 0x000000030f037223 */
/* 0x000fe20000000000 */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R22, RZ, RZ, R16 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0010 */
/*04e0*/ MOV R0, 0x500 ; /* 0x0000050000007802 */
/* 0x000fe40000000f00 */
/*04f0*/ CALL.REL.NOINC 0x630 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x001fe400078e000e */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0520*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0530*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0003e2000c101904 */
/*0540*/ BSSY B0, 0x610 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0550*/ FCHK P0, R18, R13 ; /* 0x0000000d12007302 */
/* 0x000ea20000000000 */
/*0560*/ FFMA R5, -R13, R0, 1 ; /* 0x3f8000000d057423 */
/* 0x001fc80000000100 */
/*0570*/ FFMA R11, R0, R5, R0 ; /* 0x00000005000b7223 */
/* 0x000fc80000000000 */
/*0580*/ FFMA R0, R18, R11, RZ ; /* 0x0000000b12007223 */
/* 0x000fc800000000ff */
/*0590*/ FFMA R5, -R13, R0, R18 ; /* 0x000000000d057223 */
/* 0x000fc80000000112 */
/*05a0*/ FFMA R5, R11, R5, R0 ; /* 0x000000050b057223 */
/* 0x000fe20000000000 */
/*05b0*/ @!P0 BRA 0x600 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*05c0*/ MOV R22, R18 ; /* 0x0000001200167202 */
/* 0x002fe40000000f00 */
/*05d0*/ MOV R0, 0x5f0 ; /* 0x000005f000007802 */
/* 0x000fe40000000f00 */
/*05e0*/ CALL.REL.NOINC 0x630 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*05f0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000e */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0610*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x000fe2000c101904 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ SHF.R.U32.HI R10, RZ, 0x17, R13 ; /* 0x00000017ff0a7819 */
/* 0x000fe2000001160d */
/*0640*/ BSSY B1, 0xc90 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0650*/ SHF.R.U32.HI R11, RZ, 0x17, R22.reuse ; /* 0x00000017ff0b7819 */
/* 0x100fe20000011616 */
/*0660*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0016 */
/*0670*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*0680*/ LOP3.LUT R17, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b117812 */
/* 0x000fc400078ec0ff */
/*0690*/ IADD3 R20, R10, -0x1, RZ ; /* 0xffffffff0a147810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R19, R17, -0x1, RZ ; /* 0xffffffff11137810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R20, 0xfd, PT ; /* 0x000000fd1400780c */
/* 0x000fe40003f04070 */
/*06c0*/ MOV R15, R13 ; /* 0x0000000d000f7202 */
/* 0x000fe40000000f00 */
/*06d0*/ ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ; /* 0x000000fd1300780c */
/* 0x000fda0000704470 */
/*06e0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*06f0*/ @!P0 BRA 0x870 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0700*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0710*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0730*/ @P0 BRA 0xc70 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT P0, RZ, R15, 0x7fffffff, R14, 0xc8, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fda000780c80e */
/*0750*/ @!P0 BRA 0xc50 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0760*/ FSETP.NEU.FTZ.AND P2, PT, |R22|.reuse, +INF , PT ; /* 0x7f8000001600780b */
/* 0x040fe40003f5d200 */
/*0770*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0790*/ @!P1 BRA !P2, 0xc50 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07a0*/ LOP3.LUT P2, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fc8000784c0ff */
/*07b0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07c0*/ @P1 BRA 0xc30 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT P1, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000782c0ff */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*07f0*/ @P0 BRA 0xc00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f06270 */
/*0810*/ ISETP.GE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fd60003f26270 */
/*0820*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e00ff */
/*0830*/ @!P0 MOV R11, 0xffffffc0 ; /* 0xffffffc0000b8802 */
/* 0x000fe20000000f00 */
/*0840*/ @!P0 FFMA R14, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f800000160e8823 */
/* 0x000fe400000000ff */
/*0850*/ @!P1 FFMA R15, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d0f9823 */
/* 0x000fe200000000ff */
/*0860*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0870*/ LEA R20, R10, 0xc0800000, 0x17 ; /* 0xc08000000a147811 */
/* 0x000fe200078eb8ff */
/*0880*/ BSSY B2, 0xbf0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0890*/ IADD3 R17, R17, -0x7f, RZ ; /* 0xffffff8111117810 */
/* 0x000fc60007ffe0ff */
/*08a0*/ IMAD.IADD R19, R15, 0x1, -R20 ; /* 0x000000010f137824 */
/* 0x000fe400078e0a14 */
/*08b0*/ IMAD R14, R17, -0x800000, R14 ; /* 0xff800000110e7824 */
/* 0x000fe400078e020e */
/*08c0*/ MUFU.RCP R15, R19 ; /* 0x00000013000f7308 */
/* 0x000e220000001000 */
/*08d0*/ FADD.FTZ R21, -R19, -RZ ; /* 0x800000ff13157221 */
/* 0x000fc80000010100 */
/*08e0*/ FFMA R20, R15, R21, 1 ; /* 0x3f8000000f147423 */
/* 0x001fc80000000015 */
/*08f0*/ FFMA R15, R15, R20, R15 ; /* 0x000000140f0f7223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R20, R14, R15, RZ ; /* 0x0000000f0e147223 */
/* 0x000fc800000000ff */
/*0910*/ FFMA R22, R21, R20, R14 ; /* 0x0000001415167223 */
/* 0x000fc8000000000e */
/*0920*/ FFMA R20, R15, R22, R20 ; /* 0x000000160f147223 */
/* 0x000fe20000000014 */
/*0930*/ IADD3 R22, R17, 0x7f, -R10 ; /* 0x0000007f11167810 */
/* 0x000fc60007ffe80a */
/*0940*/ FFMA R21, R21, R20, R14 ; /* 0x0000001415157223 */
/* 0x000fe4000000000e */
/*0950*/ IMAD.IADD R11, R22, 0x1, R11 ; /* 0x00000001160b7824 */
/* 0x000fe400078e020b */
/*0960*/ FFMA R14, R15, R21, R20 ; /* 0x000000150f0e7223 */
/* 0x000fca0000000014 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x17, R14 ; /* 0x00000017ff0a7819 */
/* 0x000fc8000001160e */
/*0980*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fc800078ec0ff */
/*0990*/ IADD3 R17, R10, R11, RZ ; /* 0x0000000b0a117210 */
/* 0x000fc80007ffe0ff */
/*09a0*/ IADD3 R10, R17, -0x1, RZ ; /* 0xffffffff110a7810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*09c0*/ @!P0 BRA 0xbd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*09e0*/ @P0 BRA 0xba0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0a00*/ @P0 BRA 0xbe0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0a20*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000e0e7812 */
/* 0x000fd600078ec0ff */
/*0a30*/ @!P0 BRA 0xbe0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a40*/ FFMA.RZ R10, R15, R21.reuse, R20.reuse ; /* 0x000000150f0a7223 */
/* 0x180fe2000000c014 */
/*0a50*/ ISETP.NE.AND P2, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f45270 */
/*0a60*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0a70*/ LOP3.LUT R11, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0b7812 */
/* 0x000fe200078ec0ff */
/*0a80*/ FFMA.RP R10, R15.reuse, R21.reuse, R20.reuse ; /* 0x000000150f0a7223 */
/* 0x1c0fe40000008014 */
/*0a90*/ FFMA.RM R15, R15, R21, R20 ; /* 0x000000150f0f7223 */
/* 0x000fe20000004014 */
/*0aa0*/ IADD3 R20, R17, 0x20, RZ ; /* 0x0000002011147810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0a11 */
/*0ac0*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fc400078efcff */
/*0ad0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720b */
/* 0x000fe40003f1d000 */
/*0ae0*/ SHF.L.U32 R20, R11, R20, RZ ; /* 0x000000140b147219 */
/* 0x000fe400000006ff */
/*0af0*/ SEL R10, R17, RZ, P2 ; /* 0x000000ff110a7207 */
/* 0x000fe40001000000 */
/*0b00*/ ISETP.NE.AND P1, PT, R20, RZ, P1 ; /* 0x000000ff1400720c */
/* 0x000fe40000f25270 */
/*0b10*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0b30*/ SHF.R.U32.HI R20, RZ, 0x1, R10 ; /* 0x00000001ff147819 */
/* 0x000fe4000001160a */
/*0b40*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0b50*/ LOP3.LUT R11, R11, 0x1, R20, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef814 */
/*0b60*/ LOP3.LUT R11, R11, R10, RZ, 0xc0, !PT ; /* 0x0000000a0b0b7212 */
/* 0x000fca00078ec0ff */
/*0b70*/ IMAD.IADD R11, R20, 0x1, R11 ; /* 0x00000001140b7824 */
/* 0x000fca00078e020b */
/*0b80*/ LOP3.LUT R14, R11, R14, RZ, 0xfc, !PT ; /* 0x0000000e0b0e7212 */
/* 0x000fe200078efcff */
/*0b90*/ BRA 0xbe0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ba0*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000e0e7812 */
/* 0x000fc800078ec0ff */
/*0bb0*/ LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000e0e7812 */
/* 0x000fe200078efcff */
/*0bc0*/ BRA 0xbe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LEA R14, R11, R14, 0x17 ; /* 0x0000000e0b0e7211 */
/* 0x000fe400078eb8ff */
/*0be0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xc80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R14, R15, 0x80000000, R14, 0x48, !PT ; /* 0x800000000f0e7812 */
/* 0x000fc800078e480e */
/*0c10*/ LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000e0e7812 */
/* 0x000fe200078efcff */
/*0c20*/ BRA 0xc80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c30*/ LOP3.LUT R14, R15, 0x80000000, R14, 0x48, !PT ; /* 0x800000000f0e7812 */
/* 0x000fe200078e480e */
/*0c40*/ BRA 0xc80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c50*/ MUFU.RSQ R14, -QNAN ; /* 0xffc00000000e7908 */
/* 0x000e220000001400 */
/*0c60*/ BRA 0xc80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c70*/ FADD.FTZ R14, R22, R13 ; /* 0x0000000d160e7221 */
/* 0x000fe40000010000 */
/*0c80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c90*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0ca0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0000 */
/*0cb0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff3400a007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} | .file "tmpxft_000d06f9_00000000-6_HydroUpdatePrim_CUDA3_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
.type _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi, @function
_Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movss %xmm0, 12(%rsp)
movq 288(%rsp), %rax
movq %rax, 40(%rsp)
movq 296(%rsp), %rax
movq %rax, 32(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 12(%rsp), %rax
movq %rax, 240(%rsp)
leaq 320(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi, .-_Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, @function
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .-_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 8
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@function
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
s_load_b32 s2, s[0:1], 0x54
s_lshl_b32 s3, s14, 6
s_mul_i32 s15, s15, 0xa000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
v_cmp_lt_i32_e32 vcc_lo, 1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x20
s_load_b128 s[0:3], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s15, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v16, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v17, vcc_lo, s19, v1, vcc_lo
v_add_co_u32 v18, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v20, v[2:3], off
global_load_b32 v21, v[4:5], off
global_load_b32 v22, v[6:7], off
global_load_b32 v23, v[8:9], off
global_load_b32 v24, v[10:11], off
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
global_load_b32 v14, v[16:17], off
global_load_b32 v15, v[18:19], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(4)
v_add_f32_e32 v1, v20, v12
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v13, v20, v21
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v14, v20, v22
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v15, v20, v23
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v20, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v18, null, v1, v1, v0
v_rcp_f32_e32 v22, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v29, -v18, v22, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v22, v29, v22
v_div_scale_f32 v16, null, v1, v1, v14
v_div_scale_f32 v17, null, v1, v1, v15
v_div_scale_f32 v25, s1, v15, v1, v15
v_rcp_f32_e32 v20, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v21, v17
v_div_scale_f32 v24, s0, v14, v1, v14
s_waitcnt_depctr 0xfff
v_fma_f32 v27, -v16, v20, 1.0
v_fma_f32 v28, -v17, v21, 1.0
v_fmac_f32_e32 v20, v27, v20
v_div_scale_f32 v12, null, v1, v1, v13
v_div_scale_f32 v23, vcc_lo, v13, v1, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v19, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v12, v19, 1.0
v_fmac_f32_e32 v19, v26, v19
v_fmac_f32_e32 v21, v28, v21
v_div_scale_f32 v30, s2, v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v26, v23, v19
v_mul_f32_e32 v28, v25, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v31, -v12, v26, v23
v_mul_f32_e32 v27, v24, v20
v_fma_f32 v33, -v17, v28, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v29, v30, v22 :: v_dual_fmac_f32 v26, v31, v19
v_fma_f32 v32, -v16, v27, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v28, v33, v21
v_fma_f32 v34, -v18, v29, v30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v12, -v12, v26, v23
v_fmac_f32_e32 v27, v32, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v17, -v17, v28, v25
v_fmac_f32_e32 v29, v34, v22
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f32 v12, v12, v19, v26
v_fma_f32 v16, -v16, v27, v24
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v18, -v18, v29, v30
v_div_fixup_f32 v12, v12, v1, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f32 v16, v16, v20, v27
s_mov_b32 vcc_lo, s1
v_div_fmas_f32 v17, v17, v21, v28
s_mov_b32 vcc_lo, s2
v_div_fixup_f32 v13, v16, v1, v14
v_div_fmas_f32 v18, v18, v22, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v14, v17, v1, v15
v_div_fixup_f32 v0, v18, v1, v0
global_store_b32 v[2:3], v1, off
global_store_b32 v[4:5], v12, off
global_store_b32 v[6:7], v13, off
global_store_b32 v[8:9], v14, off
global_store_b32 v[10:11], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 88
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 88
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void HydroUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float dt, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
} | .text
.file "HydroUpdatePrim_CUDA3_kernel.hip"
.globl _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi # -- Begin function _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 4, 0x90
.type _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@function
_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi: # @_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@object # @_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .rodata,"a",@progbits
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 3, 0x0
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
.quad _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x1b4] ; /* 0x00006d0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x3, URZ ; /* 0xfffffffd04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R3, 0x40, R0 ; /* 0x0000004003007824 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R16, R5, 0xa000, R0 ; /* 0x0000a00005107824 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.AND P0, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc8000bf04270 */
/*0090*/ ISETP.LT.OR P0, PT, R16, 0x2, P0 ; /* 0x000000021000780c */
/* 0x000fda0000701670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R27, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1b7435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R8, R16, R27, c[0x0][0x188] ; /* 0x0000620010087625 */
/* 0x000fc800078e021b */
/*00e0*/ IMAD.WIDE R10, R16.reuse, R27.reuse, c[0x0][0x160] ; /* 0x00005800100a7625 */
/* 0x0c0fe200078e021b */
/*00f0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x0000a8000c1e1900 */
/*0100*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R22, R16, R27, c[0x0][0x190] ; /* 0x0000640010167625 */
/* 0x000fc800078e021b */
/*0120*/ IMAD.WIDE R2, R16.reuse, R27.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x0c0fe200078e021b */
/*0130*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ee6000c1e1900 */
/*0140*/ IMAD.WIDE R20, R16.reuse, R27.reuse, c[0x0][0x1a0] ; /* 0x0000680010147625 */
/* 0x0c0fe200078e021b */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ee6000c1e1900 */
/*0160*/ IMAD.WIDE R14, R16.reuse, R27.reuse, c[0x0][0x1a8] ; /* 0x00006a00100e7625 */
/* 0x0c0fe400078e021b */
/*0170*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000324000c1e1900 */
/*0180*/ IMAD.WIDE R24, R16, R27, c[0x0][0x198] ; /* 0x0000660010187625 */
/* 0x000fc400078e021b */
/*0190*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f64000c1e1900 */
/*01a0*/ IMAD.WIDE R4, R16.reuse, R27.reuse, c[0x0][0x170] ; /* 0x00005c0010047625 */
/* 0x0c0fe400078e021b */
/*01b0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x000324000c1e1900 */
/*01c0*/ IMAD.WIDE R6, R16.reuse, R27.reuse, c[0x0][0x178] ; /* 0x00005e0010067625 */
/* 0x0c0fe400078e021b */
/*01d0*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x000f24000c1e1900 */
/*01e0*/ IMAD.WIDE R8, R16, R27, c[0x0][0x180] ; /* 0x0000600010087625 */
/* 0x001fc400078e021b */
/*01f0*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000f62000c1e1900 */
/*0210*/ BSSY B0, 0x340 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0220*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fc80000000000 */
/*0230*/ MUFU.RCP R24, R13 ; /* 0x0000000d00187308 */
/* 0x002e220000001000 */
/*0240*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0003e2000c101904 */
/*0250*/ FFMA R22, R17, R0, R12 ; /* 0x0000000011167223 */
/* 0x008fcc000000000c */
/*0260*/ FCHK P0, R22, R13 ; /* 0x0000000d16007302 */
/* 0x000ea20000000000 */
/*0270*/ FFMA R23, -R13, R24, 1 ; /* 0x3f8000000d177423 */
/* 0x001fc80000000118 */
/*0280*/ FFMA R23, R24, R23, R24 ; /* 0x0000001718177223 */
/* 0x000fc80000000018 */
/*0290*/ FFMA R20, R22, R23, RZ ; /* 0x0000001716147223 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R17, -R13, R20, R22 ; /* 0x000000140d117223 */
/* 0x000fe40000000116 */
/*02b0*/ FFMA R12, R0.reuse, R26, R19 ; /* 0x0000001a000c7223 */
/* 0x050fe40000000013 */
/*02c0*/ FFMA R16, R0.reuse, R16, R21 ; /* 0x0000001000107223 */
/* 0x040fe40000000015 */
/*02d0*/ FFMA R17, R23, R17, R20 ; /* 0x0000001117117223 */
/* 0x000fe40000000014 */
/*02e0*/ FFMA R18, R0, R18, R15 ; /* 0x0000001200127223 */
/* 0x020fe2000000000f */
/*02f0*/ @!P0 BRA 0x330 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0300*/ MOV R0, 0x320 ; /* 0x0000032000007802 */
/* 0x002fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0x630 ; /* 0x0000031000007944 */
/* 0x000fea0003c00000 */
/*0320*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x001fe400078e000e */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0340*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0350*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e2000c101904 */
/*0360*/ BSSY B0, 0x430 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0370*/ FCHK P0, R12, R13 ; /* 0x0000000d0c007302 */
/* 0x000ea20000000000 */
/*0380*/ FFMA R11, -R13, R0, 1 ; /* 0x3f8000000d0b7423 */
/* 0x001fc80000000100 */
/*0390*/ FFMA R15, R0, R11, R0 ; /* 0x0000000b000f7223 */
/* 0x000fc80000000000 */
/*03a0*/ FFMA R0, R12, R15, RZ ; /* 0x0000000f0c007223 */
/* 0x000fc800000000ff */
/*03b0*/ FFMA R11, -R13, R0, R12 ; /* 0x000000000d0b7223 */
/* 0x000fc8000000010c */
/*03c0*/ FFMA R11, R15, R11, R0 ; /* 0x0000000b0f0b7223 */
/* 0x000fe20000000000 */
/*03d0*/ @!P0 BRA 0x420 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R22, RZ, RZ, R12 ; /* 0x000000ffff167224 */
/* 0x002fe200078e000c */
/*03f0*/ MOV R0, 0x410 ; /* 0x0000041000007802 */
/* 0x000fe40000000f00 */
/*0400*/ CALL.REL.NOINC 0x630 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0410*/ MOV R11, R14 ; /* 0x0000000e000b7202 */
/* 0x001fe40000000f00 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0430*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0440*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e2000c101904 */
/*0450*/ BSSY B0, 0x520 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0460*/ FCHK P0, R16, R13 ; /* 0x0000000d10007302 */
/* 0x000ea20000000000 */
/*0470*/ FFMA R3, -R13, R0, 1 ; /* 0x3f8000000d037423 */
/* 0x001fc80000000100 */
/*0480*/ FFMA R15, R0, R3, R0 ; /* 0x00000003000f7223 */
/* 0x000fc80000000000 */
/*0490*/ FFMA R0, R16, R15, RZ ; /* 0x0000000f10007223 */
/* 0x000fc800000000ff */
/*04a0*/ FFMA R3, -R13, R0, R16 ; /* 0x000000000d037223 */
/* 0x000fc80000000110 */
/*04b0*/ FFMA R3, R15, R3, R0 ; /* 0x000000030f037223 */
/* 0x000fe20000000000 */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R22, RZ, RZ, R16 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0010 */
/*04e0*/ MOV R0, 0x500 ; /* 0x0000050000007802 */
/* 0x000fe40000000f00 */
/*04f0*/ CALL.REL.NOINC 0x630 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x001fe400078e000e */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0520*/ MUFU.RCP R0, R13 ; /* 0x0000000d00007308 */
/* 0x000e220000001000 */
/*0530*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0003e2000c101904 */
/*0540*/ BSSY B0, 0x610 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0550*/ FCHK P0, R18, R13 ; /* 0x0000000d12007302 */
/* 0x000ea20000000000 */
/*0560*/ FFMA R5, -R13, R0, 1 ; /* 0x3f8000000d057423 */
/* 0x001fc80000000100 */
/*0570*/ FFMA R11, R0, R5, R0 ; /* 0x00000005000b7223 */
/* 0x000fc80000000000 */
/*0580*/ FFMA R0, R18, R11, RZ ; /* 0x0000000b12007223 */
/* 0x000fc800000000ff */
/*0590*/ FFMA R5, -R13, R0, R18 ; /* 0x000000000d057223 */
/* 0x000fc80000000112 */
/*05a0*/ FFMA R5, R11, R5, R0 ; /* 0x000000050b057223 */
/* 0x000fe20000000000 */
/*05b0*/ @!P0 BRA 0x600 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*05c0*/ MOV R22, R18 ; /* 0x0000001200167202 */
/* 0x002fe40000000f00 */
/*05d0*/ MOV R0, 0x5f0 ; /* 0x000005f000007802 */
/* 0x000fe40000000f00 */
/*05e0*/ CALL.REL.NOINC 0x630 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*05f0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000e */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0610*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x000fe2000c101904 */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ SHF.R.U32.HI R10, RZ, 0x17, R13 ; /* 0x00000017ff0a7819 */
/* 0x000fe2000001160d */
/*0640*/ BSSY B1, 0xc90 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0650*/ SHF.R.U32.HI R11, RZ, 0x17, R22.reuse ; /* 0x00000017ff0b7819 */
/* 0x100fe20000011616 */
/*0660*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0016 */
/*0670*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*0680*/ LOP3.LUT R17, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b117812 */
/* 0x000fc400078ec0ff */
/*0690*/ IADD3 R20, R10, -0x1, RZ ; /* 0xffffffff0a147810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R19, R17, -0x1, RZ ; /* 0xffffffff11137810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R20, 0xfd, PT ; /* 0x000000fd1400780c */
/* 0x000fe40003f04070 */
/*06c0*/ MOV R15, R13 ; /* 0x0000000d000f7202 */
/* 0x000fe40000000f00 */
/*06d0*/ ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ; /* 0x000000fd1300780c */
/* 0x000fda0000704470 */
/*06e0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*06f0*/ @!P0 BRA 0x870 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0700*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0710*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0730*/ @P0 BRA 0xc70 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT P0, RZ, R15, 0x7fffffff, R14, 0xc8, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fda000780c80e */
/*0750*/ @!P0 BRA 0xc50 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0760*/ FSETP.NEU.FTZ.AND P2, PT, |R22|.reuse, +INF , PT ; /* 0x7f8000001600780b */
/* 0x040fe40003f5d200 */
/*0770*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0790*/ @!P1 BRA !P2, 0xc50 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07a0*/ LOP3.LUT P2, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fc8000784c0ff */
/*07b0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07c0*/ @P1 BRA 0xc30 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT P1, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000782c0ff */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*07f0*/ @P0 BRA 0xc00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f06270 */
/*0810*/ ISETP.GE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fd60003f26270 */
/*0820*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e00ff */
/*0830*/ @!P0 MOV R11, 0xffffffc0 ; /* 0xffffffc0000b8802 */
/* 0x000fe20000000f00 */
/*0840*/ @!P0 FFMA R14, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f800000160e8823 */
/* 0x000fe400000000ff */
/*0850*/ @!P1 FFMA R15, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d0f9823 */
/* 0x000fe200000000ff */
/*0860*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0870*/ LEA R20, R10, 0xc0800000, 0x17 ; /* 0xc08000000a147811 */
/* 0x000fe200078eb8ff */
/*0880*/ BSSY B2, 0xbf0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0890*/ IADD3 R17, R17, -0x7f, RZ ; /* 0xffffff8111117810 */
/* 0x000fc60007ffe0ff */
/*08a0*/ IMAD.IADD R19, R15, 0x1, -R20 ; /* 0x000000010f137824 */
/* 0x000fe400078e0a14 */
/*08b0*/ IMAD R14, R17, -0x800000, R14 ; /* 0xff800000110e7824 */
/* 0x000fe400078e020e */
/*08c0*/ MUFU.RCP R15, R19 ; /* 0x00000013000f7308 */
/* 0x000e220000001000 */
/*08d0*/ FADD.FTZ R21, -R19, -RZ ; /* 0x800000ff13157221 */
/* 0x000fc80000010100 */
/*08e0*/ FFMA R20, R15, R21, 1 ; /* 0x3f8000000f147423 */
/* 0x001fc80000000015 */
/*08f0*/ FFMA R15, R15, R20, R15 ; /* 0x000000140f0f7223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R20, R14, R15, RZ ; /* 0x0000000f0e147223 */
/* 0x000fc800000000ff */
/*0910*/ FFMA R22, R21, R20, R14 ; /* 0x0000001415167223 */
/* 0x000fc8000000000e */
/*0920*/ FFMA R20, R15, R22, R20 ; /* 0x000000160f147223 */
/* 0x000fe20000000014 */
/*0930*/ IADD3 R22, R17, 0x7f, -R10 ; /* 0x0000007f11167810 */
/* 0x000fc60007ffe80a */
/*0940*/ FFMA R21, R21, R20, R14 ; /* 0x0000001415157223 */
/* 0x000fe4000000000e */
/*0950*/ IMAD.IADD R11, R22, 0x1, R11 ; /* 0x00000001160b7824 */
/* 0x000fe400078e020b */
/*0960*/ FFMA R14, R15, R21, R20 ; /* 0x000000150f0e7223 */
/* 0x000fca0000000014 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x17, R14 ; /* 0x00000017ff0a7819 */
/* 0x000fc8000001160e */
/*0980*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fc800078ec0ff */
/*0990*/ IADD3 R17, R10, R11, RZ ; /* 0x0000000b0a117210 */
/* 0x000fc80007ffe0ff */
/*09a0*/ IADD3 R10, R17, -0x1, RZ ; /* 0xffffffff110a7810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*09c0*/ @!P0 BRA 0xbd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*09e0*/ @P0 BRA 0xba0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0a00*/ @P0 BRA 0xbe0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0a20*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000e0e7812 */
/* 0x000fd600078ec0ff */
/*0a30*/ @!P0 BRA 0xbe0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a40*/ FFMA.RZ R10, R15, R21.reuse, R20.reuse ; /* 0x000000150f0a7223 */
/* 0x180fe2000000c014 */
/*0a50*/ ISETP.NE.AND P2, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f45270 */
/*0a60*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0a70*/ LOP3.LUT R11, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0b7812 */
/* 0x000fe200078ec0ff */
/*0a80*/ FFMA.RP R10, R15.reuse, R21.reuse, R20.reuse ; /* 0x000000150f0a7223 */
/* 0x1c0fe40000008014 */
/*0a90*/ FFMA.RM R15, R15, R21, R20 ; /* 0x000000150f0f7223 */
/* 0x000fe20000004014 */
/*0aa0*/ IADD3 R20, R17, 0x20, RZ ; /* 0x0000002011147810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0a11 */
/*0ac0*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fc400078efcff */
/*0ad0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720b */
/* 0x000fe40003f1d000 */
/*0ae0*/ SHF.L.U32 R20, R11, R20, RZ ; /* 0x000000140b147219 */
/* 0x000fe400000006ff */
/*0af0*/ SEL R10, R17, RZ, P2 ; /* 0x000000ff110a7207 */
/* 0x000fe40001000000 */
/*0b00*/ ISETP.NE.AND P1, PT, R20, RZ, P1 ; /* 0x000000ff1400720c */
/* 0x000fe40000f25270 */
/*0b10*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0b30*/ SHF.R.U32.HI R20, RZ, 0x1, R10 ; /* 0x00000001ff147819 */
/* 0x000fe4000001160a */
/*0b40*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0b50*/ LOP3.LUT R11, R11, 0x1, R20, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef814 */
/*0b60*/ LOP3.LUT R11, R11, R10, RZ, 0xc0, !PT ; /* 0x0000000a0b0b7212 */
/* 0x000fca00078ec0ff */
/*0b70*/ IMAD.IADD R11, R20, 0x1, R11 ; /* 0x00000001140b7824 */
/* 0x000fca00078e020b */
/*0b80*/ LOP3.LUT R14, R11, R14, RZ, 0xfc, !PT ; /* 0x0000000e0b0e7212 */
/* 0x000fe200078efcff */
/*0b90*/ BRA 0xbe0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ba0*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000e0e7812 */
/* 0x000fc800078ec0ff */
/*0bb0*/ LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000e0e7812 */
/* 0x000fe200078efcff */
/*0bc0*/ BRA 0xbe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LEA R14, R11, R14, 0x17 ; /* 0x0000000e0b0e7211 */
/* 0x000fe400078eb8ff */
/*0be0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xc80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c00*/ LOP3.LUT R14, R15, 0x80000000, R14, 0x48, !PT ; /* 0x800000000f0e7812 */
/* 0x000fc800078e480e */
/*0c10*/ LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000e0e7812 */
/* 0x000fe200078efcff */
/*0c20*/ BRA 0xc80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c30*/ LOP3.LUT R14, R15, 0x80000000, R14, 0x48, !PT ; /* 0x800000000f0e7812 */
/* 0x000fe200078e480e */
/*0c40*/ BRA 0xc80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c50*/ MUFU.RSQ R14, -QNAN ; /* 0xffc00000000e7908 */
/* 0x000e220000001400 */
/*0c60*/ BRA 0xc80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c70*/ FADD.FTZ R14, R22, R13 ; /* 0x0000000d160e7221 */
/* 0x000fe40000010000 */
/*0c80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c90*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0ca0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0000 */
/*0cb0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff3400a007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 8
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@function
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
s_load_b32 s2, s[0:1], 0x54
s_lshl_b32 s3, s14, 6
s_mul_i32 s15, s15, 0xa000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
v_cmp_lt_i32_e32 vcc_lo, 1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x20
s_load_b128 s[0:3], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s15, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v16, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v17, vcc_lo, s19, v1, vcc_lo
v_add_co_u32 v18, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v20, v[2:3], off
global_load_b32 v21, v[4:5], off
global_load_b32 v22, v[6:7], off
global_load_b32 v23, v[8:9], off
global_load_b32 v24, v[10:11], off
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
global_load_b32 v14, v[16:17], off
global_load_b32 v15, v[18:19], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(4)
v_add_f32_e32 v1, v20, v12
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v13, v20, v21
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v14, v20, v22
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v15, v20, v23
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v20, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v18, null, v1, v1, v0
v_rcp_f32_e32 v22, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v29, -v18, v22, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v22, v29, v22
v_div_scale_f32 v16, null, v1, v1, v14
v_div_scale_f32 v17, null, v1, v1, v15
v_div_scale_f32 v25, s1, v15, v1, v15
v_rcp_f32_e32 v20, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v21, v17
v_div_scale_f32 v24, s0, v14, v1, v14
s_waitcnt_depctr 0xfff
v_fma_f32 v27, -v16, v20, 1.0
v_fma_f32 v28, -v17, v21, 1.0
v_fmac_f32_e32 v20, v27, v20
v_div_scale_f32 v12, null, v1, v1, v13
v_div_scale_f32 v23, vcc_lo, v13, v1, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v19, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v12, v19, 1.0
v_fmac_f32_e32 v19, v26, v19
v_fmac_f32_e32 v21, v28, v21
v_div_scale_f32 v30, s2, v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v26, v23, v19
v_mul_f32_e32 v28, v25, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v31, -v12, v26, v23
v_mul_f32_e32 v27, v24, v20
v_fma_f32 v33, -v17, v28, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v29, v30, v22 :: v_dual_fmac_f32 v26, v31, v19
v_fma_f32 v32, -v16, v27, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v28, v33, v21
v_fma_f32 v34, -v18, v29, v30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v12, -v12, v26, v23
v_fmac_f32_e32 v27, v32, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v17, -v17, v28, v25
v_fmac_f32_e32 v29, v34, v22
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f32 v12, v12, v19, v26
v_fma_f32 v16, -v16, v27, v24
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v18, -v18, v29, v30
v_div_fixup_f32 v12, v12, v1, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f32 v16, v16, v20, v27
s_mov_b32 vcc_lo, s1
v_div_fmas_f32 v17, v17, v21, v28
s_mov_b32 vcc_lo, s2
v_div_fixup_f32 v13, v16, v1, v14
v_div_fmas_f32 v18, v18, v22, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v14, v17, v1, v15
v_div_fixup_f32 v0, v18, v1, v0
global_store_b32 v[2:3], v1, off
global_store_b32 v[4:5], v12, off
global_store_b32 v[6:7], v13, off
global_store_b32 v[8:9], v14, off
global_store_b32 v[10:11], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 88
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 88
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d06f9_00000000-6_HydroUpdatePrim_CUDA3_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
.type _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi, @function
_Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movss %xmm0, 12(%rsp)
movq 288(%rsp), %rax
movq %rax, 40(%rsp)
movq 296(%rsp), %rax
movq %rax, 32(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 12(%rsp), %rax
movq %rax, 240(%rsp)
leaq 320(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi, .-_Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, @function
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z68__device_stub__Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_S_fi
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .-_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HydroUpdatePrim_CUDA3_kernel.hip"
.globl _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi # -- Begin function _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 4, 0x90
.type _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@function
_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi: # @_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi,@object # @_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.section .rodata,"a",@progbits
.globl _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.p2align 3, 0x0
_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi:
.quad _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.size _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28HydroUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} | code for sm_80
Function : _Z12Find3DMinMaxPiPfS0_S0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x7e ; /* 0x0000007eff027424 */
/* 0x000fe200078e00ff */
/*0030*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0040*/ IMAD.MOV.U32 R18, RZ, RZ, -0x1 ; /* 0xffffffffff127424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0060*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0080*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*0090*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002600 */
/*00a0*/ ULDC UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00c0*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc6000fffe13f */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD R13, R3.reuse, R2, 0x7d ; /* 0x0000007d030d7424 */
/* 0x041fe400078e0202 */
/*00f0*/ IMAD R10, R3, 0x7e, R8 ; /* 0x0000007e030a7824 */
/* 0x002fe200078e0208 */
/*0100*/ IADD3 R12, R8, -0xf, RZ ; /* 0xfffffff1080c7810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IMNMX R13, R13, UR4, PT ; /* 0x000000040d0d7c17 */
/* 0x000fe4000b800200 */
/*0120*/ LEA R19, R9, 0xffffffff, 0x5 ; /* 0xffffffff09137811 */
/* 0x004fe200078e28ff */
/*0130*/ IMAD.MOV.U32 R17, RZ, RZ, R12 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000c */
/*0140*/ IADD3 R14, R10, -0x10, RZ ; /* 0xfffffff00a0e7810 */
/* 0x000fc40007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R8, 0xf, PT ; /* 0x0000000f0800780c */
/* 0x000fe20003f06270 */
/*0160*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000c */
/*0170*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD R12, R11, 0x80, R8 ; /* 0x000000800b0c7824 */
/* 0x000fe200078e0208 */
/*0190*/ BSSY B0, 0x370 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*01a0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc40000011600 */
/*01b0*/ ISETP.NE.AND P2, PT, R18, 0x21, PT ; /* 0x000000211200780c */
/* 0x000fe20003f45270 */
/*01c0*/ IMAD.SHL.U32 R16, R12, 0x4, RZ ; /* 0x000000040c107824 */
/* 0x003fca00078e00ff */
/*01d0*/ @!P0 BRA 0x360 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R10, 0x10, PT ; /* 0x000000100a00780c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x330 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; /* 0x000060000e007a0c */
/* 0x000fda0003f06270 */
/*0210*/ @P0 STS [R16+-0x3c], RZ ; /* 0xffffc4ff10000388 */
/* 0x0001e80000000800 */
/*0220*/ @P0 STS [R16+0x5c4], RZ ; /* 0x0005c4ff10000388 */
/* 0x0001e80000000800 */
/*0230*/ @P0 STS [R16+0xbc4], RZ ; /* 0x000bc4ff10000388 */
/* 0x0001e20000000800 */
/*0240*/ @P0 BRA 0x360 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0250*/ IMNMX R2, RZ, R19, !PT ; /* 0x00000013ff027217 */
/* 0x000fe20007800200 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0270*/ IMNMX R3, R2, UR5, PT ; /* 0x0000000502037c17 */
/* 0x000fca000b800200 */
/*0280*/ IMAD R6, R3, c[0x0][0x184], R14 ; /* 0x0000610003067a24 */
/* 0x000fc800078e020e */
/*0290*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*02a0*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*02b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*02d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee8000c1e1900 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000f28000c1e1900 */
/*02f0*/ STS [R16+-0x3c], R3 ; /* 0xffffc40310007388 */
/* 0x0043e80000000800 */
/*0300*/ STS [R16+0x5c4], R5 ; /* 0x0005c40510007388 */
/* 0x0083e80000000800 */
/*0310*/ STS [R16+0xbc4], R7 ; /* 0x000bc40710007388 */
/* 0x0103e20000000800 */
/*0320*/ BRA 0x360 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0330*/ STS [R16+-0x3c], RZ ; /* 0xffffc4ff10007388 */
/* 0x0001e80000000800 */
/*0340*/ STS [R16+0x5c4], RZ ; /* 0x0005c4ff10007388 */
/* 0x0001e80000000800 */
/*0350*/ STS [R16+0xbc4], RZ ; /* 0x000bc4ff10007388 */
/* 0x0001e40000000800 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fc80003f26070 */
/*0390*/ ISETP.GT.OR P0, PT, R8, 0x7f, !P1 ; /* 0x0000007f0800780c */
/* 0x000fe20004f04670 */
/*03a0*/ BSSY B0, 0x5c0 ; /* 0x0000021000007945 */
/* 0x000fd80003800000 */
/*03b0*/ @P0 BRA 0x5b0 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LDS R4, [R15.X4] ; /* 0x000000000f047984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R5, [R17.X4] ; /* 0x0000000011057984 */
/* 0x002e680000004800 */
/*03e0*/ LDS R7, [R16] ; /* 0x0000000010077984 */
/* 0x000ea80000000800 */
/*03f0*/ LDS R20, [R15.X4+0x600] ; /* 0x000600000f147984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000ee80000004800 */
/*0410*/ LDS R22, [R15.X4+0xc00] ; /* 0x000c00000f167984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R23, [R17.X4+0xc00] ; /* 0x000c000011177984 */
/* 0x000f280000004800 */
/*0430*/ LDS R3, [R16+0x600] ; /* 0x0006000010037984 */
/* 0x000f680000000800 */
/*0440*/ LDS R2, [R16+0xc00] ; /* 0x000c000010027984 */
/* 0x000e220000000800 */
/*0450*/ FMNMX R6, R4, R5, PT ; /* 0x0000000504067209 */
/* 0x002fc40003800000 */
/*0460*/ FMNMX R4, R4, R5, !PT ; /* 0x0000000504047209 */
/* 0x000fe40007800000 */
/*0470*/ FMNMX R5, R6, R7, PT ; /* 0x0000000706057209 */
/* 0x004fe40003800000 */
/*0480*/ FMNMX R7, R7, R4, !PT ; /* 0x0000000407077209 */
/* 0x000fc60007800000 */
/*0490*/ STS [R8.X4+0x1200], R5 ; /* 0x0012000508007388 */
/* 0x0003e20000004800 */
/*04a0*/ FMNMX R4, R20, R21, PT ; /* 0x0000001514047209 */
/* 0x008fc60003800000 */
/*04b0*/ STS [R8.X4+0x1800], R7 ; /* 0x0018000708007388 */
/* 0x0003e20000004800 */
/*04c0*/ FMNMX R20, R20, R21, !PT ; /* 0x0000001514147209 */
/* 0x000fe40007800000 */
/*04d0*/ FMNMX R21, R22.reuse, R23.reuse, PT ; /* 0x0000001716157209 */
/* 0x0d0fe40003800000 */
/*04e0*/ FMNMX R23, R22, R23, !PT ; /* 0x0000001716177209 */
/* 0x000fe40007800000 */
/*04f0*/ FMNMX R4, R4, R3, PT ; /* 0x0000000304047209 */
/* 0x020fe40003800000 */
/*0500*/ FMNMX R20, R3, R20, !PT ; /* 0x0000001403147209 */
/* 0x000fe40007800000 */
/*0510*/ FMNMX R21, R21, R2, PT ; /* 0x0000000215157209 */
/* 0x001fc40003800000 */
/*0520*/ FMNMX R23, R2, R23, !PT ; /* 0x0000001702177209 */
/* 0x000fe40007800000 */
/*0530*/ FMNMX R4, R5, R4, PT ; /* 0x0000000405047209 */
/* 0x000fe20003800000 */
/*0540*/ STS [R8.X4+0x1600], R21 ; /* 0x0016001508007388 */
/* 0x0003e20000004800 */
/*0550*/ FMNMX R20, R7, R20, !PT ; /* 0x0000001407147209 */
/* 0x000fe40007800000 */
/*0560*/ FMNMX R3, R21, R4, PT ; /* 0x0000000415037209 */
/* 0x000fe20003800000 */
/*0570*/ STS [R8.X4+0x1c00], R23 ; /* 0x001c001708007388 */
/* 0x0003e20000004800 */
/*0580*/ FMNMX R25, R23, R20, !PT ; /* 0x0000001417197209 */
/* 0x000fc60007800000 */
/*0590*/ STS [R8.X4+0x1400], R3 ; /* 0x0014000308007388 */
/* 0x0003e80000004800 */
/*05a0*/ STS [R8.X4+0x1a00], R25 ; /* 0x001a001908007388 */
/* 0x0003e40000004800 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ ISETP.GT.OR P1, PT, R8.reuse, 0x7d, !P1 ; /* 0x0000007d0800780c */
/* 0x040fe40004f24670 */
/*05e0*/ ISETP.GT.AND P0, PT, R8, 0x7d, PT ; /* 0x0000007d0800780c */
/* 0x000fe40003f04270 */
/*05f0*/ ISETP.GT.OR P1, PT, R10, R13, P1 ; /* 0x0000000d0a00720c */
/* 0x000fe20000f24670 */
/*0600*/ BSSY B0, 0x7d0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0610*/ @P1 BRA 0x7c0 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0620*/ LDS R6, [R8.X4+0x1a08] ; /* 0x001a080008067984 */
/* 0x000fe80000004800 */
/*0630*/ LDS R23, [R8.X4+0x1a00] ; /* 0x001a000008177984 */
/* 0x002e680000004800 */
/*0640*/ LDS R4, [R8.X4+0x1400] ; /* 0x0014000008047984 */
/* 0x000fe80000004800 */
/*0650*/ LDS R5, [R8.X4+0x1408] ; /* 0x0014080008057984 */
/* 0x000ea80000004800 */
/*0660*/ LDS R25, [R8.X4+0x1804] ; /* 0x0018040008197984 */
/* 0x000ee80000004800 */
/*0670*/ LDS R7, [R8.X4+0x1204] ; /* 0x0012040008077984 */
/* 0x000f280000004800 */
/*0680*/ LDS R27, [R8.X4+0x1c04] ; /* 0x001c0400081b7984 */
/* 0x000f680000004800 */
/*0690*/ LDS R21, [R8.X4+0x1604] ; /* 0x0016040008157984 */
/* 0x000e280000004800 */
/*06a0*/ LDS R3, [R17.X4+0x604] ; /* 0x0006040011037984 */
/* 0x000e280000004800 */
/*06b0*/ LDS R16, [R16+0x604] ; /* 0x0006040010107984 */
/* 0x001e280000000800 */
/*06c0*/ LDS R2, [R15.X4+0x604] ; /* 0x000604000f027984 */
/* 0x000e220000004800 */
/*06d0*/ FMNMX R6, R6, R23, !PT ; /* 0x0000001706067209 */
/* 0x002fc40007800000 */
/*06e0*/ FMNMX R4, R4, R5, PT ; /* 0x0000000504047209 */
/* 0x004fe40003800000 */
/*06f0*/ FMNMX R6, R6, R25, !PT ; /* 0x0000001906067209 */
/* 0x008fe40007800000 */
/*0700*/ FMNMX R4, R4, R7, PT ; /* 0x0000000704047209 */
/* 0x010fe40003800000 */
/*0710*/ FMNMX R6, R6, R27, !PT ; /* 0x0000001b06067209 */
/* 0x020fe40007800000 */
/*0720*/ FMNMX R4, R4, R21, PT ; /* 0x0000001504047209 */
/* 0x000fe40003800000 */
/*0730*/ FMNMX R5, R3, R6, !PT ; /* 0x0000000603057209 */
/* 0x000fc40007800000 */
/*0740*/ FMNMX R3, R4, R3, PT ; /* 0x0000000304037209 */
/* 0x000fe40003800000 */
/*0750*/ FMNMX R5, R16, R5, !PT ; /* 0x0000000510057209 */
/* 0x001fe40007800000 */
/*0760*/ FMNMX R3, R3, R16, PT ; /* 0x0000001003037209 */
/* 0x000fe40003800000 */
/*0770*/ FMNMX R5, R5, c[0x3][0x0], !PT ; /* 0x00c0000005057a09 */
/* 0x000fe40007800000 */
/*0780*/ FMNMX R3, R3, c[0x3][0x4], PT ; /* 0x00c0010003037a09 */
/* 0x000fe40003800000 */
/*0790*/ FSETP.GT.AND P1, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x000fc80003f24000 */
/*07a0*/ FSETP.LT.OR P1, PT, R2, R3, P1 ; /* 0x000000030200720b */
/* 0x000fda0000f21400 */
/*07b0*/ @P1 LOP3.LUT R0, R0, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000000001812 */
/* 0x000fe400078efcff */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07e0*/ ISETP.GE.AND P1, PT, R11.reuse, 0x2, PT ; /* 0x000000020b00780c */
/* 0x040fe20003f26270 */
/*07f0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0800*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0820*/ SEL R11, R11, RZ, !P1 ; /* 0x000000ff0b0b7207 */
/* 0x000fe20004800000 */
/*0830*/ @P2 BRA 0x150 ; /* 0xfffff91000002947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x180], P0 ; /* 0x000060000a007a0c */
/* 0x000fda0000706670 */
/*0850*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe400078e00ff */
/*0870*/ IMAD R2, R9, c[0x0][0x184], R10 ; /* 0x0000610009027a24 */
/* 0x000fc800078e020a */
/*0880*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0890*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101906 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} | .file "tmpxft_000a954b_00000000-6_Find3DMinMax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
.type _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, @function
_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, .-_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.type _Z12Find3DMinMaxPiPfS0_S0_iii, @function
_Z12Find3DMinMaxPiPfS0_S0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12Find3DMinMaxPiPfS0_S0_iii, .-_Z12Find3DMinMaxPiPfS0_S0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12Find3DMinMaxPiPfS0_S0_iii"
.LC1:
.string "d_Threshold"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11d_Threshold(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11d_Threshold
.comm _ZL11d_Threshold,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Find3DMinMaxPiPfS0_S0_iii
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.p2align 8
.type _Z12Find3DMinMaxPiPfS0_S0_iii,@function
_Z12Find3DMinMaxPiPfS0_S0_iii:
s_clause 0x1
s_load_b256 s[16:23], s[0:1], 0x8
s_load_b32 s11, s[0:1], 0x28
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_Threshold@rel32@lo+8
s_addc_u32 s5, s5, d_Threshold@rel32@hi+16
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_Threshold@rel32@lo+4
s_addc_u32 s7, s7, d_Threshold@rel32@hi+12
s_clause 0x1
s_load_b32 s9, s[4:5], 0x0
s_load_b32 s10, s[6:7], 0x0
s_mul_i32 s2, s14, 0x7e
v_dual_mov_b32 v17, 0 :: v_dual_lshlrev_b32 v4, 2, v0
v_add_nc_u32_e32 v1, s2, v0
v_add_nc_u32_e32 v3, -15, v0
s_add_i32 s8, s2, 0x7d
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 0x1800, v4
v_add_nc_u32_e32 v6, 0x1a00, v4
v_dual_mov_b32 v18, v3 :: v_dual_add_nc_u32 v7, 0x1c00, v4
v_add_nc_u32_e32 v8, 0x1200, v4
v_add_nc_u32_e32 v9, 0x1400, v4
v_add_nc_u32_e32 v10, 0x1600, v4
v_add_nc_u32_e32 v11, 0x1a08, v4
v_add_nc_u32_e32 v12, 0x1804, v4
v_add_nc_u32_e32 v13, 0x1c04, v4
v_add_nc_u32_e32 v14, 0x1408, v4
v_add_nc_u32_e32 v15, 0x1204, v4
v_add_nc_u32_e32 v16, 0x1604, v4
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v19, v3 :: v_dual_add_nc_u32 v2, -16, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s22, -1
v_cmp_lt_u32_e32 vcc_lo, 14, v0
s_min_i32 s6, s8, s5
v_cmp_gt_u32_e64 s2, 0x80, v0
v_cmp_gt_u32_e64 s3, 0x7e, v0
v_cmp_lt_i32_e64 s4, 15, v1
v_cmp_le_i32_e64 s5, s22, v2
v_cmp_ge_i32_e64 s6, s6, v1
s_lshl_b32 s12, s15, 5
s_add_i32 s11, s11, -1
s_add_i32 s12, s12, -1
s_mov_b32 s13, 0
s_mov_b32 s14, 0
.LBB0_1:
s_lshl_b32 s8, s13, 7
s_and_saveexec_b32 s24, vcc_lo
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v20, s8, v3
s_and_saveexec_b32 s7, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s25, exec_lo, s7
s_cbranch_execz .LBB0_8
s_and_saveexec_b32 s26, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB0_5
v_lshlrev_b32_e32 v21, 2, v20
s_mov_b32 s7, 0
ds_store_2addr_stride64_b32 v21, v17, v17 offset1:6
.LBB0_5:
s_or_saveexec_b32 s26, s26
v_mov_b32_e32 v21, s7
s_xor_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_7
s_add_i32 s7, s12, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_max_i32 s7, s7, 0
s_min_i32 s7, s7, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[21:22], null, s7, s23, v[2:3]
v_ashrrev_i32_e32 v22, 31, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[21:22], 2, v[21:22]
v_add_co_u32 v23, s7, s16, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v24, s7, s17, v22, s7
v_add_co_u32 v25, s7, s18, v21
v_add_co_ci_u32_e64 v26, s7, s19, v22, s7
v_add_co_u32 v21, s7, s20, v21
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s7, s21, v22, s7
global_load_b32 v23, v[23:24], off
global_load_b32 v24, v[25:26], off
global_load_b32 v21, v[21:22], off
v_lshlrev_b32_e32 v22, 2, v20
s_waitcnt vmcnt(1)
ds_store_2addr_stride64_b32 v22, v23, v24 offset1:6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s26
.LBB0_8:
s_or_saveexec_b32 s7, s25
v_lshlrev_b32_e32 v20, 2, v20
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_10
s_waitcnt vmcnt(0)
v_mov_b32_e32 v21, 0
ds_store_2addr_stride64_b32 v20, v17, v17 offset1:6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
ds_store_b32 v20, v21 offset:3072
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s24
v_add_nc_u32_e32 v20, s8, v0
s_cmp_gt_u32 s14, 1
v_lshlrev_b32_e32 v21, 2, v19
v_lshlrev_b32_e32 v19, 2, v18
s_cselect_b32 s7, -1, 0
v_lshlrev_b32_e32 v22, 2, v20
s_and_b32 s24, s2, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s8, s24
s_cbranch_execz .LBB0_13
ds_load_2addr_stride64_b32 v[23:24], v21 offset1:6
ds_load_2addr_stride64_b32 v[25:26], v19 offset1:6
ds_load_2addr_stride64_b32 v[27:28], v22 offset1:6
ds_load_b32 v29, v21 offset:3072
ds_load_b32 v30, v19 offset:3072
ds_load_b32 v31, v22 offset:3072
s_waitcnt lgkmcnt(3)
v_min3_f32 v32, v23, v25, v27
v_min3_f32 v33, v24, v26, v28
v_max3_f32 v23, v23, v25, v27
s_waitcnt lgkmcnt(0)
v_min3_f32 v34, v29, v30, v31
v_max3_f32 v24, v24, v26, v28
v_max3_f32 v25, v29, v30, v31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v26, v32, v33, v34
v_max3_f32 v24, v23, v24, v25
ds_store_b32 v5, v32
ds_store_b32 v6, v26
ds_store_b32 v7, v34
ds_store_b32 v8, v23
ds_store_b32 v9, v24
ds_store_b32 v10, v25
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
v_lshrrev_b32_e32 v4, 1, v4
s_and_b32 s7, s3, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s7, s6
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s24, s7
s_cbranch_execz .LBB0_15
ds_load_b32 v23, v6
ds_load_b32 v24, v12
ds_load_b32 v25, v13
ds_load_b32 v26, v14
ds_load_b32 v27, v15
ds_load_b32 v28, v16
ds_load_b32 v29, v11
ds_load_b32 v30, v9
ds_load_b32 v21, v21 offset:1540
ds_load_b32 v22, v22 offset:1540
ds_load_b32 v19, v19 offset:1540
s_waitcnt lgkmcnt(4)
v_min3_f32 v23, v23, v29, v24
s_waitcnt lgkmcnt(3)
v_max3_f32 v24, v30, v26, v27
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v23, v23, v25, v21
v_max3_f32 v21, v24, v28, v21
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v23, v23, v22, s9
v_max3_f32 v21, v21, v22, s10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s7, v19, v23
v_cmp_gt_f32_e64 s8, v19, v21
v_or_b32_e32 v19, 0x80000000, v4
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s7, s7, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v4, v4, v19, s7
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s24
s_add_i32 s7, s13, 1
s_cmp_lt_i32 s13, 2
s_cselect_b32 s13, s7, 0
s_add_i32 s14, s14, 1
s_barrier
s_cmp_eq_u32 s14, 34
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
v_dual_mov_b32 v19, v18 :: v_dual_mov_b32 v18, v20
s_branch .LBB0_1
.LBB0_17:
v_cmp_gt_u32_e32 vcc_lo, 0x7e, v0
v_cmp_gt_i32_e64 s2, s22, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s23, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Find3DMinMaxPiPfS0_S0_iii
.amdhsa_group_segment_fixed_size 7680
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z12Find3DMinMaxPiPfS0_S0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_Threshold
.type d_Threshold,@object
.section .bss,"aw",@nobits
.globl d_Threshold
.p2align 2, 0x0
d_Threshold:
.zero 8
.size d_Threshold, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_Threshold
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 7680
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Find3DMinMaxPiPfS0_S0_iii
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z12Find3DMinMaxPiPfS0_S0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];
// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;
int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {
output >>= 1;
int memPos = yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;
// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();
int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();
if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();
memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
} | .text
.file "Find3DMinMax.hip"
.globl _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii # -- Begin function _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.p2align 4, 0x90
.type _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii,@function
_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii: # @_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12Find3DMinMaxPiPfS0_S0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Find3DMinMaxPiPfS0_S0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_Threshold, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_Threshold,@object # @d_Threshold
.local d_Threshold
.comm d_Threshold,8,4
.type _Z12Find3DMinMaxPiPfS0_S0_iii,@object # @_Z12Find3DMinMaxPiPfS0_S0_iii
.section .rodata,"a",@progbits
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.p2align 3, 0x0
_Z12Find3DMinMaxPiPfS0_S0_iii:
.quad _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.size _Z12Find3DMinMaxPiPfS0_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12Find3DMinMaxPiPfS0_S0_iii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_Threshold"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_Threshold
.addrsig_sym _Z12Find3DMinMaxPiPfS0_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12Find3DMinMaxPiPfS0_S0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x7e ; /* 0x0000007eff027424 */
/* 0x000fe200078e00ff */
/*0030*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0040*/ IMAD.MOV.U32 R18, RZ, RZ, -0x1 ; /* 0xffffffffff127424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0060*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0080*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*0090*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002600 */
/*00a0*/ ULDC UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00c0*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc6000fffe13f */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD R13, R3.reuse, R2, 0x7d ; /* 0x0000007d030d7424 */
/* 0x041fe400078e0202 */
/*00f0*/ IMAD R10, R3, 0x7e, R8 ; /* 0x0000007e030a7824 */
/* 0x002fe200078e0208 */
/*0100*/ IADD3 R12, R8, -0xf, RZ ; /* 0xfffffff1080c7810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IMNMX R13, R13, UR4, PT ; /* 0x000000040d0d7c17 */
/* 0x000fe4000b800200 */
/*0120*/ LEA R19, R9, 0xffffffff, 0x5 ; /* 0xffffffff09137811 */
/* 0x004fe200078e28ff */
/*0130*/ IMAD.MOV.U32 R17, RZ, RZ, R12 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000c */
/*0140*/ IADD3 R14, R10, -0x10, RZ ; /* 0xfffffff00a0e7810 */
/* 0x000fc40007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R8, 0xf, PT ; /* 0x0000000f0800780c */
/* 0x000fe20003f06270 */
/*0160*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000c */
/*0170*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD R12, R11, 0x80, R8 ; /* 0x000000800b0c7824 */
/* 0x000fe200078e0208 */
/*0190*/ BSSY B0, 0x370 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*01a0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc40000011600 */
/*01b0*/ ISETP.NE.AND P2, PT, R18, 0x21, PT ; /* 0x000000211200780c */
/* 0x000fe20003f45270 */
/*01c0*/ IMAD.SHL.U32 R16, R12, 0x4, RZ ; /* 0x000000040c107824 */
/* 0x003fca00078e00ff */
/*01d0*/ @!P0 BRA 0x360 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R10, 0x10, PT ; /* 0x000000100a00780c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x330 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; /* 0x000060000e007a0c */
/* 0x000fda0003f06270 */
/*0210*/ @P0 STS [R16+-0x3c], RZ ; /* 0xffffc4ff10000388 */
/* 0x0001e80000000800 */
/*0220*/ @P0 STS [R16+0x5c4], RZ ; /* 0x0005c4ff10000388 */
/* 0x0001e80000000800 */
/*0230*/ @P0 STS [R16+0xbc4], RZ ; /* 0x000bc4ff10000388 */
/* 0x0001e20000000800 */
/*0240*/ @P0 BRA 0x360 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0250*/ IMNMX R2, RZ, R19, !PT ; /* 0x00000013ff027217 */
/* 0x000fe20007800200 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0270*/ IMNMX R3, R2, UR5, PT ; /* 0x0000000502037c17 */
/* 0x000fca000b800200 */
/*0280*/ IMAD R6, R3, c[0x0][0x184], R14 ; /* 0x0000610003067a24 */
/* 0x000fc800078e020e */
/*0290*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*02a0*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*02b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*02d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee8000c1e1900 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000f28000c1e1900 */
/*02f0*/ STS [R16+-0x3c], R3 ; /* 0xffffc40310007388 */
/* 0x0043e80000000800 */
/*0300*/ STS [R16+0x5c4], R5 ; /* 0x0005c40510007388 */
/* 0x0083e80000000800 */
/*0310*/ STS [R16+0xbc4], R7 ; /* 0x000bc40710007388 */
/* 0x0103e20000000800 */
/*0320*/ BRA 0x360 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0330*/ STS [R16+-0x3c], RZ ; /* 0xffffc4ff10007388 */
/* 0x0001e80000000800 */
/*0340*/ STS [R16+0x5c4], RZ ; /* 0x0005c4ff10007388 */
/* 0x0001e80000000800 */
/*0350*/ STS [R16+0xbc4], RZ ; /* 0x000bc4ff10007388 */
/* 0x0001e40000000800 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fc80003f26070 */
/*0390*/ ISETP.GT.OR P0, PT, R8, 0x7f, !P1 ; /* 0x0000007f0800780c */
/* 0x000fe20004f04670 */
/*03a0*/ BSSY B0, 0x5c0 ; /* 0x0000021000007945 */
/* 0x000fd80003800000 */
/*03b0*/ @P0 BRA 0x5b0 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LDS R4, [R15.X4] ; /* 0x000000000f047984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R5, [R17.X4] ; /* 0x0000000011057984 */
/* 0x002e680000004800 */
/*03e0*/ LDS R7, [R16] ; /* 0x0000000010077984 */
/* 0x000ea80000000800 */
/*03f0*/ LDS R20, [R15.X4+0x600] ; /* 0x000600000f147984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000ee80000004800 */
/*0410*/ LDS R22, [R15.X4+0xc00] ; /* 0x000c00000f167984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R23, [R17.X4+0xc00] ; /* 0x000c000011177984 */
/* 0x000f280000004800 */
/*0430*/ LDS R3, [R16+0x600] ; /* 0x0006000010037984 */
/* 0x000f680000000800 */
/*0440*/ LDS R2, [R16+0xc00] ; /* 0x000c000010027984 */
/* 0x000e220000000800 */
/*0450*/ FMNMX R6, R4, R5, PT ; /* 0x0000000504067209 */
/* 0x002fc40003800000 */
/*0460*/ FMNMX R4, R4, R5, !PT ; /* 0x0000000504047209 */
/* 0x000fe40007800000 */
/*0470*/ FMNMX R5, R6, R7, PT ; /* 0x0000000706057209 */
/* 0x004fe40003800000 */
/*0480*/ FMNMX R7, R7, R4, !PT ; /* 0x0000000407077209 */
/* 0x000fc60007800000 */
/*0490*/ STS [R8.X4+0x1200], R5 ; /* 0x0012000508007388 */
/* 0x0003e20000004800 */
/*04a0*/ FMNMX R4, R20, R21, PT ; /* 0x0000001514047209 */
/* 0x008fc60003800000 */
/*04b0*/ STS [R8.X4+0x1800], R7 ; /* 0x0018000708007388 */
/* 0x0003e20000004800 */
/*04c0*/ FMNMX R20, R20, R21, !PT ; /* 0x0000001514147209 */
/* 0x000fe40007800000 */
/*04d0*/ FMNMX R21, R22.reuse, R23.reuse, PT ; /* 0x0000001716157209 */
/* 0x0d0fe40003800000 */
/*04e0*/ FMNMX R23, R22, R23, !PT ; /* 0x0000001716177209 */
/* 0x000fe40007800000 */
/*04f0*/ FMNMX R4, R4, R3, PT ; /* 0x0000000304047209 */
/* 0x020fe40003800000 */
/*0500*/ FMNMX R20, R3, R20, !PT ; /* 0x0000001403147209 */
/* 0x000fe40007800000 */
/*0510*/ FMNMX R21, R21, R2, PT ; /* 0x0000000215157209 */
/* 0x001fc40003800000 */
/*0520*/ FMNMX R23, R2, R23, !PT ; /* 0x0000001702177209 */
/* 0x000fe40007800000 */
/*0530*/ FMNMX R4, R5, R4, PT ; /* 0x0000000405047209 */
/* 0x000fe20003800000 */
/*0540*/ STS [R8.X4+0x1600], R21 ; /* 0x0016001508007388 */
/* 0x0003e20000004800 */
/*0550*/ FMNMX R20, R7, R20, !PT ; /* 0x0000001407147209 */
/* 0x000fe40007800000 */
/*0560*/ FMNMX R3, R21, R4, PT ; /* 0x0000000415037209 */
/* 0x000fe20003800000 */
/*0570*/ STS [R8.X4+0x1c00], R23 ; /* 0x001c001708007388 */
/* 0x0003e20000004800 */
/*0580*/ FMNMX R25, R23, R20, !PT ; /* 0x0000001417197209 */
/* 0x000fc60007800000 */
/*0590*/ STS [R8.X4+0x1400], R3 ; /* 0x0014000308007388 */
/* 0x0003e80000004800 */
/*05a0*/ STS [R8.X4+0x1a00], R25 ; /* 0x001a001908007388 */
/* 0x0003e40000004800 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ ISETP.GT.OR P1, PT, R8.reuse, 0x7d, !P1 ; /* 0x0000007d0800780c */
/* 0x040fe40004f24670 */
/*05e0*/ ISETP.GT.AND P0, PT, R8, 0x7d, PT ; /* 0x0000007d0800780c */
/* 0x000fe40003f04270 */
/*05f0*/ ISETP.GT.OR P1, PT, R10, R13, P1 ; /* 0x0000000d0a00720c */
/* 0x000fe20000f24670 */
/*0600*/ BSSY B0, 0x7d0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0610*/ @P1 BRA 0x7c0 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0620*/ LDS R6, [R8.X4+0x1a08] ; /* 0x001a080008067984 */
/* 0x000fe80000004800 */
/*0630*/ LDS R23, [R8.X4+0x1a00] ; /* 0x001a000008177984 */
/* 0x002e680000004800 */
/*0640*/ LDS R4, [R8.X4+0x1400] ; /* 0x0014000008047984 */
/* 0x000fe80000004800 */
/*0650*/ LDS R5, [R8.X4+0x1408] ; /* 0x0014080008057984 */
/* 0x000ea80000004800 */
/*0660*/ LDS R25, [R8.X4+0x1804] ; /* 0x0018040008197984 */
/* 0x000ee80000004800 */
/*0670*/ LDS R7, [R8.X4+0x1204] ; /* 0x0012040008077984 */
/* 0x000f280000004800 */
/*0680*/ LDS R27, [R8.X4+0x1c04] ; /* 0x001c0400081b7984 */
/* 0x000f680000004800 */
/*0690*/ LDS R21, [R8.X4+0x1604] ; /* 0x0016040008157984 */
/* 0x000e280000004800 */
/*06a0*/ LDS R3, [R17.X4+0x604] ; /* 0x0006040011037984 */
/* 0x000e280000004800 */
/*06b0*/ LDS R16, [R16+0x604] ; /* 0x0006040010107984 */
/* 0x001e280000000800 */
/*06c0*/ LDS R2, [R15.X4+0x604] ; /* 0x000604000f027984 */
/* 0x000e220000004800 */
/*06d0*/ FMNMX R6, R6, R23, !PT ; /* 0x0000001706067209 */
/* 0x002fc40007800000 */
/*06e0*/ FMNMX R4, R4, R5, PT ; /* 0x0000000504047209 */
/* 0x004fe40003800000 */
/*06f0*/ FMNMX R6, R6, R25, !PT ; /* 0x0000001906067209 */
/* 0x008fe40007800000 */
/*0700*/ FMNMX R4, R4, R7, PT ; /* 0x0000000704047209 */
/* 0x010fe40003800000 */
/*0710*/ FMNMX R6, R6, R27, !PT ; /* 0x0000001b06067209 */
/* 0x020fe40007800000 */
/*0720*/ FMNMX R4, R4, R21, PT ; /* 0x0000001504047209 */
/* 0x000fe40003800000 */
/*0730*/ FMNMX R5, R3, R6, !PT ; /* 0x0000000603057209 */
/* 0x000fc40007800000 */
/*0740*/ FMNMX R3, R4, R3, PT ; /* 0x0000000304037209 */
/* 0x000fe40003800000 */
/*0750*/ FMNMX R5, R16, R5, !PT ; /* 0x0000000510057209 */
/* 0x001fe40007800000 */
/*0760*/ FMNMX R3, R3, R16, PT ; /* 0x0000001003037209 */
/* 0x000fe40003800000 */
/*0770*/ FMNMX R5, R5, c[0x3][0x0], !PT ; /* 0x00c0000005057a09 */
/* 0x000fe40007800000 */
/*0780*/ FMNMX R3, R3, c[0x3][0x4], PT ; /* 0x00c0010003037a09 */
/* 0x000fe40003800000 */
/*0790*/ FSETP.GT.AND P1, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x000fc80003f24000 */
/*07a0*/ FSETP.LT.OR P1, PT, R2, R3, P1 ; /* 0x000000030200720b */
/* 0x000fda0000f21400 */
/*07b0*/ @P1 LOP3.LUT R0, R0, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000000001812 */
/* 0x000fe400078efcff */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07e0*/ ISETP.GE.AND P1, PT, R11.reuse, 0x2, PT ; /* 0x000000020b00780c */
/* 0x040fe20003f26270 */
/*07f0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0800*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0820*/ SEL R11, R11, RZ, !P1 ; /* 0x000000ff0b0b7207 */
/* 0x000fe20004800000 */
/*0830*/ @P2 BRA 0x150 ; /* 0xfffff91000002947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x180], P0 ; /* 0x000060000a007a0c */
/* 0x000fda0000706670 */
/*0850*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe400078e00ff */
/*0870*/ IMAD R2, R9, c[0x0][0x184], R10 ; /* 0x0000610009027a24 */
/* 0x000fc800078e020a */
/*0880*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0890*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101906 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Find3DMinMaxPiPfS0_S0_iii
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.p2align 8
.type _Z12Find3DMinMaxPiPfS0_S0_iii,@function
_Z12Find3DMinMaxPiPfS0_S0_iii:
s_clause 0x1
s_load_b256 s[16:23], s[0:1], 0x8
s_load_b32 s11, s[0:1], 0x28
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_Threshold@rel32@lo+8
s_addc_u32 s5, s5, d_Threshold@rel32@hi+16
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_Threshold@rel32@lo+4
s_addc_u32 s7, s7, d_Threshold@rel32@hi+12
s_clause 0x1
s_load_b32 s9, s[4:5], 0x0
s_load_b32 s10, s[6:7], 0x0
s_mul_i32 s2, s14, 0x7e
v_dual_mov_b32 v17, 0 :: v_dual_lshlrev_b32 v4, 2, v0
v_add_nc_u32_e32 v1, s2, v0
v_add_nc_u32_e32 v3, -15, v0
s_add_i32 s8, s2, 0x7d
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 0x1800, v4
v_add_nc_u32_e32 v6, 0x1a00, v4
v_dual_mov_b32 v18, v3 :: v_dual_add_nc_u32 v7, 0x1c00, v4
v_add_nc_u32_e32 v8, 0x1200, v4
v_add_nc_u32_e32 v9, 0x1400, v4
v_add_nc_u32_e32 v10, 0x1600, v4
v_add_nc_u32_e32 v11, 0x1a08, v4
v_add_nc_u32_e32 v12, 0x1804, v4
v_add_nc_u32_e32 v13, 0x1c04, v4
v_add_nc_u32_e32 v14, 0x1408, v4
v_add_nc_u32_e32 v15, 0x1204, v4
v_add_nc_u32_e32 v16, 0x1604, v4
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v19, v3 :: v_dual_add_nc_u32 v2, -16, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s22, -1
v_cmp_lt_u32_e32 vcc_lo, 14, v0
s_min_i32 s6, s8, s5
v_cmp_gt_u32_e64 s2, 0x80, v0
v_cmp_gt_u32_e64 s3, 0x7e, v0
v_cmp_lt_i32_e64 s4, 15, v1
v_cmp_le_i32_e64 s5, s22, v2
v_cmp_ge_i32_e64 s6, s6, v1
s_lshl_b32 s12, s15, 5
s_add_i32 s11, s11, -1
s_add_i32 s12, s12, -1
s_mov_b32 s13, 0
s_mov_b32 s14, 0
.LBB0_1:
s_lshl_b32 s8, s13, 7
s_and_saveexec_b32 s24, vcc_lo
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v20, s8, v3
s_and_saveexec_b32 s7, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s25, exec_lo, s7
s_cbranch_execz .LBB0_8
s_and_saveexec_b32 s26, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB0_5
v_lshlrev_b32_e32 v21, 2, v20
s_mov_b32 s7, 0
ds_store_2addr_stride64_b32 v21, v17, v17 offset1:6
.LBB0_5:
s_or_saveexec_b32 s26, s26
v_mov_b32_e32 v21, s7
s_xor_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_7
s_add_i32 s7, s12, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_max_i32 s7, s7, 0
s_min_i32 s7, s7, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[21:22], null, s7, s23, v[2:3]
v_ashrrev_i32_e32 v22, 31, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[21:22], 2, v[21:22]
v_add_co_u32 v23, s7, s16, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v24, s7, s17, v22, s7
v_add_co_u32 v25, s7, s18, v21
v_add_co_ci_u32_e64 v26, s7, s19, v22, s7
v_add_co_u32 v21, s7, s20, v21
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s7, s21, v22, s7
global_load_b32 v23, v[23:24], off
global_load_b32 v24, v[25:26], off
global_load_b32 v21, v[21:22], off
v_lshlrev_b32_e32 v22, 2, v20
s_waitcnt vmcnt(1)
ds_store_2addr_stride64_b32 v22, v23, v24 offset1:6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s26
.LBB0_8:
s_or_saveexec_b32 s7, s25
v_lshlrev_b32_e32 v20, 2, v20
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_10
s_waitcnt vmcnt(0)
v_mov_b32_e32 v21, 0
ds_store_2addr_stride64_b32 v20, v17, v17 offset1:6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
ds_store_b32 v20, v21 offset:3072
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s24
v_add_nc_u32_e32 v20, s8, v0
s_cmp_gt_u32 s14, 1
v_lshlrev_b32_e32 v21, 2, v19
v_lshlrev_b32_e32 v19, 2, v18
s_cselect_b32 s7, -1, 0
v_lshlrev_b32_e32 v22, 2, v20
s_and_b32 s24, s2, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s8, s24
s_cbranch_execz .LBB0_13
ds_load_2addr_stride64_b32 v[23:24], v21 offset1:6
ds_load_2addr_stride64_b32 v[25:26], v19 offset1:6
ds_load_2addr_stride64_b32 v[27:28], v22 offset1:6
ds_load_b32 v29, v21 offset:3072
ds_load_b32 v30, v19 offset:3072
ds_load_b32 v31, v22 offset:3072
s_waitcnt lgkmcnt(3)
v_min3_f32 v32, v23, v25, v27
v_min3_f32 v33, v24, v26, v28
v_max3_f32 v23, v23, v25, v27
s_waitcnt lgkmcnt(0)
v_min3_f32 v34, v29, v30, v31
v_max3_f32 v24, v24, v26, v28
v_max3_f32 v25, v29, v30, v31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v26, v32, v33, v34
v_max3_f32 v24, v23, v24, v25
ds_store_b32 v5, v32
ds_store_b32 v6, v26
ds_store_b32 v7, v34
ds_store_b32 v8, v23
ds_store_b32 v9, v24
ds_store_b32 v10, v25
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
v_lshrrev_b32_e32 v4, 1, v4
s_and_b32 s7, s3, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s7, s6
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s24, s7
s_cbranch_execz .LBB0_15
ds_load_b32 v23, v6
ds_load_b32 v24, v12
ds_load_b32 v25, v13
ds_load_b32 v26, v14
ds_load_b32 v27, v15
ds_load_b32 v28, v16
ds_load_b32 v29, v11
ds_load_b32 v30, v9
ds_load_b32 v21, v21 offset:1540
ds_load_b32 v22, v22 offset:1540
ds_load_b32 v19, v19 offset:1540
s_waitcnt lgkmcnt(4)
v_min3_f32 v23, v23, v29, v24
s_waitcnt lgkmcnt(3)
v_max3_f32 v24, v30, v26, v27
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v23, v23, v25, v21
v_max3_f32 v21, v24, v28, v21
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min3_f32 v23, v23, v22, s9
v_max3_f32 v21, v21, v22, s10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s7, v19, v23
v_cmp_gt_f32_e64 s8, v19, v21
v_or_b32_e32 v19, 0x80000000, v4
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s7, s7, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v4, v4, v19, s7
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s24
s_add_i32 s7, s13, 1
s_cmp_lt_i32 s13, 2
s_cselect_b32 s13, s7, 0
s_add_i32 s14, s14, 1
s_barrier
s_cmp_eq_u32 s14, 34
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
v_dual_mov_b32 v19, v18 :: v_dual_mov_b32 v18, v20
s_branch .LBB0_1
.LBB0_17:
v_cmp_gt_u32_e32 vcc_lo, 0x7e, v0
v_cmp_gt_i32_e64 s2, s22, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s23, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Find3DMinMaxPiPfS0_S0_iii
.amdhsa_group_segment_fixed_size 7680
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z12Find3DMinMaxPiPfS0_S0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_Threshold
.type d_Threshold,@object
.section .bss,"aw",@nobits
.globl d_Threshold
.p2align 2, 0x0
d_Threshold:
.zero 8
.size d_Threshold, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_Threshold
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 7680
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Find3DMinMaxPiPfS0_S0_iii
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z12Find3DMinMaxPiPfS0_S0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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