system
stringclasses 7
values | input
stringlengths 10
94.5k
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stringlengths 14
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You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a954b_00000000-6_Find3DMinMax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
.type _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, @function
_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, .-_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.type _Z12Find3DMinMaxPiPfS0_S0_iii, @function
_Z12Find3DMinMaxPiPfS0_S0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12Find3DMinMaxPiPfS0_S0_iii, .-_Z12Find3DMinMaxPiPfS0_S0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12Find3DMinMaxPiPfS0_S0_iii"
.LC1:
.string "d_Threshold"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11d_Threshold(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11d_Threshold
.comm _ZL11d_Threshold,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Find3DMinMax.hip"
.globl _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii # -- Begin function _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.p2align 4, 0x90
.type _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii,@function
_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii: # @_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12Find3DMinMaxPiPfS0_S0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Find3DMinMaxPiPfS0_S0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_Threshold, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_Threshold,@object # @d_Threshold
.local d_Threshold
.comm d_Threshold,8,4
.type _Z12Find3DMinMaxPiPfS0_S0_iii,@object # @_Z12Find3DMinMaxPiPfS0_S0_iii
.section .rodata,"a",@progbits
.globl _Z12Find3DMinMaxPiPfS0_S0_iii
.p2align 3, 0x0
_Z12Find3DMinMaxPiPfS0_S0_iii:
.quad _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.size _Z12Find3DMinMaxPiPfS0_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12Find3DMinMaxPiPfS0_S0_iii"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_Threshold"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_Threshold
.addrsig_sym _Z12Find3DMinMaxPiPfS0_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
cudaMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
cudaMemcpy(d_c, c, size, cudaMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
cudaMemcpy(res, d_c, size, cudaMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z11rotateArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0060*/ IADD3 R0, R5, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x002fe40007ffe0ff */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e0004 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
cudaMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
cudaMemcpy(d_c, c, size, cudaMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
cudaMemcpy(res, d_c, size, cudaMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00021d3d_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11rotateArrayPiiPii
.type _Z32__device_stub__Z11rotateArrayPiiPii, @function
_Z32__device_stub__Z11rotateArrayPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11rotateArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11rotateArrayPiiPii, .-_Z32__device_stub__Z11rotateArrayPiiPii
.globl _Z11rotateArrayPii
.type _Z11rotateArrayPii, @function
_Z11rotateArrayPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11rotateArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11rotateArrayPii, .-_Z11rotateArrayPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "First thirty elements are as follows:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Original\tNew\n"
.LC2:
.string "%d\t\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 4096(%r12), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L14:
movl 0(%r13,%rbx), %ecx
movl (%r12,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $120, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11rotateArrayPiiPii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11rotateArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rotateArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
cudaMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
cudaMemcpy(d_c, c, size, cudaMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
cudaMemcpy(res, d_c, size, cudaMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
cudaFree(d_c);
return 0;
} | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
hipMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
hipMemcpy(res, d_c, size, hipMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
hipMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
hipMemcpy(res, d_c, size, hipMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rotateArrayPii
.globl _Z11rotateArrayPii
.p2align 8
.type _Z11rotateArrayPii,@function
_Z11rotateArrayPii:
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v3, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rotateArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rotateArrayPii, .Lfunc_end0-_Z11rotateArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rotateArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11rotateArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
}
#define N 1024
int main(void)
{
int *c, *res;
int *d_c;
int size = N * sizeof(int);
//Allocate memory for array in GPU
hipMalloc((void **)&d_c, size);
//Allocate memory on host
c = (int *)malloc(size);
res = (int *)malloc(size);
srand(time(NULL));
//Populate array
for (int i = 0; i < N; ++i)
{
c[i] = rand()%20;
}
//Copy input to device
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
//Launch rotateArray() kernel on GPU
rotateArray<<<1,N>>>(d_c, N);
//Copy result back to host
hipMemcpy(res, d_c, size, hipMemcpyDeviceToHost);
printf("First thirty elements are as follows:\n");
printf("Original\tNew\n");
for (int i = 0; i < 30; ++i)
{
printf("%d\t\t%d\n", c[i], res[i]);
}
//Cleanup
free(c); free(res);
hipFree(d_c);
return 0;
} | .text
.file "q4.hip"
.globl _Z26__device_stub__rotateArrayPii # -- Begin function _Z26__device_stub__rotateArrayPii
.p2align 4, 0x90
.type _Z26__device_stub__rotateArrayPii,@function
_Z26__device_stub__rotateArrayPii: # @_Z26__device_stub__rotateArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__rotateArrayPii, .Lfunc_end0-_Z26__device_stub__rotateArrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1024, 20(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl (%r14,%r15,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $30, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rotateArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rotateArrayPii,@object # @_Z11rotateArrayPii
.section .rodata,"a",@progbits
.globl _Z11rotateArrayPii
.p2align 3, 0x0
_Z11rotateArrayPii:
.quad _Z26__device_stub__rotateArrayPii
.size _Z11rotateArrayPii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d\t\t%d\n"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11rotateArrayPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "First thirty elements are as follows:"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Original\tNew"
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rotateArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rotateArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11rotateArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0060*/ IADD3 R0, R5, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x002fe40007ffe0ff */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e0004 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rotateArrayPii
.globl _Z11rotateArrayPii
.p2align 8
.type _Z11rotateArrayPii,@function
_Z11rotateArrayPii:
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v3, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rotateArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rotateArrayPii, .Lfunc_end0-_Z11rotateArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rotateArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11rotateArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021d3d_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11rotateArrayPiiPii
.type _Z32__device_stub__Z11rotateArrayPiiPii, @function
_Z32__device_stub__Z11rotateArrayPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11rotateArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11rotateArrayPiiPii, .-_Z32__device_stub__Z11rotateArrayPiiPii
.globl _Z11rotateArrayPii
.type _Z11rotateArrayPii, @function
_Z11rotateArrayPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11rotateArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11rotateArrayPii, .-_Z11rotateArrayPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "First thirty elements are as follows:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Original\tNew\n"
.LC2:
.string "%d\t\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 4096(%r12), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L14:
movl 0(%r13,%rbx), %ecx
movl (%r12,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $120, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11rotateArrayPiiPii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11rotateArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rotateArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q4.hip"
.globl _Z26__device_stub__rotateArrayPii # -- Begin function _Z26__device_stub__rotateArrayPii
.p2align 4, 0x90
.type _Z26__device_stub__rotateArrayPii,@function
_Z26__device_stub__rotateArrayPii: # @_Z26__device_stub__rotateArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__rotateArrayPii, .Lfunc_end0-_Z26__device_stub__rotateArrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1024, 20(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl (%r14,%r15,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $30, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rotateArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rotateArrayPii,@object # @_Z11rotateArrayPii
.section .rodata,"a",@progbits
.globl _Z11rotateArrayPii
.p2align 3, 0x0
_Z11rotateArrayPii:
.quad _Z26__device_stub__rotateArrayPii
.size _Z11rotateArrayPii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d\t\t%d\n"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11rotateArrayPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "First thirty elements are as follows:"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Original\tNew"
.size .Lstr.1, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rotateArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rotateArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" | .file "tmpxft_0008fc25_00000000-6_cuda-march.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed -march.
// (Specifically, we want to pass it to host compilation, but not to device
// compilation or ptxas!)
//
// REQUIRES: clang-driver
// REQUIRES: x86-registered-target
// REQUIRES: nvptx-registered-target
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell %s 2>&1 | FileCheck %s
// RUN: %clang -### -target x86_64-linux-gnu -c -march=haswell --cuda-gpu-arch=sm_20 %s 2>&1 | \
// RUN: FileCheck %s
// CHECK: bin{{/|\\+}}clang
// CHECK: "-cc1"
// CHECK-SAME: "-triple" "nvptx
// CHECK-SAME: "-target-cpu" "sm_20"
// CHECK: ptxas
// CHECK-SAME: "--gpu-name" "sm_20"
// CHECK: bin{{/|\\+}}clang
// CHECK-SAME: "-cc1"
// CHECK-SAME: "-target-cpu" "haswell" | .text
.file "cuda-march.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008fc25_00000000-6_cuda-march.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-march.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda( cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( cudaSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( cudaMalloc(&d_idata, mem_size) );
checkCuda( cudaMalloc(&d_cdata, mem_size) );
checkCuda( cudaMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice) );
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda( cudaEventCreate(&startEvent) );
checkCuda( cudaEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( cudaEventDestroy(startEvent) );
checkCuda( cudaEventDestroy(stopEvent) );
checkCuda( cudaFree(d_tdata) );
checkCuda( cudaFree(d_cdata) );
checkCuda( cudaFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | code for sm_80
Function : _Z24transposeNoBankConflictsPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R3, R8, 0x5, RZ ; /* 0x0000000508037819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R4, R14, 0x5 ; /* 0x0000000e04007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R6, R16, R5, 0x5 ; /* 0x0000000510067211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R7, R6, R3, R0 ; /* 0x0000000306077224 */
/* 0x000fe200078e0200 */
/*00c0*/ SHF.L.U32 R0, R8, 0x8, RZ ; /* 0x0000000808007819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0202 */
/*00e0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0110*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0130*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0150*/ IMAD R19, R5, 0x21, R14 ; /* 0x0000002105137824 */
/* 0x000fe400078e020e */
/*0160*/ IMAD R18, R14, 0x21, R5 ; /* 0x000000210e127824 */
/* 0x000fe200078e0205 */
/*0170*/ LEA R14, R16, R14, 0x5 ; /* 0x0000000e100e7211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R4, R4, R5, 0x5 ; /* 0x0000000504047211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R3, R3, R4, R14 ; /* 0x0000000403037224 */
/* 0x000fc800078e020e */
/*01a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*01b0*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*01c0*/ STS [R19.X4], R6 ; /* 0x0000000613007388 */
/* 0x0041e80000004800 */
/*01d0*/ STS [R19.X4+0x420], R8 ; /* 0x0004200813007388 */
/* 0x0083e80000004800 */
/*01e0*/ STS [R19.X4+0x840], R10 ; /* 0x0008400a13007388 */
/* 0x010fe80000004800 */
/*01f0*/ STS [R19.X4+0xc60], R12 ; /* 0x000c600c13007388 */
/* 0x020fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R15, [R18.X4] ; /* 0x00000000120f7984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R17, [R18.X4+0x20] ; /* 0x0000200012117984 */
/* 0x000ee80000004800 */
/*0230*/ LDS R11, [R18.X4+0x40] ; /* 0x00004000120b7984 */
/* 0x000f280000004800 */
/*0240*/ LDS R13, [R18.X4+0x60] ; /* 0x00006000120d7984 */
/* 0x000f620000004800 */
/*0250*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x001fcc00078e0204 */
/*0260*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x002fe200078e0206 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x004fe8000c101904 */
/*0280*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x008fe8000c101904 */
/*0290*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x010fe8000c101904 */
/*02a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x020fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18transposeCoalescedPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R3, R8, 0x5, RZ ; /* 0x0000000508037819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R4, R14, 0x5 ; /* 0x0000000e04007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R6, R16, R5, 0x5 ; /* 0x0000000510067211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R7, R6, R3, R0 ; /* 0x0000000306077224 */
/* 0x000fe200078e0200 */
/*00c0*/ SHF.L.U32 R0, R8, 0x8, RZ ; /* 0x0000000808007819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0202 */
/*00e0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0110*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0130*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0150*/ LEA R19, R5, R14.reuse, 0x5 ; /* 0x0000000e05137211 */
/* 0x080fe400078e28ff */
/*0160*/ LEA R18, R14, R5.reuse, 0x5 ; /* 0x000000050e127211 */
/* 0x080fe400078e28ff */
/*0170*/ LEA R14, R16, R14, 0x5 ; /* 0x0000000e100e7211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R4, R4, R5, 0x5 ; /* 0x0000000504047211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R3, R3, R4, R14 ; /* 0x0000000403037224 */
/* 0x000fc800078e020e */
/*01a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*01b0*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*01c0*/ STS [R19.X4], R6 ; /* 0x0000000613007388 */
/* 0x0041e80000004800 */
/*01d0*/ STS [R19.X4+0x400], R8 ; /* 0x0004000813007388 */
/* 0x0083e80000004800 */
/*01e0*/ STS [R19.X4+0x800], R10 ; /* 0x0008000a13007388 */
/* 0x010fe80000004800 */
/*01f0*/ STS [R19.X4+0xc00], R12 ; /* 0x000c000c13007388 */
/* 0x020fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R15, [R18.X4] ; /* 0x00000000120f7984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R17, [R18.X4+0x20] ; /* 0x0000200012117984 */
/* 0x000ee80000004800 */
/*0230*/ LDS R11, [R18.X4+0x40] ; /* 0x00004000120b7984 */
/* 0x000f280000004800 */
/*0240*/ LDS R13, [R18.X4+0x60] ; /* 0x00006000120d7984 */
/* 0x000f620000004800 */
/*0250*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x001fcc00078e0204 */
/*0260*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x002fe200078e0206 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x004fe8000c101904 */
/*0280*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x008fe8000c101904 */
/*0290*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x010fe8000c101904 */
/*02a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x020fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14transposeNaivePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R4, R11, 0x5, RZ ; /* 0x000000050b047819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R5, R5, R2, 0x5 ; /* 0x0000000205057211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R2, R5, R4, R0 ; /* 0x0000000405027224 */
/* 0x000fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0207 */
/*00d0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ SHF.L.U32 R11, R11, 0x8, RZ ; /* 0x000000080b0b7819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R4, R0, R4, R5 ; /* 0x0000000400047224 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0110*/ IMAD.WIDE R6, R11.reuse, 0x4, R2 ; /* 0x000000040b067825 */
/* 0x040fe200078e0202 */
/*0120*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101904 */
/*0130*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE R8, R11, 0x4, R6 ; /* 0x000000040b087825 */
/* 0x000fc600078e0206 */
/*0150*/ STG.E [R4.64+0x20], R15 ; /* 0x0000200f04007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R10, R11, 0x4, R8 ; /* 0x000000040b0a7825 */
/* 0x000fc600078e0208 */
/*0180*/ STG.E [R4.64+0x40], R17 ; /* 0x0000401104007986 */
/* 0x004fe8000c101904 */
/*0190*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64+0x60], R11 ; /* 0x0000600b04007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13copySharedMemPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0xc] ; /* 0x00000300000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R2, R13.reuse, 0x5, RZ ; /* 0x000000050d027819 */
/* 0x040fe400000006ff */
/*0070*/ SHF.L.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7819 */
/* 0x000fe200000006ff */
/*0080*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0090*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000e620000002200 */
/*00a0*/ LEA R0, R0, R11, 0x5 ; /* 0x0000000b00007211 */
/* 0x001fc400078e28ff */
/*00b0*/ LEA R3, R3, R18, 0x5 ; /* 0x0000001203037211 */
/* 0x002fca00078e28ff */
/*00c0*/ IMAD R0, R3, R2, R0 ; /* 0x0000000203007224 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R23, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0217 */
/*00e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x0002e2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000962000c1e1900 */
/*0130*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fca00078e0206 */
/*0140*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000962000c1e1900 */
/*0150*/ LEA R11, R18, R11, 0x5 ; /* 0x0000000b120b7211 */
/* 0x000fe200078e28ff */
/*0160*/ IMAD.WIDE R2, R0, R23, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0217 */
/*0170*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x002fcc00078e0202 */
/*0180*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x010fcc00078e0204 */
/*0190*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fe200078e0206 */
/*01a0*/ STS [R11.X4], R10 ; /* 0x0000000a0b007388 */
/* 0x004fe80000004800 */
/*01b0*/ STS [R11.X4+0x400], R12 ; /* 0x0004000c0b007388 */
/* 0x008fe80000004800 */
/*01c0*/ STS [R11.X4+0x800], R14 ; /* 0x0008000e0b007388 */
/* 0x020fe80000004800 */
/*01d0*/ STS [R11.X4+0xc00], R16 ; /* 0x000c00100b007388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ LDS R15, [R11.X4] ; /* 0x000000000b0f7984 */
/* 0x000e280000004800 */
/*0200*/ LDS R17, [R11.X4+0x400] ; /* 0x000400000b117984 */
/* 0x000e680000004800 */
/*0210*/ LDS R19, [R11.X4+0x800] ; /* 0x000800000b137984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R21, [R11.X4+0xc00] ; /* 0x000c00000b157984 */
/* 0x000ee80000004800 */
/*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x001fe8000c101904 */
/*0240*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x002fe8000c101904 */
/*0250*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x004fe8000c101904 */
/*0260*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x008fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4copyPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0060*/ LEA R0, R0, R7, 0x5 ; /* 0x0000000700007211 */
/* 0x001fe200078e28ff */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fca00078e0203 */
/*0090*/ LEA R0, R0, R5, 0x5 ; /* 0x0000000500007211 */
/* 0x004fca00078e28ff */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R15, c[0x0][0xc] ; /* 0x00000300000f7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0207 */
/*00e0*/ SHF.L.U32 R15, R15, 0x8, RZ ; /* 0x000000080f0f7819 */
/* 0x000fca00000006ff */
/*00f0*/ IMAD.WIDE R6, R15.reuse, 0x4, R2 ; /* 0x000000040f067825 */
/* 0x040fe200078e0202 */
/*0100*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x004fe8000c101904 */
/*0110*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R10, R15.reuse, 0x4, R6 ; /* 0x000000040f0a7825 */
/* 0x040fe200078e0206 */
/*0140*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x004fe8000c101904 */
/*0150*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*0180*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x004fea000c101904 */
/*0190*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.WIDE R14, R15, 0x4, R2 ; /* 0x000000040f0e7825 */
/* 0x000fca00078e0202 */
/*01b0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x004fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda( cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( cudaSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( cudaMalloc(&d_idata, mem_size) );
checkCuda( cudaMalloc(&d_cdata, mem_size) );
checkCuda( cudaMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice) );
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda( cudaEventCreate(&startEvent) );
checkCuda( cudaEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( cudaEventDestroy(startEvent) );
checkCuda( cudaEventDestroy(stopEvent) );
checkCuda( cudaFree(d_tdata) );
checkCuda( cudaFree(d_cdata) );
checkCuda( cudaFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .file "tmpxft_00020de3_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f %f\n"
.LC1:
.string "*** FAILED ***"
.LC2:
.string "%25s\n"
.LC5:
.string "%20.2f\n"
.text
.globl _Z11postprocessPKfS0_if
.type _Z11postprocessPKfS0_if, @function
_Z11postprocessPKfS0_if:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movaps %xmm0, %xmm3
testl %edx, %edx
jle .L4
movslq %edx, %rcx
movl $0, %eax
.L8:
movss (%rsi,%rax,4), %xmm0
movss (%rdi,%rax,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L11
jne .L11
addq $1, %rax
cmpq %rcx, %rax
jne .L8
.L4:
addl %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L10:
mulsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
cvtss2sd %xmm3, %xmm3
divsd %xmm3, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L9:
shrq %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L10
.cfi_endproc
.LFE2058:
.size _Z11postprocessPKfS0_if, .-_Z11postprocessPKfS0_if
.globl _Z26__device_stub__Z4copyPfPKfPfPKf
.type _Z26__device_stub__Z4copyPfPKfPfPKf, @function
_Z26__device_stub__Z4copyPfPKfPfPKf:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z4copyPfPKfPfPKf, .-_Z26__device_stub__Z4copyPfPKfPfPKf
.globl _Z4copyPfPKf
.type _Z4copyPfPKf, @function
_Z4copyPfPKf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4copyPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4copyPfPKf, .-_Z4copyPfPKf
.globl _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.type _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, @function
_Z36__device_stub__Z13copySharedMemPfPKfPfPKf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13copySharedMemPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, .-_Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.globl _Z13copySharedMemPfPKf
.type _Z13copySharedMemPfPKf, @function
_Z13copySharedMemPfPKf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13copySharedMemPfPKf, .-_Z13copySharedMemPfPKf
.globl _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.type _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, @function
_Z37__device_stub__Z14transposeNaivePfPKfPfPKf:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14transposeNaivePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, .-_Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.globl _Z14transposeNaivePfPKf
.type _Z14transposeNaivePfPKf, @function
_Z14transposeNaivePfPKf:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z14transposeNaivePfPKf, .-_Z14transposeNaivePfPKf
.globl _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf
.type _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf, @function
_Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18transposeCoalescedPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf, .-_Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf
.globl _Z18transposeCoalescedPfPKf
.type _Z18transposeCoalescedPfPKf, @function
_Z18transposeCoalescedPfPKf:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z18transposeCoalescedPfPKf, .-_Z18transposeCoalescedPfPKf
.globl _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf
.type _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf, @function
_Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf:
.LFB2092:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24transposeNoBankConflictsPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf, .-_Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf
.globl _Z24transposeNoBankConflictsPfPKf
.type _Z24transposeNoBankConflictsPfPKf, @function
_Z24transposeNoBankConflictsPfPKf:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z24transposeNoBankConflictsPfPKf, .-_Z24transposeNoBankConflictsPfPKf
.section .rodata.str1.1
.LC6:
.string "\nDevice : %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n"
.align 8
.LC8:
.string "dimGrid: %d %d %d. dimBlock: %d %d %d\n"
.section .rodata.str1.1
.LC9:
.string "Bandwidth (GB/s)"
.LC10:
.string "Routine"
.LC11:
.string "%25s%25s\n"
.LC12:
.string "copy"
.LC13:
.string "%25s"
.LC14:
.string "shared memory copy"
.LC15:
.string "naive transpose"
.LC16:
.string "coalesced transpose"
.LC17:
.string "conflict-free transpose"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1120, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rdx
movq %rdx, 1112(%rsp)
xorl %edx, %edx
movl $0, %ebx
cmpl $1, %edi
jg .L87
.L55:
leaq 80(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pushq $32
.cfi_def_cfa_offset 1176
pushq $32
.cfi_def_cfa_offset 1184
movl $8, %r9d
movl $32, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1168
pushq $1
.cfi_def_cfa_offset 1176
pushq $8
.cfi_def_cfa_offset 1184
movl $32, %r9d
movl $1, %r8d
movl $32, %ecx
movl $32, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1168
movl %ebx, %edi
call cudaSetDevice@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq %rbp, %rsi
movl $1024, %ecx
.L56:
leal -1024(%rcx), %eax
movq %rsi, %rdx
.L57:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L57
addq $4096, %rsi
addl $1024, %ecx
cmpl $1049600, %ecx
jne .L56
movq %r12, %rdi
leaq 4194304(%rbp), %rcx
movl $0, %esi
.L58:
leaq -4194304(%rcx), %rax
movq %rdi, %rdx
.L59:
movss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $4096, %rax
addq $4, %rdx
cmpq %rcx, %rax
jne .L59
addl $1, %esi
addq $4096, %rdi
addq $4, %rcx
cmpl $1024, %esi
jne .L58
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $8, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L61:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %r14d
jmp .L63
.L87:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L55
.L88:
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z4copyPfPKfPfPKf
jmp .L61
.L62:
subl $1, %r14d
je .L89
.L63:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z4copyPfPKfPfPKf
jmp .L62
.L89:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movss 12(%rsp), %xmm0
movl $1048576, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z11postprocessPKfS0_if
leaq .LC14(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L64:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %r14d
jmp .L66
.L90:
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
jmp .L64
.L65:
subl $1, %r14d
je .L91
.L66:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
jmp .L65
.L91:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movss 12(%rsp), %xmm0
movl $1048576, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z11postprocessPKfS0_if
leaq .LC15(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L67:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %r14d
jmp .L69
.L92:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
jmp .L67
.L68:
subl $1, %r14d
je .L93
.L69:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L68
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
jmp .L68
.L93:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss 12(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z11postprocessPKfS0_if
leaq .LC16(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L70:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %r14d
jmp .L72
.L94:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf
jmp .L70
.L71:
subl $1, %r14d
je .L95
.L72:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L71
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z41__device_stub__Z18transposeCoalescedPfPKfPfPKf
jmp .L71
.L95:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss 12(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z11postprocessPKfS0_if
leaq .LC17(%rip), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L73:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %r14d
jmp .L75
.L96:
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf
jmp .L73
.L74:
subl $1, %r14d
je .L97
.L75:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L74
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z47__device_stub__Z24transposeNoBankConflictsPfPKfPfPKf
jmp .L74
.L97:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss 12(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z11postprocessPKfS0_if
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L98
movl $0, %eax
addq $1120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z24transposeNoBankConflictsPfPKf"
.section .rodata.str1.1
.LC19:
.string "_Z18transposeCoalescedPfPKf"
.LC20:
.string "_Z14transposeNaivePfPKf"
.LC21:
.string "_Z13copySharedMemPfPKf"
.LC22:
.string "_Z4copyPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z24transposeNoBankConflictsPfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeCoalescedPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z14transposeNaivePfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z13copySharedMemPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -1598689907
.long 1051772663
.align 8
.LC4:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda( cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( cudaSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( cudaMalloc(&d_idata, mem_size) );
checkCuda( cudaMalloc(&d_cdata, mem_size) );
checkCuda( cudaMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice) );
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda( cudaEventCreate(&startEvent) );
checkCuda( cudaEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( cudaMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_cdata, d_cdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( cudaMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( cudaEventDestroy(startEvent) );
checkCuda( cudaEventDestroy(stopEvent) );
checkCuda( cudaFree(d_tdata) );
checkCuda( cudaFree(d_cdata) );
checkCuda( cudaFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda( hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( hipSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( hipMalloc(&d_idata, mem_size) );
checkCuda( hipMalloc(&d_cdata, mem_size) );
checkCuda( hipMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice) );
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( hipEventDestroy(startEvent) );
checkCuda( hipEventDestroy(stopEvent) );
checkCuda( hipFree(d_tdata) );
checkCuda( hipFree(d_cdata) );
checkCuda( hipFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda( hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( hipSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( hipMalloc(&d_idata, mem_size) );
checkCuda( hipMalloc(&d_cdata, mem_size) );
checkCuda( hipMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice) );
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( hipEventDestroy(startEvent) );
checkCuda( hipEventDestroy(stopEvent) );
checkCuda( hipFree(d_tdata) );
checkCuda( hipFree(d_cdata) );
checkCuda( hipFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKf
.globl _Z4copyPfPKf
.p2align 8
.type _Z4copyPfPKf,@function
_Z4copyPfPKf:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s15, 5, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v0, v1, s5
s_mov_b32 s5, -8
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPfPKf, .Lfunc_end0-_Z4copyPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13copySharedMemPfPKf
.globl _Z13copySharedMemPfPKf
.p2align 8
.type _Z13copySharedMemPfPKf,@function
_Z13copySharedMemPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_mov_b32 s7, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 5, v2
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v5, v2, 7, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, s4, v1
s_lshl_b32 s6, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v4
v_add3_u32 v0, v3, v1, s5
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s7, s7, 8
s_cmp_gt_u32 s7, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
v_add_nc_u32_e32 v5, 0x400, v5
s_cbranch_scc0 .LBB1_1
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 5, v4
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, v3, v0, s5
v_lshl_add_u32 v2, v2, 7, v1
s_barrier
buffer_gl0_inv
.LBB1_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 0x400, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB1_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copySharedMemPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13copySharedMemPfPKf, .Lfunc_end1-_Z13copySharedMemPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 8
.type _Z14transposeNaivePfPKf,@function
_Z14transposeNaivePfPKf:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s14, 5
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v2
v_mul_lo_u32 v3, s4, v3
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 5, v2
v_lshlrev_b32_e32 v3, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, s6
v_add3_u32 v0, v1, v3, s5
s_mov_b32 s5, -8
.p2align 6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_add_nc_u32_e32 v3, s5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB2_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14transposeNaivePfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14transposeNaivePfPKf, .Lfunc_end2-_Z14transposeNaivePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeCoalescedPfPKf
.globl _Z18transposeCoalescedPfPKf
.p2align 8
.type _Z18transposeCoalescedPfPKf,@function
_Z18transposeCoalescedPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v3
v_lshl_add_u32 v4, v2, 7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s6
.LBB3_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 0x400, v4
s_cbranch_scc0 .LBB3_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v2, v3, 7, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB3_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB3_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeCoalescedPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z18transposeCoalescedPfPKf, .Lfunc_end3-_Z18transposeCoalescedPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24transposeNoBankConflictsPfPKf
.globl _Z24transposeNoBankConflictsPfPKf
.p2align 8
.type _Z24transposeNoBankConflictsPfPKf,@function
_Z24transposeNoBankConflictsPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v4, v2, 0x84, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s6
.LBB4_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 0x420, v4
s_cbranch_scc0 .LBB4_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_mad_u32_u24 v2, v3, 0x84, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB4_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB4_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24transposeNoBankConflictsPfPKf
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z24transposeNoBankConflictsPfPKf, .Lfunc_end4-_Z24transposeNoBankConflictsPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copySharedMemPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copySharedMemPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14transposeNaivePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14transposeNaivePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeCoalescedPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeCoalescedPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24transposeNoBankConflictsPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24transposeNoBankConflictsPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float *ref, const float *res, int n, float ms)
{
bool passed = true;
for (int i = 0; i < n; i++)
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, res[i], ref[i]);
printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms );
}
// simple copy kernel
// Used as reference case representing best effective bandwidth.
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
// copy kernel using shared memory
// Also used as reference case, demonstrating effect of using shared memory.
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
}
// naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
// coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalesced(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
__global__ void transposeNoBankConflicts(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM+1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
int main(int argc, char **argv)
{
const int nx = 1024;
const int ny = 1024;
const int mem_size = nx*ny*sizeof(float);
dim3 dimGrid(nx/TILE_DIM, ny/TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
int devId = 0;
if (argc > 1) devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda( hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda( hipSetDevice(devId) );
float *h_idata = (float*)malloc(mem_size);
float *h_cdata = (float*)malloc(mem_size);
float *h_tdata = (float*)malloc(mem_size);
float *gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda( hipMalloc(&d_idata, mem_size) );
checkCuda( hipMalloc(&d_cdata, mem_size) );
checkCuda( hipMalloc(&d_tdata, mem_size) );
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
h_idata[j*nx + i] = j*nx + i;
// correct result for error checking
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
gold[j*nx + i] = h_idata[i*nx + j];
// device
checkCuda( hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice) );
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
float ms;
// ------------
// time kernels
// ------------
printf("%25s%25s\n", "Routine", "Bandwidth (GB/s)");
// ----
// copy
// ----
printf("%25s", "copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copy<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx*ny, ms);
// -------------
// copySharedMem
// -------------
printf("%25s", "shared memory copy");
checkCuda( hipMemset(d_cdata, 0, mem_size) );
// warm up
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
copySharedMem<<<dimGrid, dimBlock>>>(d_cdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_cdata, d_cdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(h_idata, h_cdata, nx * ny, ms);
// --------------
// transposeNaive
// --------------
printf("%25s", "naive transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNaive<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------
// transposeCoalesced
// ------------------
printf("%25s", "coalesced transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeCoalesced<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
// ------------------------
// transposeNoBankConflicts
// ------------------------
printf("%25s", "conflict-free transpose");
checkCuda( hipMemset(d_tdata, 0, mem_size) );
// warmup
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(startEvent, 0) );
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflicts<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
checkCuda( hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost) );
postprocess(gold, h_tdata, nx * ny, ms);
error_exit:
// cleanup
checkCuda( hipEventDestroy(startEvent) );
checkCuda( hipEventDestroy(stopEvent) );
checkCuda( hipFree(d_tdata) );
checkCuda( hipFree(d_cdata) );
checkCuda( hipFree(d_idata) );
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .text
.file "transpose.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11postprocessPKfS0_if
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI0_3:
.quad 0x4059000000000000 # double 100
.text
.globl _Z11postprocessPKfS0_if
.p2align 4, 0x90
.type _Z11postprocessPKfS0_if,@function
_Z11postprocessPKfS0_if: # @_Z11postprocessPKfS0_if
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rdi,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_5
jp .LBB0_5
# %bb.3: # in Loop: Header=BB0_2 Depth=1
incq %rax
cmpq %rax, %rcx
jne .LBB0_2
.LBB0_4: # %.critedge
addl %edx, %edx
movslq %edx, %rax
shlq $2, %rax
movq %rax, %xmm2
punpckldq .LCPI0_0(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI0_1(%rip), %xmm2
movapd %xmm2, %xmm1
unpckhpd %xmm2, %xmm1 # xmm1 = xmm1[1],xmm2[1]
addsd %xmm2, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm1
movl $.L.str.3, %edi
movapd %xmm1, %xmm0
movb $1, %al
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_5:
.cfi_def_cfa_offset 16
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %eax, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11postprocessPKfS0_if, .Lfunc_end0-_Z11postprocessPKfS0_if
.cfi_endproc
# -- End function
.globl _Z19__device_stub__copyPfPKf # -- Begin function _Z19__device_stub__copyPfPKf
.p2align 4, 0x90
.type _Z19__device_stub__copyPfPKf,@function
_Z19__device_stub__copyPfPKf: # @_Z19__device_stub__copyPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4copyPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__copyPfPKf, .Lfunc_end1-_Z19__device_stub__copyPfPKf
.cfi_endproc
# -- End function
.globl _Z28__device_stub__copySharedMemPfPKf # -- Begin function _Z28__device_stub__copySharedMemPfPKf
.p2align 4, 0x90
.type _Z28__device_stub__copySharedMemPfPKf,@function
_Z28__device_stub__copySharedMemPfPKf: # @_Z28__device_stub__copySharedMemPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13copySharedMemPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__copySharedMemPfPKf, .Lfunc_end2-_Z28__device_stub__copySharedMemPfPKf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__transposeNaivePfPKf # -- Begin function _Z29__device_stub__transposeNaivePfPKf
.p2align 4, 0x90
.type _Z29__device_stub__transposeNaivePfPKf,@function
_Z29__device_stub__transposeNaivePfPKf: # @_Z29__device_stub__transposeNaivePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14transposeNaivePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z29__device_stub__transposeNaivePfPKf, .Lfunc_end3-_Z29__device_stub__transposeNaivePfPKf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__transposeCoalescedPfPKf # -- Begin function _Z33__device_stub__transposeCoalescedPfPKf
.p2align 4, 0x90
.type _Z33__device_stub__transposeCoalescedPfPKf,@function
_Z33__device_stub__transposeCoalescedPfPKf: # @_Z33__device_stub__transposeCoalescedPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18transposeCoalescedPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z33__device_stub__transposeCoalescedPfPKf, .Lfunc_end4-_Z33__device_stub__transposeCoalescedPfPKf
.cfi_endproc
# -- End function
.globl _Z39__device_stub__transposeNoBankConflictsPfPKf # -- Begin function _Z39__device_stub__transposeNoBankConflictsPfPKf
.p2align 4, 0x90
.type _Z39__device_stub__transposeNoBankConflictsPfPKf,@function
_Z39__device_stub__transposeNoBankConflictsPfPKf: # @_Z39__device_stub__transposeNoBankConflictsPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24transposeNoBankConflictsPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z39__device_stub__transposeNoBankConflictsPfPKf, .Lfunc_end5-_Z39__device_stub__transposeNoBankConflictsPfPKf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x408a36e2eb1c432c # double 838.86079999999993
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB6_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB6_2:
leaq 152(%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
xorl %r15d, %r15d
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.5, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $32, %ecx
movl $8, %r8d
movl $32, %r9d
xorl %eax, %eax
pushq $32
.cfi_adjust_cfa_offset 8
callq printf
addq $8, %rsp
.cfi_adjust_cfa_offset -8
movl $.L.str.6, %edi
movl $32, %esi
movl $32, %edx
movl $1, %ecx
movl $32, %r8d
movl $8, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl %ebx, %edi
callq hipSetDevice
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, 144(%rsp) # 8-byte Spill
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 104(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 96(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # %.preheader270
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
movl $1024, %ecx # imm = 0x400
movq %r15, %rdx
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%rdx,4)
incq %rdx
decq %rcx
jne .LBB6_4
# %bb.5: # in Loop: Header=BB6_3 Depth=1
incq %rax
addq $1024, %r15 # imm = 0x400
cmpq $1024, %rax # imm = 0x400
jne .LBB6_3
# %bb.6: # %.preheader.preheader
xorl %eax, %eax
movq %r14, %rcx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB6_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_8 Depth 2
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_8: # Parent Loop BB6_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %rdi # imm = 0x400
jne .LBB6_8
# %bb.9: # in Loop: Header=BB6_7 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4, %rcx
cmpq $1024, %rax # imm = 0x400
jne .LBB6_7
# %bb.10:
movq %r12, 128(%rsp) # 8-byte Spill
movq %rbx, 136(%rsp) # 8-byte Spill
movabsq $137438953504, %rbx # imm = 0x2000000020
movabsq $34359738400, %r15 # imm = 0x800000020
movq 104(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 112(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movl $.L.str.7, %edi
movl $.L.str.8, %esi
movl $.L.str.9, %edx
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq 120(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movq %rbx, %rdi
movl $1, %esi
movq %r15, %r12
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
movq 120(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4copyPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 8(%rsp), %r15
movq %rsp, %r13
leaq 80(%rsp), %rbp
jmp .LBB6_13
.p2align 4, 0x90
.LBB6_15: # in Loop: Header=BB6_13 Depth=1
decl %ebx
je .LBB6_16
.LBB6_13: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_15
# %bb.14: # in Loop: Header=BB6_13 Depth=1
movq 120(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r15, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z4copyPfPKf, %edi
movq %rbp, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_15
.LBB6_16:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movq 120(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 144(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 68(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_17: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB6_18
jp .LBB6_18
# %bb.19: # in Loop: Header=BB6_17 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB6_17
# %bb.20: # %.critedge.i
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB6_21
.LBB6_18:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB6_21: # %_Z11postprocessPKfS0_if.exit
movl $.L.str.10, %edi
movl $.L.str.12, %esi
xorl %eax, %eax
callq printf
movq 120(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_23
# %bb.22:
movq 120(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13copySharedMemPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_23:
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 8(%rsp), %r15
movq %rsp, %r13
leaq 80(%rsp), %rbp
jmp .LBB6_24
.p2align 4, 0x90
.LBB6_26: # in Loop: Header=BB6_24 Depth=1
decl %ebx
je .LBB6_27
.LBB6_24: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_26
# %bb.25: # in Loop: Header=BB6_24 Depth=1
movq 120(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r15, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z13copySharedMemPfPKf, %edi
movq %rbp, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_26
.LBB6_27:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movq 120(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 144(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 68(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_28: # %.lr.ph.i161
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB6_29
jp .LBB6_29
# %bb.30: # in Loop: Header=BB6_28 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB6_28
# %bb.31: # %.critedge.i165
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB6_32
.LBB6_29:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB6_32: # %_Z11postprocessPKfS0_if.exit166
movl $.L.str.10, %edi
movl $.L.str.13, %esi
xorl %eax, %eax
callq printf
movq 96(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_34
# %bb.33:
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14transposeNaivePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_34:
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 8(%rsp), %r15
movq %rsp, %r13
leaq 80(%rsp), %rbp
jmp .LBB6_35
.p2align 4, 0x90
.LBB6_37: # in Loop: Header=BB6_35 Depth=1
decl %ebx
je .LBB6_38
.LBB6_35: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_37
# %bb.36: # in Loop: Header=BB6_35 Depth=1
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r15, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z14transposeNaivePfPKf, %edi
movq %rbp, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_37
.LBB6_38:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 128(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 68(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 136(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB6_39: # %.lr.ph.i179
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB6_40
jp .LBB6_40
# %bb.41: # in Loop: Header=BB6_39 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB6_39
# %bb.42: # %.critedge.i183
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB6_43
.LBB6_40:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB6_43: # %_Z11postprocessPKfS0_if.exit184
movl $.L.str.10, %edi
movl $.L.str.14, %esi
xorl %eax, %eax
callq printf
movq 96(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_45
# %bb.44:
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeCoalescedPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_45:
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 8(%rsp), %r15
movq %rsp, %r13
leaq 80(%rsp), %rbp
jmp .LBB6_46
.p2align 4, 0x90
.LBB6_48: # in Loop: Header=BB6_46 Depth=1
decl %ebx
je .LBB6_49
.LBB6_46: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_48
# %bb.47: # in Loop: Header=BB6_46 Depth=1
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r15, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z18transposeCoalescedPfPKf, %edi
movq %rbp, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_48
.LBB6_49:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 128(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 68(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 136(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB6_50: # %.lr.ph.i197
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB6_51
jp .LBB6_51
# %bb.52: # in Loop: Header=BB6_50 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB6_50
# %bb.53: # %.critedge.i201
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB6_54
.LBB6_51:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB6_54: # %_Z11postprocessPKfS0_if.exit202
movl $.L.str.10, %edi
movl $.L.str.15, %esi
xorl %eax, %eax
callq printf
movq 96(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_56
# %bb.55:
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24transposeNoBankConflictsPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_56:
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 8(%rsp), %r15
movq %rsp, %r13
leaq 80(%rsp), %rbp
jmp .LBB6_57
.p2align 4, 0x90
.LBB6_59: # in Loop: Header=BB6_57 Depth=1
decl %ebx
je .LBB6_60
.LBB6_57: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_59
# %bb.58: # in Loop: Header=BB6_57 Depth=1
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r15, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z24transposeNoBankConflictsPfPKf, %edi
movq %rbp, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_59
.LBB6_60:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 112(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 128(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movss 68(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 144(%rsp), %r15 # 8-byte Reload
movq 136(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB6_61: # %.lr.ph.i215
# =>This Inner Loop Header: Depth=1
movss (%r13,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB6_62
jp .LBB6_62
# %bb.63: # in Loop: Header=BB6_61 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB6_61
# %bb.64: # %.critedge.i219
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB6_65
.LBB6_62:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB6_65: # %_Z11postprocessPKfS0_if.exit220
movq 112(%rsp), %rdi
callq hipEventDestroy
movq 72(%rsp), %rdi
callq hipEventDestroy
movq 96(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13copySharedMemPfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14transposeNaivePfPKf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeCoalescedPfPKf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24transposeNoBankConflictsPfPKf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%25s\n"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*** FAILED ***"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%20.2f\n"
.size .L.str.3, 8
.type _Z4copyPfPKf,@object # @_Z4copyPfPKf
.section .rodata,"a",@progbits
.globl _Z4copyPfPKf
.p2align 3, 0x0
_Z4copyPfPKf:
.quad _Z19__device_stub__copyPfPKf
.size _Z4copyPfPKf, 8
.type _Z13copySharedMemPfPKf,@object # @_Z13copySharedMemPfPKf
.globl _Z13copySharedMemPfPKf
.p2align 3, 0x0
_Z13copySharedMemPfPKf:
.quad _Z28__device_stub__copySharedMemPfPKf
.size _Z13copySharedMemPfPKf, 8
.type _Z14transposeNaivePfPKf,@object # @_Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 3, 0x0
_Z14transposeNaivePfPKf:
.quad _Z29__device_stub__transposeNaivePfPKf
.size _Z14transposeNaivePfPKf, 8
.type _Z18transposeCoalescedPfPKf,@object # @_Z18transposeCoalescedPfPKf
.globl _Z18transposeCoalescedPfPKf
.p2align 3, 0x0
_Z18transposeCoalescedPfPKf:
.quad _Z33__device_stub__transposeCoalescedPfPKf
.size _Z18transposeCoalescedPfPKf, 8
.type _Z24transposeNoBankConflictsPfPKf,@object # @_Z24transposeNoBankConflictsPfPKf
.globl _Z24transposeNoBankConflictsPfPKf
.p2align 3, 0x0
_Z24transposeNoBankConflictsPfPKf:
.quad _Z39__device_stub__transposeNoBankConflictsPfPKf
.size _Z24transposeNoBankConflictsPfPKf, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "\nDevice : %s\n"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n"
.size .L.str.5, 57
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "dimGrid: %d %d %d. dimBlock: %d %d %d\n"
.size .L.str.6, 39
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%25s%25s\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Routine"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Bandwidth (GB/s)"
.size .L.str.9, 17
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%25s"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "copy"
.size .L.str.11, 5
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "shared memory copy"
.size .L.str.12, 19
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "naive transpose"
.size .L.str.13, 16
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "coalesced transpose"
.size .L.str.14, 20
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "conflict-free transpose"
.size .L.str.15, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4copyPfPKf"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13copySharedMemPfPKf"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14transposeNaivePfPKf"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18transposeCoalescedPfPKf"
.size .L__unnamed_4, 28
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z24transposeNoBankConflictsPfPKf"
.size .L__unnamed_5, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPfPKf
.addrsig_sym _Z28__device_stub__copySharedMemPfPKf
.addrsig_sym _Z29__device_stub__transposeNaivePfPKf
.addrsig_sym _Z33__device_stub__transposeCoalescedPfPKf
.addrsig_sym _Z39__device_stub__transposeNoBankConflictsPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPfPKf
.addrsig_sym _Z13copySharedMemPfPKf
.addrsig_sym _Z14transposeNaivePfPKf
.addrsig_sym _Z18transposeCoalescedPfPKf
.addrsig_sym _Z24transposeNoBankConflictsPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} | code for sm_80
Function : histogram_optimized
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fca0000011400 */
/*0080*/ @!P1 STS [R4.X4], RZ ; /* 0x000000ff04009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00a0*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*00b0*/ @P0 BRA 0x1a0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0000 */
/*00e0*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x001fc80007f1e0ff */
/*00f0*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590006037a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0130*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x000fc800078e0200 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, R5.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0005 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011405 */
/*0170*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x16c], PT, P0 ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06300 */
/*0180*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0190*/ @!P0 BRA 0xe0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fca00078e0003 */
/*0200*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : histogram
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0090*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f0eff */
/*00b0*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fd20000000f00 */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e0003 */
/*00f0*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e184 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} | .file "tmpxft_000214d6_00000000-6_07-histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9histogramPhPiPhPi
.type _Z30__device_stub__Z9histogramPhPiPhPi, @function
_Z30__device_stub__Z9histogramPhPiPhPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq histogram(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9histogramPhPiPhPi, .-_Z30__device_stub__Z9histogramPhPiPhPi
.globl histogram
.type histogram, @function
histogram:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9histogramPhPiPhPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size histogram, .-histogram
.globl _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
.type _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj, @function
_Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq histogram_optimized(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj, .-_Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
.globl histogram_optimized
.type histogram_optimized, @function
histogram_optimized:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size histogram_optimized, .-histogram_optimized
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "histogram_optimized"
.LC1:
.string "histogram"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq histogram_optimized(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq histogram(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} | #include <hip/hip_runtime.h>
extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected histogram
.globl histogram
.p2align 8
.type histogram,@function
histogram:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_lshr_b32 s6, s5, 16
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
s_and_b32 s4, s5, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v3
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel histogram
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size histogram, .Lfunc_end0-histogram
.section .AMDGPU.csdata,"",@progbits
.text
.protected histogram_optimized
.globl histogram_optimized
.p2align 8
.type histogram_optimized,@function
histogram_optimized:
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s6, s0, 24
s_addc_u32 s7, s1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s8, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_5
s_load_b32 s2, s[6:7], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v5, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
s_mul_i32 s8, s2, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_co_u32 v3, s2, v3, s8
v_subrev_co_ci_u32_e64 v4, s2, s9, v4, s2
.p2align 6
.LBB1_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, v3, s8
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
global_load_u8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e64 s2, s[4:5], v[3:4]
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s10, s2, s10
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
ds_add_u32 v1, v5
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB1_4
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel histogram_optimized
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size histogram_optimized, .Lfunc_end1-histogram_optimized
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: histogram
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: histogram.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: histogram_optimized
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: histogram_optimized.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
//灰度直方图统计
__global__ void histogram(unsigned char *dataIn, int *hist)
{
int threadIndex = threadIdx.x + threadIdx.y * blockDim.x;
int blockIndex = blockIdx.x + blockIdx.y * gridDim.x;
int index = threadIndex + blockIndex * blockDim.x * blockDim.y;
atomicAdd(&hist[dataIn[index]], 1);
}
//灰度图像直方图（优化）
__global__ void histogram_optimized(unsigned char *buffer, long size, unsigned int *histo){
__shared__ unsigned int private_histo[256];
if(threadIdx.x < 256) //初始化shared histo
private_histo[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
// 步长是所有threads的数目
int stride = blockDim.x * gridDim.x;
while(i < size) {
atomicAdd(&(private_histo[buffer[i]]), 1);
i += stride;
}
//等待所有线程执行完
__syncthreads();
if(threadIdx.x < 256){
atomicAdd(&(histo[threadIdx.x]), private_histo[threadIdx.x]);
}
}
} | .text
.file "07-histogram.hip"
.globl __device_stub__histogram # -- Begin function __device_stub__histogram
.p2align 4, 0x90
.type __device_stub__histogram,@function
__device_stub__histogram: # @__device_stub__histogram
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $histogram, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__histogram, .Lfunc_end0-__device_stub__histogram
.cfi_endproc
# -- End function
.globl __device_stub__histogram_optimized # -- Begin function __device_stub__histogram_optimized
.p2align 4, 0x90
.type __device_stub__histogram_optimized,@function
__device_stub__histogram_optimized: # @__device_stub__histogram_optimized
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $histogram_optimized, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__histogram_optimized, .Lfunc_end1-__device_stub__histogram_optimized
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $histogram, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $histogram_optimized, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type histogram,@object # @histogram
.section .rodata,"a",@progbits
.globl histogram
.p2align 3, 0x0
histogram:
.quad __device_stub__histogram
.size histogram, 8
.type histogram_optimized,@object # @histogram_optimized
.globl histogram_optimized
.p2align 3, 0x0
histogram_optimized:
.quad __device_stub__histogram_optimized
.size histogram_optimized, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "histogram"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "histogram_optimized"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__histogram
.addrsig_sym __device_stub__histogram_optimized
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym histogram
.addrsig_sym histogram_optimized
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : histogram_optimized
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fca0000011400 */
/*0080*/ @!P1 STS [R4.X4], RZ ; /* 0x000000ff04009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00a0*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*00b0*/ @P0 BRA 0x1a0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0000 */
/*00e0*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x001fc80007f1e0ff */
/*00f0*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590006037a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0130*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x000fc800078e0200 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, R5.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0005 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011405 */
/*0170*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x16c], PT, P0 ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06300 */
/*0180*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0190*/ @!P0 BRA 0xe0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fca00078e0003 */
/*0200*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : histogram
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0090*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f0eff */
/*00b0*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fd20000000f00 */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e0003 */
/*00f0*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e184 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected histogram
.globl histogram
.p2align 8
.type histogram,@function
histogram:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_lshr_b32 s6, s5, 16
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
s_and_b32 s4, s5, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v3
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel histogram
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size histogram, .Lfunc_end0-histogram
.section .AMDGPU.csdata,"",@progbits
.text
.protected histogram_optimized
.globl histogram_optimized
.p2align 8
.type histogram_optimized,@function
histogram_optimized:
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s6, s0, 24
s_addc_u32 s7, s1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s8, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_5
s_load_b32 s2, s[6:7], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v5, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
s_mul_i32 s8, s2, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_co_u32 v3, s2, v3, s8
v_subrev_co_ci_u32_e64 v4, s2, s9, v4, s2
.p2align 6
.LBB1_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, v3, s8
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
global_load_u8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e64 s2, s[4:5], v[3:4]
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s10, s2, s10
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
ds_add_u32 v1, v5
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB1_4
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel histogram_optimized
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size histogram_optimized, .Lfunc_end1-histogram_optimized
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: histogram
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: histogram.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: histogram_optimized
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: histogram_optimized.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000214d6_00000000-6_07-histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9histogramPhPiPhPi
.type _Z30__device_stub__Z9histogramPhPiPhPi, @function
_Z30__device_stub__Z9histogramPhPiPhPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq histogram(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9histogramPhPiPhPi, .-_Z30__device_stub__Z9histogramPhPiPhPi
.globl histogram
.type histogram, @function
histogram:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9histogramPhPiPhPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size histogram, .-histogram
.globl _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
.type _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj, @function
_Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq histogram_optimized(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj, .-_Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
.globl histogram_optimized
.type histogram_optimized, @function
histogram_optimized:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19histogram_optimizedPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size histogram_optimized, .-histogram_optimized
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "histogram_optimized"
.LC1:
.string "histogram"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq histogram_optimized(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq histogram(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "07-histogram.hip"
.globl __device_stub__histogram # -- Begin function __device_stub__histogram
.p2align 4, 0x90
.type __device_stub__histogram,@function
__device_stub__histogram: # @__device_stub__histogram
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $histogram, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__histogram, .Lfunc_end0-__device_stub__histogram
.cfi_endproc
# -- End function
.globl __device_stub__histogram_optimized # -- Begin function __device_stub__histogram_optimized
.p2align 4, 0x90
.type __device_stub__histogram_optimized,@function
__device_stub__histogram_optimized: # @__device_stub__histogram_optimized
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $histogram_optimized, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__histogram_optimized, .Lfunc_end1-__device_stub__histogram_optimized
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $histogram, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $histogram_optimized, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type histogram,@object # @histogram
.section .rodata,"a",@progbits
.globl histogram
.p2align 3, 0x0
histogram:
.quad __device_stub__histogram
.size histogram, 8
.type histogram_optimized,@object # @histogram_optimized
.globl histogram_optimized
.p2align 3, 0x0
histogram_optimized:
.quad __device_stub__histogram_optimized
.size histogram_optimized, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "histogram"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "histogram_optimized"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__histogram
.addrsig_sym __device_stub__histogram_optimized
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym histogram
.addrsig_sym histogram_optimized
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <iomanip>
#include <fstream>
#include <cmath>
#define INFINITE 1000000000
int* distance_host;
int* distance_dev;
__global__ void FW1(int *distance_dev, int r, int vertexPadded){
int i = r * blockDim.x + threadIdx.y;
int j = r * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
extern __shared__ int dist[];
dist[threadIdx.y * blockDim.x + threadIdx.x] = distance_dev[ offset + j ];
__syncthreads();
for(int k=0; k<blockDim.x; ++k){
dist[ threadIdx.y * blockDim.x + threadIdx.x ] = min(dist[ threadIdx.y * blockDim.x + threadIdx.x ], dist[ threadIdx.y * blockDim.x + k ] + dist[ k * blockDim.x + threadIdx.x ]);
__syncthreads();
}
distance_dev[ offset + j ] = dist[threadIdx.y * blockDim.x + threadIdx.x];
}
__global__ void FW2(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i, block_j;
if(blockIdx.y == 0){
block_i = r;
block_j = (blockIdx.x + r + 1) % total_round;
}else{
block_j = r;
block_i = (blockIdx.x + r + 1) % total_round;
}
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j];
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x];
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ];
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
__global__ void FW3(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i = (r + blockIdx.y + 1) % total_round;
int block_j = (r + blockIdx.x + 1) % total_round;
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j]; //block(i,j)
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x]; //block(i,r)
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ]; //block(r,j)
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
void block_FW(int blockSize, int vertexNum, int vertexPadded) {
int round = vertexPadded / blockSize;
dim3 block(blockSize, blockSize);
dim3 grid2(round-1, 2);
dim3 grid3(round-1, round-1);
cudaMalloc(&distance_dev, sizeof(int) * vertexPadded * vertexPadded);
cudaMemcpy(distance_dev, distance_host, sizeof(int) * vertexPadded * vertexPadded, cudaMemcpyHostToDevice);
for (int r = 0; r < round; ++r) {
FW1<<< 1, block, blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded);
FW2<<< grid2, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
FW3<<< grid3, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
}
cudaMemcpy(distance_host, distance_dev, sizeof(int) * vertexPadded * vertexPadded, cudaMemcpyDeviceToHost);
}
int main(int argc, char **argv){
//get number of threads per block
cudaSetDevice(0);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
int ThreadsPerBlock = (int) sqrt(prop.maxThreadsPerBlock);
int blockSize = ThreadsPerBlock;
//read input file
std::ifstream inputFile(argv[1], std::ios::in | std::ios::binary);
unsigned vertexNum, edgeNum;
inputFile.read((char*)&vertexNum, 4);
inputFile.read((char*)&edgeNum, 4);
//calculate block number, vertex number in a block
if(vertexNum < blockSize) blockSize = vertexNum;
int blockNum = ceil( 1.0 * vertexNum / blockSize);
int vertexPadded = blockSize * blockNum;
//Allocate memory (pinned)
cudaMallocHost(&distance_host, sizeof(int) * vertexPadded * vertexPadded);
for(unsigned i=0; i<vertexPadded; ++i){
for(unsigned j=0; j<vertexPadded; ++j){
if( i>=vertexNum || j>=vertexNum) distance_host[ i * vertexPadded + j ] = INFINITE;
else if( i == j) distance_host[ i * vertexPadded + j ] = 0;
else distance_host[ i * vertexPadded + j ] = INFINITE;
}
}
int source, destination, weight;
while( inputFile.read((char*)&source, 4) ){
inputFile.read((char*)&destination, 4);
inputFile.read((char*)&weight, 4);
distance_host[ source * vertexPadded + destination ] = weight;
}
inputFile.close();
block_FW(blockSize, vertexNum, vertexPadded);
//write answer to output file
std::ofstream outputFile(argv[2], std::ios::out | std::ios::binary);
for(int i=0; i<vertexNum; ++i){
for(int j=0; j<vertexNum; ++j){
outputFile.write( (char*)&distance_host[ i * vertexPadded + j ], 4);
}
}
outputFile.close();
cudaFree(distance_host);
cudaFree(distance_dev);
return 0;
} | .file "tmpxft_0005f881_00000000-6_apsp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3FW1PiiiPiii
.type _Z24__device_stub__Z3FW1PiiiPiii, @function
_Z24__device_stub__Z3FW1PiiiPiii:
.LFB4065:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3FW1Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z24__device_stub__Z3FW1PiiiPiii, .-_Z24__device_stub__Z3FW1PiiiPiii
.globl _Z3FW1Piii
.type _Z3FW1Piii, @function
_Z3FW1Piii:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3FW1PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z3FW1Piii, .-_Z3FW1Piii
.globl _Z25__device_stub__Z3FW2PiiiiPiiii
.type _Z25__device_stub__Z3FW2PiiiiPiiii, @function
_Z25__device_stub__Z3FW2PiiiiPiiii:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3FW2Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z25__device_stub__Z3FW2PiiiiPiiii, .-_Z25__device_stub__Z3FW2PiiiiPiiii
.globl _Z3FW2Piiii
.type _Z3FW2Piiii, @function
_Z3FW2Piiii:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3FW2PiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z3FW2Piiii, .-_Z3FW2Piiii
.globl _Z25__device_stub__Z3FW3PiiiiPiiii
.type _Z25__device_stub__Z3FW3PiiiiPiiii, @function
_Z25__device_stub__Z3FW3PiiiiPiiii:
.LFB4069:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3FW3Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4069:
.size _Z25__device_stub__Z3FW3PiiiiPiiii, .-_Z25__device_stub__Z3FW3PiiiiPiiii
.globl _Z3FW3Piiii
.type _Z3FW3Piiii, @function
_Z3FW3Piiii:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3FW3PiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _Z3FW3Piiii, .-_Z3FW3Piiii
.globl _Z8block_FWiii
.type _Z8block_FWiii, @function
_Z8block_FWiii:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %edx, %r13d
movl %edx, %eax
cltd
idivl %edi
movl %eax, %r12d
movl %edi, (%rsp)
movl %edi, 4(%rsp)
movl $1, 8(%rsp)
leal -1(%rax), %eax
movl %eax, 12(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movslq %r13d, %r15
imulq %r15, %r15
salq $2, %r15
movq %r15, %rsi
leaq distance_dev(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq distance_host(%rip), %rsi
movq distance_dev(%rip), %rdi
call cudaMemcpy@PLT
testl %r12d, %r12d
jle .L28
imull %ebx, %ebx
movslq %ebx, %r14
salq $2, %r14
leal (%rbx,%rbx,2), %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl $0, %ebx
jmp .L32
.L35:
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z24__device_stub__Z3FW1PiiiPiii
jmp .L29
.L36:
movl %r12d, %ecx
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z25__device_stub__Z3FW2PiiiiPiiii
jmp .L30
.L31:
addl $1, %ebx
cmpl %ebx, %r12d
je .L28
.L32:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 8(%rsp), %ecx
movl $0, %r9d
movq %r14, %r8
movq (%rsp), %rdx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movl 8(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq (%rsp), %rdx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
movl 8(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq (%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl %r12d, %ecx
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z25__device_stub__Z3FW3PiiiiPiiii
jmp .L31
.L28:
movl $2, %ecx
movq %r15, %rdx
movq distance_dev(%rip), %rsi
movq distance_host(%rip), %rdi
call cudaMemcpy@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _Z8block_FWiii, .-_Z8block_FWiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3FW3Piiii"
.LC1:
.string "_Z3FW2Piiii"
.LC2:
.string "_Z3FW1Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW3Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW2Piiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW1Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4072:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.globl main
.type main, @function
main:
.LFB4040:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4040
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2120, %rsp
.cfi_def_cfa_offset 2176
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call cudaSetDevice@PLT
leaq 1072(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 1392(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L70
sqrtsd %xmm0, %xmm0
.L42:
cvttsd2sil %xmm0, %r12d
movq 8(%r13), %rsi
leaq 544(%rsp), %rbx
movl $12, %edx
movq %rbx, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 12(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSi4readEPcl@PLT
jmp .L73
.L70:
call sqrt@PLT
jmp .L42
.L73:
leaq 16(%rsp), %rsi
movq %rbx, %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
movl 12(%rsp), %eax
cmpl %eax, %r12d
cmova %eax, %r12d
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L46
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L46:
cvttsd2sil %xmm3, %ebx
imull %r12d, %ebx
movslq %ebx, %r15
movq %r15, %rsi
imulq %r15, %rsi
salq $2, %rsi
movl $0, %edx
leaq distance_host(%rip), %rdi
call cudaHostAlloc@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
testl %ebx, %ebx
jne .L47
.L48:
leaq 20(%rsp), %r14
jmp .L53
.L49:
cmpl %eax, %ecx
je .L74
leal (%rax,%r8), %edx
movq distance_host(%rip), %rdi
movl $1000000000, (%rdi,%rdx,4)
.L50:
addl $1, %eax
addl $1, %esi
cmpl %ebx, %eax
je .L75
.L52:
cmpl %eax, %ecx
movl %eax, %edx
cmovnb %ecx, %edx
cmpl 12(%rsp), %edx
jb .L49
leal (%rax,%r8), %edx
movq distance_host(%rip), %rdi
movl $1000000000, (%rdi,%rdx,4)
jmp .L50
.L74:
movl %esi, %edx
movq distance_host(%rip), %rdi
movl $0, (%rdi,%rdx,4)
jmp .L50
.L75:
addl $1, %ecx
addl %ebx, %r8d
addl %ebx, %r9d
cmpl %ebx, %ecx
je .L48
.L47:
movl %r9d, %esi
movl $0, %eax
jmp .L52
.L77:
leaq 28(%rsp), %rsi
leaq 544(%rsp), %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
movl %ebx, %eax
imull 20(%rsp), %eax
addl 24(%rsp), %eax
cltq
movl 28(%rsp), %ecx
movq distance_host(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
.L53:
leaq 544(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
call _ZNSi4readEPcl@PLT
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L76
leaq 24(%rsp), %rsi
leaq 544(%rsp), %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
jmp .L77
.L76:
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
movl %ebx, %edx
movl 12(%rsp), %esi
movl %r12d, %edi
call _Z8block_FWiii
movq 16(%r13), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
cmpl $0, 12(%rsp)
je .L55
salq $2, %r15
movl $0, %r13d
movl $0, %r14d
leaq 32(%rsp), %r12
jmp .L56
.L79:
addl $1, %ebx
movl 12(%rsp), %eax
addq $4, %rbp
cmpl %eax, %ebx
jnb .L78
.L57:
movq %rbp, %rsi
addq distance_host(%rip), %rsi
movl $4, %edx
movq %r12, %rdi
.LEHB2:
call _ZNSo5writeEPKcl@PLT
jmp .L79
.L78:
addl $1, %r14d
addq %r15, %r13
cmpl %eax, %r14d
jnb .L55
.L56:
cmpl $0, 12(%rsp)
je .L55
movq %r13, %rbp
movl $0, %ebx
jmp .L57
.L55:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq distance_host(%rip), %rdi
call cudaFree@PLT
movq distance_dev(%rip), %rdi
call cudaFree@PLT
.LEHE2:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L59:
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
je .L60
call __stack_chk_fail@PLT
.L64:
endbr64
movq %rax, %rbx
jmp .L59
.L60:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4040:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4040:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4040-.LLSDACSB4040
.LLSDACSB4040:
.uleb128 .LEHB0-.LFB4040
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4040
.uleb128 .LEHE1-.LEHB1
.uleb128 .L64-.LFB4040
.uleb128 0
.uleb128 .LEHB2-.LFB4040
.uleb128 .LEHE2-.LEHB2
.uleb128 .L65-.LFB4040
.uleb128 0
.uleb128 .LEHB3-.LFB4040
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4040:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl distance_dev
.bss
.align 8
.type distance_dev, @object
.size distance_dev, 8
distance_dev:
.zero 8
.globl distance_host
.align 8
.type distance_host, @object
.size distance_host, 8
distance_host:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <iomanip>
#include <fstream>
#include <cmath>
#define INFINITE 1000000000
int* distance_host;
int* distance_dev;
__global__ void FW1(int *distance_dev, int r, int vertexPadded){
int i = r * blockDim.x + threadIdx.y;
int j = r * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
extern __shared__ int dist[];
dist[threadIdx.y * blockDim.x + threadIdx.x] = distance_dev[ offset + j ];
__syncthreads();
for(int k=0; k<blockDim.x; ++k){
dist[ threadIdx.y * blockDim.x + threadIdx.x ] = min(dist[ threadIdx.y * blockDim.x + threadIdx.x ], dist[ threadIdx.y * blockDim.x + k ] + dist[ k * blockDim.x + threadIdx.x ]);
__syncthreads();
}
distance_dev[ offset + j ] = dist[threadIdx.y * blockDim.x + threadIdx.x];
}
__global__ void FW2(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i, block_j;
if(blockIdx.y == 0){
block_i = r;
block_j = (blockIdx.x + r + 1) % total_round;
}else{
block_j = r;
block_i = (blockIdx.x + r + 1) % total_round;
}
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j];
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x];
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ];
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
__global__ void FW3(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i = (r + blockIdx.y + 1) % total_round;
int block_j = (r + blockIdx.x + 1) % total_round;
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j]; //block(i,j)
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x]; //block(i,r)
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ]; //block(r,j)
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
void block_FW(int blockSize, int vertexNum, int vertexPadded) {
int round = vertexPadded / blockSize;
dim3 block(blockSize, blockSize);
dim3 grid2(round-1, 2);
dim3 grid3(round-1, round-1);
cudaMalloc(&distance_dev, sizeof(int) * vertexPadded * vertexPadded);
cudaMemcpy(distance_dev, distance_host, sizeof(int) * vertexPadded * vertexPadded, cudaMemcpyHostToDevice);
for (int r = 0; r < round; ++r) {
FW1<<< 1, block, blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded);
FW2<<< grid2, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
FW3<<< grid3, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
}
cudaMemcpy(distance_host, distance_dev, sizeof(int) * vertexPadded * vertexPadded, cudaMemcpyDeviceToHost);
}
int main(int argc, char **argv){
//get number of threads per block
cudaSetDevice(0);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
int ThreadsPerBlock = (int) sqrt(prop.maxThreadsPerBlock);
int blockSize = ThreadsPerBlock;
//read input file
std::ifstream inputFile(argv[1], std::ios::in | std::ios::binary);
unsigned vertexNum, edgeNum;
inputFile.read((char*)&vertexNum, 4);
inputFile.read((char*)&edgeNum, 4);
//calculate block number, vertex number in a block
if(vertexNum < blockSize) blockSize = vertexNum;
int blockNum = ceil( 1.0 * vertexNum / blockSize);
int vertexPadded = blockSize * blockNum;
//Allocate memory (pinned)
cudaMallocHost(&distance_host, sizeof(int) * vertexPadded * vertexPadded);
for(unsigned i=0; i<vertexPadded; ++i){
for(unsigned j=0; j<vertexPadded; ++j){
if( i>=vertexNum || j>=vertexNum) distance_host[ i * vertexPadded + j ] = INFINITE;
else if( i == j) distance_host[ i * vertexPadded + j ] = 0;
else distance_host[ i * vertexPadded + j ] = INFINITE;
}
}
int source, destination, weight;
while( inputFile.read((char*)&source, 4) ){
inputFile.read((char*)&destination, 4);
inputFile.read((char*)&weight, 4);
distance_host[ source * vertexPadded + destination ] = weight;
}
inputFile.close();
block_FW(blockSize, vertexNum, vertexPadded);
//write answer to output file
std::ofstream outputFile(argv[2], std::ios::out | std::ios::binary);
for(int i=0; i<vertexNum; ++i){
for(int j=0; j<vertexNum; ++j){
outputFile.write( (char*)&distance_host[ i * vertexPadded + j ], 4);
}
}
outputFile.close();
cudaFree(distance_host);
cudaFree(distance_dev);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <fstream>
#include <cmath>
#define INFINITE 1000000000
int* distance_host;
int* distance_dev;
__global__ void FW1(int *distance_dev, int r, int vertexPadded){
int i = r * blockDim.x + threadIdx.y;
int j = r * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
extern __shared__ int dist[];
dist[threadIdx.y * blockDim.x + threadIdx.x] = distance_dev[ offset + j ];
__syncthreads();
for(int k=0; k<blockDim.x; ++k){
dist[ threadIdx.y * blockDim.x + threadIdx.x ] = min(dist[ threadIdx.y * blockDim.x + threadIdx.x ], dist[ threadIdx.y * blockDim.x + k ] + dist[ k * blockDim.x + threadIdx.x ]);
__syncthreads();
}
distance_dev[ offset + j ] = dist[threadIdx.y * blockDim.x + threadIdx.x];
}
__global__ void FW2(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i, block_j;
if(blockIdx.y == 0){
block_i = r;
block_j = (blockIdx.x + r + 1) % total_round;
}else{
block_j = r;
block_i = (blockIdx.x + r + 1) % total_round;
}
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j];
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x];
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ];
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
__global__ void FW3(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i = (r + blockIdx.y + 1) % total_round;
int block_j = (r + blockIdx.x + 1) % total_round;
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j]; //block(i,j)
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x]; //block(i,r)
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ]; //block(r,j)
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
void block_FW(int blockSize, int vertexNum, int vertexPadded) {
int round = vertexPadded / blockSize;
dim3 block(blockSize, blockSize);
dim3 grid2(round-1, 2);
dim3 grid3(round-1, round-1);
hipMalloc(&distance_dev, sizeof(int) * vertexPadded * vertexPadded);
hipMemcpy(distance_dev, distance_host, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyHostToDevice);
for (int r = 0; r < round; ++r) {
FW1<<< 1, block, blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded);
FW2<<< grid2, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
FW3<<< grid3, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
}
hipMemcpy(distance_host, distance_dev, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyDeviceToHost);
}
int main(int argc, char **argv){
//get number of threads per block
hipSetDevice(0);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
int ThreadsPerBlock = (int) sqrt(prop.maxThreadsPerBlock);
int blockSize = ThreadsPerBlock;
//read input file
std::ifstream inputFile(argv[1], std::ios::in | std::ios::binary);
unsigned vertexNum, edgeNum;
inputFile.read((char*)&vertexNum, 4);
inputFile.read((char*)&edgeNum, 4);
//calculate block number, vertex number in a block
if(vertexNum < blockSize) blockSize = vertexNum;
int blockNum = ceil( 1.0 * vertexNum / blockSize);
int vertexPadded = blockSize * blockNum;
//Allocate memory (pinned)
hipHostMalloc(&distance_host, sizeof(int) * vertexPadded * vertexPadded, hipHostMallocDefault);
for(unsigned i=0; i<vertexPadded; ++i){
for(unsigned j=0; j<vertexPadded; ++j){
if( i>=vertexNum || j>=vertexNum) distance_host[ i * vertexPadded + j ] = INFINITE;
else if( i == j) distance_host[ i * vertexPadded + j ] = 0;
else distance_host[ i * vertexPadded + j ] = INFINITE;
}
}
int source, destination, weight;
while( inputFile.read((char*)&source, 4) ){
inputFile.read((char*)&destination, 4);
inputFile.read((char*)&weight, 4);
distance_host[ source * vertexPadded + destination ] = weight;
}
inputFile.close();
block_FW(blockSize, vertexNum, vertexPadded);
//write answer to output file
std::ofstream outputFile(argv[2], std::ios::out | std::ios::binary);
for(int i=0; i<vertexNum; ++i){
for(int j=0; j<vertexNum; ++j){
outputFile.write( (char*)&distance_host[ i * vertexPadded + j ], 4);
}
}
outputFile.close();
hipFree(distance_host);
hipFree(distance_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <fstream>
#include <cmath>
#define INFINITE 1000000000
int* distance_host;
int* distance_dev;
__global__ void FW1(int *distance_dev, int r, int vertexPadded){
int i = r * blockDim.x + threadIdx.y;
int j = r * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
extern __shared__ int dist[];
dist[threadIdx.y * blockDim.x + threadIdx.x] = distance_dev[ offset + j ];
__syncthreads();
for(int k=0; k<blockDim.x; ++k){
dist[ threadIdx.y * blockDim.x + threadIdx.x ] = min(dist[ threadIdx.y * blockDim.x + threadIdx.x ], dist[ threadIdx.y * blockDim.x + k ] + dist[ k * blockDim.x + threadIdx.x ]);
__syncthreads();
}
distance_dev[ offset + j ] = dist[threadIdx.y * blockDim.x + threadIdx.x];
}
__global__ void FW2(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i, block_j;
if(blockIdx.y == 0){
block_i = r;
block_j = (blockIdx.x + r + 1) % total_round;
}else{
block_j = r;
block_i = (blockIdx.x + r + 1) % total_round;
}
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j];
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x];
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ];
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
__global__ void FW3(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i = (r + blockIdx.y + 1) % total_round;
int block_j = (r + blockIdx.x + 1) % total_round;
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j]; //block(i,j)
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x]; //block(i,r)
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ]; //block(r,j)
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
void block_FW(int blockSize, int vertexNum, int vertexPadded) {
int round = vertexPadded / blockSize;
dim3 block(blockSize, blockSize);
dim3 grid2(round-1, 2);
dim3 grid3(round-1, round-1);
hipMalloc(&distance_dev, sizeof(int) * vertexPadded * vertexPadded);
hipMemcpy(distance_dev, distance_host, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyHostToDevice);
for (int r = 0; r < round; ++r) {
FW1<<< 1, block, blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded);
FW2<<< grid2, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
FW3<<< grid3, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
}
hipMemcpy(distance_host, distance_dev, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyDeviceToHost);
}
int main(int argc, char **argv){
//get number of threads per block
hipSetDevice(0);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
int ThreadsPerBlock = (int) sqrt(prop.maxThreadsPerBlock);
int blockSize = ThreadsPerBlock;
//read input file
std::ifstream inputFile(argv[1], std::ios::in | std::ios::binary);
unsigned vertexNum, edgeNum;
inputFile.read((char*)&vertexNum, 4);
inputFile.read((char*)&edgeNum, 4);
//calculate block number, vertex number in a block
if(vertexNum < blockSize) blockSize = vertexNum;
int blockNum = ceil( 1.0 * vertexNum / blockSize);
int vertexPadded = blockSize * blockNum;
//Allocate memory (pinned)
hipHostMalloc(&distance_host, sizeof(int) * vertexPadded * vertexPadded, hipHostMallocDefault);
for(unsigned i=0; i<vertexPadded; ++i){
for(unsigned j=0; j<vertexPadded; ++j){
if( i>=vertexNum || j>=vertexNum) distance_host[ i * vertexPadded + j ] = INFINITE;
else if( i == j) distance_host[ i * vertexPadded + j ] = 0;
else distance_host[ i * vertexPadded + j ] = INFINITE;
}
}
int source, destination, weight;
while( inputFile.read((char*)&source, 4) ){
inputFile.read((char*)&destination, 4);
inputFile.read((char*)&weight, 4);
distance_host[ source * vertexPadded + destination ] = weight;
}
inputFile.close();
block_FW(blockSize, vertexNum, vertexPadded);
//write answer to output file
std::ofstream outputFile(argv[2], std::ios::out | std::ios::binary);
for(int i=0; i<vertexNum; ++i){
for(int j=0; j<vertexNum; ++j){
outputFile.write( (char*)&distance_host[ i * vertexPadded + j ], 4);
}
}
outputFile.close();
hipFree(distance_host);
hipFree(distance_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3FW1Piii
.globl _Z3FW1Piii
.p2align 8
.type _Z3FW1Piii,@function
_Z3FW1Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s0, s1, s6
v_mad_u32_u24 v2, v3, s1, v4
v_add_nc_u32_e32 v1, s0, v3
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 2, 0
v_mul_lo_u32 v1, v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s0, v4, v1
s_mov_b32 s0, 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
v_mul_u32_u24_e32 v5, s1, v3
v_lshl_add_u32 v3, v4, 2, 0
s_lshl_b32 s1, s1, 2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v5, 2, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, s0, v4
s_add_i32 s0, s0, 4
ds_load_b32 v6, v3
ds_load_b32 v7, v2
ds_load_b32 v5, v5
v_add_nc_u32_e32 v3, s1, v3
s_cmp_eq_u32 s1, s0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v5, v7, v5
ds_store_b32 v2, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_3:
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3FW1Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3FW1Piii, .Lfunc_end0-_Z3FW1Piii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3FW2Piiii
.globl _Z3FW2Piiii
.p2align 8
.type _Z3FW2Piiii,@function
_Z3FW2Piiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s7, 0, s4
s_add_i32 s8, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s8, s8, 1
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s6, v1
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
s_sub_i32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s7, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s7, s6
s_sub_i32 s7, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s4, s7, s6
s_cmp_eq_u32 s15, 0
s_cselect_b32 s6, s4, s2
s_cselect_b32 s7, s2, s4
s_and_b32 s4, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s7, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_mul_i32 s2, s4, s2
s_cmp_eq_u32 s4, 0
v_add_nc_u32_e32 v7, s2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s3
v_mad_u64_u32 v[5:6], null, v7, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v7, v2, v3
v_add3_u32 v3, s2, v0, v2
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[8:9], off
global_load_b32 v5, v[4:5], off
v_mad_u32_u24 v4, v1, s4, v0
s_mul_i32 s1, s4, s4
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, s1, v4
v_lshl_add_u32 v9, s1, 1, v4
v_lshl_add_u32 v4, v4, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v9, v9, 2, 0
s_waitcnt vmcnt(2)
ds_store_b32 v4, v6
s_waitcnt vmcnt(1)
ds_store_b32 v8, v7
s_waitcnt vmcnt(0)
ds_store_b32 v9, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_3
v_mul_u32_u24_e32 v1, s4, v1
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, s1, v1
s_lshl_b32 s1, s1, 3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, 0, s1, v0
s_lshl_b32 s1, s4, 2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, v1, 2, 0
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, s0, v1
s_add_i32 s0, s0, 4
ds_load_b32 v6, v0
ds_load_b32 v7, v4
ds_load_b32 v5, v5
v_add_nc_u32_e32 v0, s1, v0
s_cmp_eq_u32 s1, s0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v5, v7, v5
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
.LBB1_3:
ds_load_b32 v0, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3FW2Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3FW2Piiii, .Lfunc_end1-_Z3FW2Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3FW3Piiii
.globl _Z3FW3Piiii
.p2align 8
.type _Z3FW3Piiii,@function
_Z3FW3Piiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s7, 0, s4
s_add_i32 s8, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s9, s8, s15
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s6, v1
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s7, s9, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s4
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s9, s7, s4
s_cmp_ge_u32 s7, s4
s_cselect_b32 s7, s9, s7
s_sub_i32 s9, s7, s4
s_cmp_ge_u32 s7, s4
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s8, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s8, s6
s_mul_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s6, s8, s6
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_and_b32 s4, s5, 0xffff
v_mad_u64_u32 v[2:3], null, s7, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_mul_i32 s2, s4, s2
s_cmp_eq_u32 s4, 0
v_add_nc_u32_e32 v7, s2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s3
v_mad_u64_u32 v[5:6], null, v7, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v7, v2, v3
v_add3_u32 v3, s2, v0, v2
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[8:9], off
global_load_b32 v5, v[4:5], off
v_mad_u32_u24 v4, v1, s4, v0
s_mul_i32 s1, s4, s4
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, s1, v4
v_lshl_add_u32 v9, s1, 1, v4
v_lshl_add_u32 v4, v4, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v9, v9, 2, 0
s_waitcnt vmcnt(2)
ds_store_b32 v4, v6
s_waitcnt vmcnt(1)
ds_store_b32 v8, v7
s_waitcnt vmcnt(0)
ds_store_b32 v9, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_3
v_mul_u32_u24_e32 v1, s4, v1
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, s1, v1
s_lshl_b32 s1, s1, 3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, 0, s1, v0
s_lshl_b32 s1, s4, 2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, v1, 2, 0
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, s0, v1
s_add_i32 s0, s0, 4
ds_load_b32 v6, v0
ds_load_b32 v7, v4
ds_load_b32 v5, v5
v_add_nc_u32_e32 v0, s1, v0
s_cmp_eq_u32 s1, s0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v5, v7, v5
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
.LBB2_3:
ds_load_b32 v0, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3FW3Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3FW3Piiii, .Lfunc_end2-_Z3FW3Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3FW1Piii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z3FW1Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3FW2Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3FW2Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3FW3Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3FW3Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <fstream>
#include <cmath>
#define INFINITE 1000000000
int* distance_host;
int* distance_dev;
__global__ void FW1(int *distance_dev, int r, int vertexPadded){
int i = r * blockDim.x + threadIdx.y;
int j = r * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
extern __shared__ int dist[];
dist[threadIdx.y * blockDim.x + threadIdx.x] = distance_dev[ offset + j ];
__syncthreads();
for(int k=0; k<blockDim.x; ++k){
dist[ threadIdx.y * blockDim.x + threadIdx.x ] = min(dist[ threadIdx.y * blockDim.x + threadIdx.x ], dist[ threadIdx.y * blockDim.x + k ] + dist[ k * blockDim.x + threadIdx.x ]);
__syncthreads();
}
distance_dev[ offset + j ] = dist[threadIdx.y * blockDim.x + threadIdx.x];
}
__global__ void FW2(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i, block_j;
if(blockIdx.y == 0){
block_i = r;
block_j = (blockIdx.x + r + 1) % total_round;
}else{
block_j = r;
block_i = (blockIdx.x + r + 1) % total_round;
}
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j];
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x];
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ];
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
__global__ void FW3(int *distance_dev, int r, int vertexPadded, int total_round){
int block_i = (r + blockIdx.y + 1) % total_round;
int block_j = (r + blockIdx.x + 1) % total_round;
int i = block_i * blockDim.x + threadIdx.y;
int j = block_j * blockDim.x + threadIdx.x;
int offset = i * vertexPadded;
int index = threadIdx.y * blockDim.x + threadIdx.x;
int blockSize_squard = blockDim.x * blockDim.x;
extern __shared__ int dist[];
dist[index] = distance_dev[offset + j]; //block(i,j)
dist[blockSize_squard + index] = distance_dev[offset + threadIdx.x + r * blockDim.x]; //block(i,r)
dist[2*blockSize_squard + index] = distance_dev[(threadIdx.y + r * blockDim.x) * vertexPadded + j ]; //block(r,j)
__syncthreads();
for (int k = 0; k < blockDim.x; k++) {
int ik = threadIdx.y * blockDim.x + blockSize_squard + k;
int kj = k * blockDim.x + 2 * blockSize_squard + threadIdx.x;
dist[index] = min(dist[index], dist[ik] + dist[kj]);
__syncthreads();
}
distance_dev[offset + j] = dist[index];
}
void block_FW(int blockSize, int vertexNum, int vertexPadded) {
int round = vertexPadded / blockSize;
dim3 block(blockSize, blockSize);
dim3 grid2(round-1, 2);
dim3 grid3(round-1, round-1);
hipMalloc(&distance_dev, sizeof(int) * vertexPadded * vertexPadded);
hipMemcpy(distance_dev, distance_host, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyHostToDevice);
for (int r = 0; r < round; ++r) {
FW1<<< 1, block, blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded);
FW2<<< grid2, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
FW3<<< grid3, block, 3 * blockSize * blockSize * sizeof(int) >>>(distance_dev, r, vertexPadded, round);
}
hipMemcpy(distance_host, distance_dev, sizeof(int) * vertexPadded * vertexPadded, hipMemcpyDeviceToHost);
}
int main(int argc, char **argv){
//get number of threads per block
hipSetDevice(0);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
int ThreadsPerBlock = (int) sqrt(prop.maxThreadsPerBlock);
int blockSize = ThreadsPerBlock;
//read input file
std::ifstream inputFile(argv[1], std::ios::in | std::ios::binary);
unsigned vertexNum, edgeNum;
inputFile.read((char*)&vertexNum, 4);
inputFile.read((char*)&edgeNum, 4);
//calculate block number, vertex number in a block
if(vertexNum < blockSize) blockSize = vertexNum;
int blockNum = ceil( 1.0 * vertexNum / blockSize);
int vertexPadded = blockSize * blockNum;
//Allocate memory (pinned)
hipHostMalloc(&distance_host, sizeof(int) * vertexPadded * vertexPadded, hipHostMallocDefault);
for(unsigned i=0; i<vertexPadded; ++i){
for(unsigned j=0; j<vertexPadded; ++j){
if( i>=vertexNum || j>=vertexNum) distance_host[ i * vertexPadded + j ] = INFINITE;
else if( i == j) distance_host[ i * vertexPadded + j ] = 0;
else distance_host[ i * vertexPadded + j ] = INFINITE;
}
}
int source, destination, weight;
while( inputFile.read((char*)&source, 4) ){
inputFile.read((char*)&destination, 4);
inputFile.read((char*)&weight, 4);
distance_host[ source * vertexPadded + destination ] = weight;
}
inputFile.close();
block_FW(blockSize, vertexNum, vertexPadded);
//write answer to output file
std::ofstream outputFile(argv[2], std::ios::out | std::ios::binary);
for(int i=0; i<vertexNum; ++i){
for(int j=0; j<vertexNum; ++j){
outputFile.write( (char*)&distance_host[ i * vertexPadded + j ], 4);
}
}
outputFile.close();
hipFree(distance_host);
hipFree(distance_dev);
return 0;
} | .text
.file "apsp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__FW1Piii # -- Begin function _Z18__device_stub__FW1Piii
.p2align 4, 0x90
.type _Z18__device_stub__FW1Piii,@function
_Z18__device_stub__FW1Piii: # @_Z18__device_stub__FW1Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3FW1Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__FW1Piii, .Lfunc_end0-_Z18__device_stub__FW1Piii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__FW2Piiii # -- Begin function _Z18__device_stub__FW2Piiii
.p2align 4, 0x90
.type _Z18__device_stub__FW2Piiii,@function
_Z18__device_stub__FW2Piiii: # @_Z18__device_stub__FW2Piiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3FW2Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__FW2Piiii, .Lfunc_end1-_Z18__device_stub__FW2Piiii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__FW3Piiii # -- Begin function _Z18__device_stub__FW3Piiii
.p2align 4, 0x90
.type _Z18__device_stub__FW3Piiii,@function
_Z18__device_stub__FW3Piiii: # @_Z18__device_stub__FW3Piiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3FW3Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__FW3Piiii, .Lfunc_end2-_Z18__device_stub__FW3Piiii
.cfi_endproc
# -- End function
.globl _Z8block_FWiii # -- Begin function _Z8block_FWiii
.p2align 4, 0x90
.type _Z8block_FWiii,@function
_Z8block_FWiii: # @_Z8block_FWiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %edi, %ebx
movl %edx, %eax
cltd
idivl %edi
movl %eax, %r15d
movl %ecx, 16(%rsp) # 4-byte Spill
movslq %ecx, %r14
imulq %r14, %r14
shlq $2, %r14
movl $distance_dev, %edi
movq %r14, %rsi
callq hipMalloc
movq distance_dev(%rip), %rdi
movq distance_host(%rip), %rsi
movq %r14, 120(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB3_9
# %bb.1: # %.lr.ph
movl %ebx, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
leal -1(%r15), %eax
movabsq $8589934592, %rbp # imm = 0x200000000
orq %rax, %rbp
movq %rax, %r14
shlq $32, %r14
orq %rax, %r14
imull %ebx, %ebx
leaq (,%rbx,4), %rax
movq %rax, 128(%rsp) # 8-byte Spill
leal (%rbx,%rbx,2), %eax
movslq %eax, %rbx
shlq $2, %rbx
xorl %r12d, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_2 Depth=1
incl %r12d
cmpl %r12d, %r15d
je .LBB3_9
.LBB3_2: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW1Piii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW2Piiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW3Piiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9: # %._crit_edge
movq distance_host(%rip), %rdi
movq distance_dev(%rip), %rsi
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8block_FWiii, .Lfunc_end3-_Z8block_FWiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2552, %rsp # imm = 0x9F8
.cfi_def_cfa_offset 2608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
xorl %edi, %edi
callq hipSetDevice
leaq 1080(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cvtsi2sdl 1400(%rsp), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB4_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB4_3
.LBB4_2: # %call.sqrt
callq sqrt
.LBB4_3: # %.split
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rbx, 32(%rsp) # 8-byte Spill
movq 8(%rbx), %rsi
leaq 48(%rsp), %rbx
movq %rbx, %rdi
movl $12, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
leaq 4(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
callq _ZNSi4readEPcl
.Ltmp1:
# %bb.4:
.Ltmp2:
leaq 48(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
callq _ZNSi4readEPcl
.Ltmp3:
# %bb.5:
cvttsd2si 8(%rsp), %ebx # 8-byte Folded Reload
movl 4(%rsp), %eax
cmpl %ebx, %eax
cmovbl %eax, %ebx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %ebx, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
movl %ebx, 8(%rsp) # 4-byte Spill
imull %ebx, %r14d
movslq %r14d, %rbp
movq %rbp, %rsi
imulq %rbp, %rsi
shlq $2, %rsi
.Ltmp5:
movl $distance_host, %edi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp6:
# %bb.6: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit.preheader
testl %r14d, %r14d
je .LBB4_15
# %bb.7: # %.preheader68.preheader
movl %r14d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_14: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit
# in Loop: Header=BB4_8 Depth=1
incq %rdx
addq %rax, %rcx
cmpq %rax, %rdx
je .LBB4_15
.LBB4_8: # %.preheader68
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
movq distance_host(%rip), %rsi
movl %r14d, %edi
imull %edx, %edi
xorl %r8d, %r8d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_22: # in Loop: Header=BB4_9 Depth=2
xorl %r10d, %r10d
.LBB4_23: # in Loop: Header=BB4_9 Depth=2
movl %r9d, %r9d
movl %r10d, (%rsi,%r9,4)
incq %r8
cmpq %r8, %rax
je .LBB4_14
.LBB4_9: # Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movl 4(%rsp), %r9d
cmpq %r9, %rdx
jae .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=2
cmpq %r9, %r8
jae .LBB4_11
# %bb.21: # in Loop: Header=BB4_9 Depth=2
leal (%rdi,%r8), %r9d
cmpq %r8, %rdx
je .LBB4_22
jmp .LBB4_12
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=2
leal (%rcx,%r8), %r9d
.LBB4_12: # in Loop: Header=BB4_9 Depth=2
movl $1000000000, %r10d # imm = 0x3B9ACA00
jmp .LBB4_23
.LBB4_15: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit._crit_edge
leaq 48(%rsp), %r15
leaq 28(%rsp), %r12
leaq 24(%rsp), %r13
leaq 20(%rsp), %rbx
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
.Ltmp8:
movl $4, %edx
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSi4readEPcl
.Ltmp9:
# %bb.17: # in Loop: Header=BB4_16 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB4_26
# %bb.18: # in Loop: Header=BB4_16 Depth=1
.Ltmp32:
movl $4, %edx
movq %r15, %rdi
movq %r13, %rsi
callq _ZNSi4readEPcl
.Ltmp33:
# %bb.19: # in Loop: Header=BB4_16 Depth=1
.Ltmp34:
movl $4, %edx
movq %r15, %rdi
movq %rbx, %rsi
callq _ZNSi4readEPcl
.Ltmp35:
# %bb.20: # in Loop: Header=BB4_16 Depth=1
movl 20(%rsp), %eax
movq distance_host(%rip), %rcx
movslq 28(%rsp), %rdx
imulq %rbp, %rdx
movslq 24(%rsp), %rsi
addq %rdx, %rsi
movl %eax, (%rcx,%rsi,4)
jmp .LBB4_16
.LBB4_26:
leaq 64(%rsp), %rdi
.Ltmp10:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp11:
# %bb.27: # %.noexc
testq %rax, %rax
jne .LBB4_29
# %bb.28:
movq 48(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $48, %rdi
movl 80(%rsp,%rax), %esi
orl $4, %esi
.Ltmp12:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp13:
.LBB4_29: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp14:
movl 8(%rsp), %edi # 4-byte Reload
movl %r14d, %edx
callq _Z8block_FWiii
.Ltmp15:
# %bb.30:
movq 32(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rsi
.Ltmp17:
leaq 568(%rsp), %rdi
movl $20, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp18:
# %bb.31: # %.preheader67
cmpl $0, 4(%rsp)
je .LBB4_38
# %bb.32: # %.preheader.preheader
shlq $2, %rbp
xorl %r14d, %r14d
leaq 568(%rsp), %rbx
xorl %r15d, %r15d
jmp .LBB4_33
.p2align 4, 0x90
.LBB4_37: # %._crit_edge
# in Loop: Header=BB4_33 Depth=1
incq %r15
addq %rbp, %r14
cmpl %r15d, 4(%rsp)
jbe .LBB4_38
.LBB4_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_35 Depth 2
cmpl $0, 4(%rsp)
je .LBB4_37
# %bb.34: # %.lr.ph
# in Loop: Header=BB4_33 Depth=1
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB4_35: # Parent Loop BB4_33 Depth=1
# => This Inner Loop Header: Depth=2
movq distance_host(%rip), %rsi
addq %r13, %rsi
.Ltmp20:
movl $4, %edx
movq %rbx, %rdi
callq _ZNSo5writeEPKcl
.Ltmp21:
# %bb.36: # in Loop: Header=BB4_35 Depth=2
addq $4, %r13
incl %r12d
cmpl %r12d, 4(%rsp)
ja .LBB4_35
jmp .LBB4_37
.LBB4_38: # %._crit_edge73
leaq 576(%rsp), %rdi
.Ltmp23:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp24:
# %bb.39: # %.noexc65
testq %rax, %rax
jne .LBB4_41
# %bb.40:
movq 568(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $568, %rdi # imm = 0x238
movl 600(%rsp,%rax), %esi
orl $4, %esi
.Ltmp25:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp26:
.LBB4_41: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq distance_host(%rip), %rdi
.Ltmp27:
callq hipFree
.Ltmp28:
# %bb.42:
movq distance_dev(%rip), %rdi
.Ltmp29:
callq hipFree
.Ltmp30:
# %bb.43:
leaq 568(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 48(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $2552, %rsp # imm = 0x9F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_44:
.cfi_def_cfa_offset 2608
.Ltmp19:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_13:
.Ltmp7:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_49:
.Ltmp4:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_25: # %.loopexit.split-lp
.Ltmp16:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_46:
.Ltmp31:
jmp .LBB4_47
.LBB4_24: # %.loopexit
.Ltmp36:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_45:
.Ltmp22:
.LBB4_47:
movq %rax, %rbx
leaq 568(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB4_48:
leaq 48(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp35-.Ltmp8 # Call between .Ltmp8 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp10 # Call between .Ltmp10 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp30-.Ltmp23 # Call between .Ltmp23 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end4-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW1Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW2Piiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW3Piiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type distance_host,@object # @distance_host
.bss
.globl distance_host
.p2align 3, 0x0
distance_host:
.quad 0
.size distance_host, 8
.type distance_dev,@object # @distance_dev
.globl distance_dev
.p2align 3, 0x0
distance_dev:
.quad 0
.size distance_dev, 8
.type _Z3FW1Piii,@object # @_Z3FW1Piii
.section .rodata,"a",@progbits
.globl _Z3FW1Piii
.p2align 3, 0x0
_Z3FW1Piii:
.quad _Z18__device_stub__FW1Piii
.size _Z3FW1Piii, 8
.type _Z3FW2Piiii,@object # @_Z3FW2Piiii
.globl _Z3FW2Piiii
.p2align 3, 0x0
_Z3FW2Piiii:
.quad _Z18__device_stub__FW2Piiii
.size _Z3FW2Piiii, 8
.type _Z3FW3Piiii,@object # @_Z3FW3Piiii
.globl _Z3FW3Piiii
.p2align 3, 0x0
_Z3FW3Piiii:
.quad _Z18__device_stub__FW3Piiii
.size _Z3FW3Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3FW1Piii"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3FW2Piiii"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3FW3Piiii"
.size .L__unnamed_3, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__FW1Piii
.addrsig_sym _Z18__device_stub__FW2Piiii
.addrsig_sym _Z18__device_stub__FW3Piiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym distance_host
.addrsig_sym distance_dev
.addrsig_sym _Z3FW1Piii
.addrsig_sym _Z3FW2Piiii
.addrsig_sym _Z3FW3Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005f881_00000000-6_apsp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3FW1PiiiPiii
.type _Z24__device_stub__Z3FW1PiiiPiii, @function
_Z24__device_stub__Z3FW1PiiiPiii:
.LFB4065:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3FW1Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z24__device_stub__Z3FW1PiiiPiii, .-_Z24__device_stub__Z3FW1PiiiPiii
.globl _Z3FW1Piii
.type _Z3FW1Piii, @function
_Z3FW1Piii:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3FW1PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z3FW1Piii, .-_Z3FW1Piii
.globl _Z25__device_stub__Z3FW2PiiiiPiiii
.type _Z25__device_stub__Z3FW2PiiiiPiiii, @function
_Z25__device_stub__Z3FW2PiiiiPiiii:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3FW2Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z25__device_stub__Z3FW2PiiiiPiiii, .-_Z25__device_stub__Z3FW2PiiiiPiiii
.globl _Z3FW2Piiii
.type _Z3FW2Piiii, @function
_Z3FW2Piiii:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3FW2PiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z3FW2Piiii, .-_Z3FW2Piiii
.globl _Z25__device_stub__Z3FW3PiiiiPiiii
.type _Z25__device_stub__Z3FW3PiiiiPiiii, @function
_Z25__device_stub__Z3FW3PiiiiPiiii:
.LFB4069:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3FW3Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4069:
.size _Z25__device_stub__Z3FW3PiiiiPiiii, .-_Z25__device_stub__Z3FW3PiiiiPiiii
.globl _Z3FW3Piiii
.type _Z3FW3Piiii, @function
_Z3FW3Piiii:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3FW3PiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _Z3FW3Piiii, .-_Z3FW3Piiii
.globl _Z8block_FWiii
.type _Z8block_FWiii, @function
_Z8block_FWiii:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %edx, %r13d
movl %edx, %eax
cltd
idivl %edi
movl %eax, %r12d
movl %edi, (%rsp)
movl %edi, 4(%rsp)
movl $1, 8(%rsp)
leal -1(%rax), %eax
movl %eax, 12(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movslq %r13d, %r15
imulq %r15, %r15
salq $2, %r15
movq %r15, %rsi
leaq distance_dev(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq distance_host(%rip), %rsi
movq distance_dev(%rip), %rdi
call cudaMemcpy@PLT
testl %r12d, %r12d
jle .L28
imull %ebx, %ebx
movslq %ebx, %r14
salq $2, %r14
leal (%rbx,%rbx,2), %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl $0, %ebx
jmp .L32
.L35:
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z24__device_stub__Z3FW1PiiiPiii
jmp .L29
.L36:
movl %r12d, %ecx
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z25__device_stub__Z3FW2PiiiiPiiii
jmp .L30
.L31:
addl $1, %ebx
cmpl %ebx, %r12d
je .L28
.L32:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 8(%rsp), %ecx
movl $0, %r9d
movq %r14, %r8
movq (%rsp), %rdx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movl 8(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq (%rsp), %rdx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
movl 8(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq (%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl %r12d, %ecx
movl %r13d, %edx
movl %ebx, %esi
movq distance_dev(%rip), %rdi
call _Z25__device_stub__Z3FW3PiiiiPiiii
jmp .L31
.L28:
movl $2, %ecx
movq %r15, %rdx
movq distance_dev(%rip), %rsi
movq distance_host(%rip), %rdi
call cudaMemcpy@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _Z8block_FWiii, .-_Z8block_FWiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3FW3Piiii"
.LC1:
.string "_Z3FW2Piiii"
.LC2:
.string "_Z3FW1Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW3Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW2Piiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3FW1Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4072:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.globl main
.type main, @function
main:
.LFB4040:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4040
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2120, %rsp
.cfi_def_cfa_offset 2176
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call cudaSetDevice@PLT
leaq 1072(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 1392(%rsp), %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L70
sqrtsd %xmm0, %xmm0
.L42:
cvttsd2sil %xmm0, %r12d
movq 8(%r13), %rsi
leaq 544(%rsp), %rbx
movl $12, %edx
movq %rbx, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 12(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSi4readEPcl@PLT
jmp .L73
.L70:
call sqrt@PLT
jmp .L42
.L73:
leaq 16(%rsp), %rsi
movq %rbx, %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
movl 12(%rsp), %eax
cmpl %eax, %r12d
cmova %eax, %r12d
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L46
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L46:
cvttsd2sil %xmm3, %ebx
imull %r12d, %ebx
movslq %ebx, %r15
movq %r15, %rsi
imulq %r15, %rsi
salq $2, %rsi
movl $0, %edx
leaq distance_host(%rip), %rdi
call cudaHostAlloc@PLT
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
testl %ebx, %ebx
jne .L47
.L48:
leaq 20(%rsp), %r14
jmp .L53
.L49:
cmpl %eax, %ecx
je .L74
leal (%rax,%r8), %edx
movq distance_host(%rip), %rdi
movl $1000000000, (%rdi,%rdx,4)
.L50:
addl $1, %eax
addl $1, %esi
cmpl %ebx, %eax
je .L75
.L52:
cmpl %eax, %ecx
movl %eax, %edx
cmovnb %ecx, %edx
cmpl 12(%rsp), %edx
jb .L49
leal (%rax,%r8), %edx
movq distance_host(%rip), %rdi
movl $1000000000, (%rdi,%rdx,4)
jmp .L50
.L74:
movl %esi, %edx
movq distance_host(%rip), %rdi
movl $0, (%rdi,%rdx,4)
jmp .L50
.L75:
addl $1, %ecx
addl %ebx, %r8d
addl %ebx, %r9d
cmpl %ebx, %ecx
je .L48
.L47:
movl %r9d, %esi
movl $0, %eax
jmp .L52
.L77:
leaq 28(%rsp), %rsi
leaq 544(%rsp), %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
movl %ebx, %eax
imull 20(%rsp), %eax
addl 24(%rsp), %eax
cltq
movl 28(%rsp), %ecx
movq distance_host(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
.L53:
leaq 544(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
call _ZNSi4readEPcl@PLT
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L76
leaq 24(%rsp), %rsi
leaq 544(%rsp), %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
jmp .L77
.L76:
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
movl %ebx, %edx
movl 12(%rsp), %esi
movl %r12d, %edi
call _Z8block_FWiii
movq 16(%r13), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
cmpl $0, 12(%rsp)
je .L55
salq $2, %r15
movl $0, %r13d
movl $0, %r14d
leaq 32(%rsp), %r12
jmp .L56
.L79:
addl $1, %ebx
movl 12(%rsp), %eax
addq $4, %rbp
cmpl %eax, %ebx
jnb .L78
.L57:
movq %rbp, %rsi
addq distance_host(%rip), %rsi
movl $4, %edx
movq %r12, %rdi
.LEHB2:
call _ZNSo5writeEPKcl@PLT
jmp .L79
.L78:
addl $1, %r14d
addq %r15, %r13
cmpl %eax, %r14d
jnb .L55
.L56:
cmpl $0, 12(%rsp)
je .L55
movq %r13, %rbp
movl $0, %ebx
jmp .L57
.L55:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq distance_host(%rip), %rdi
call cudaFree@PLT
movq distance_dev(%rip), %rdi
call cudaFree@PLT
.LEHE2:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L59:
leaq 544(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
je .L60
call __stack_chk_fail@PLT
.L64:
endbr64
movq %rax, %rbx
jmp .L59
.L60:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4040:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4040:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4040-.LLSDACSB4040
.LLSDACSB4040:
.uleb128 .LEHB0-.LFB4040
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4040
.uleb128 .LEHE1-.LEHB1
.uleb128 .L64-.LFB4040
.uleb128 0
.uleb128 .LEHB2-.LFB4040
.uleb128 .LEHE2-.LEHB2
.uleb128 .L65-.LFB4040
.uleb128 0
.uleb128 .LEHB3-.LFB4040
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4040:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl distance_dev
.bss
.align 8
.type distance_dev, @object
.size distance_dev, 8
distance_dev:
.zero 8
.globl distance_host
.align 8
.type distance_host, @object
.size distance_host, 8
distance_host:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "apsp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__FW1Piii # -- Begin function _Z18__device_stub__FW1Piii
.p2align 4, 0x90
.type _Z18__device_stub__FW1Piii,@function
_Z18__device_stub__FW1Piii: # @_Z18__device_stub__FW1Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3FW1Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__FW1Piii, .Lfunc_end0-_Z18__device_stub__FW1Piii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__FW2Piiii # -- Begin function _Z18__device_stub__FW2Piiii
.p2align 4, 0x90
.type _Z18__device_stub__FW2Piiii,@function
_Z18__device_stub__FW2Piiii: # @_Z18__device_stub__FW2Piiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3FW2Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__FW2Piiii, .Lfunc_end1-_Z18__device_stub__FW2Piiii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__FW3Piiii # -- Begin function _Z18__device_stub__FW3Piiii
.p2align 4, 0x90
.type _Z18__device_stub__FW3Piiii,@function
_Z18__device_stub__FW3Piiii: # @_Z18__device_stub__FW3Piiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3FW3Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__FW3Piiii, .Lfunc_end2-_Z18__device_stub__FW3Piiii
.cfi_endproc
# -- End function
.globl _Z8block_FWiii # -- Begin function _Z8block_FWiii
.p2align 4, 0x90
.type _Z8block_FWiii,@function
_Z8block_FWiii: # @_Z8block_FWiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %edi, %ebx
movl %edx, %eax
cltd
idivl %edi
movl %eax, %r15d
movl %ecx, 16(%rsp) # 4-byte Spill
movslq %ecx, %r14
imulq %r14, %r14
shlq $2, %r14
movl $distance_dev, %edi
movq %r14, %rsi
callq hipMalloc
movq distance_dev(%rip), %rdi
movq distance_host(%rip), %rsi
movq %r14, 120(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB3_9
# %bb.1: # %.lr.ph
movl %ebx, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
leal -1(%r15), %eax
movabsq $8589934592, %rbp # imm = 0x200000000
orq %rax, %rbp
movq %rax, %r14
shlq $32, %r14
orq %rax, %r14
imull %ebx, %ebx
leaq (,%rbx,4), %rax
movq %rax, 128(%rsp) # 8-byte Spill
leal (%rbx,%rbx,2), %eax
movslq %eax, %rbx
shlq $2, %rbx
xorl %r12d, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_2 Depth=1
incl %r12d
cmpl %r12d, %r15d
je .LBB3_9
.LBB3_2: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW1Piii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW2Piiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movq distance_dev(%rip), %rax
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z3FW3Piiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9: # %._crit_edge
movq distance_host(%rip), %rdi
movq distance_dev(%rip), %rsi
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8block_FWiii, .Lfunc_end3-_Z8block_FWiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2552, %rsp # imm = 0x9F8
.cfi_def_cfa_offset 2608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
xorl %edi, %edi
callq hipSetDevice
leaq 1080(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cvtsi2sdl 1400(%rsp), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB4_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB4_3
.LBB4_2: # %call.sqrt
callq sqrt
.LBB4_3: # %.split
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rbx, 32(%rsp) # 8-byte Spill
movq 8(%rbx), %rsi
leaq 48(%rsp), %rbx
movq %rbx, %rdi
movl $12, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
leaq 4(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
callq _ZNSi4readEPcl
.Ltmp1:
# %bb.4:
.Ltmp2:
leaq 48(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
callq _ZNSi4readEPcl
.Ltmp3:
# %bb.5:
cvttsd2si 8(%rsp), %ebx # 8-byte Folded Reload
movl 4(%rsp), %eax
cmpl %ebx, %eax
cmovbl %eax, %ebx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %ebx, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r14d
movl %ebx, 8(%rsp) # 4-byte Spill
imull %ebx, %r14d
movslq %r14d, %rbp
movq %rbp, %rsi
imulq %rbp, %rsi
shlq $2, %rsi
.Ltmp5:
movl $distance_host, %edi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp6:
# %bb.6: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit.preheader
testl %r14d, %r14d
je .LBB4_15
# %bb.7: # %.preheader68.preheader
movl %r14d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_14: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit
# in Loop: Header=BB4_8 Depth=1
incq %rdx
addq %rax, %rcx
cmpq %rax, %rdx
je .LBB4_15
.LBB4_8: # %.preheader68
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
movq distance_host(%rip), %rsi
movl %r14d, %edi
imull %edx, %edi
xorl %r8d, %r8d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_22: # in Loop: Header=BB4_9 Depth=2
xorl %r10d, %r10d
.LBB4_23: # in Loop: Header=BB4_9 Depth=2
movl %r9d, %r9d
movl %r10d, (%rsi,%r9,4)
incq %r8
cmpq %r8, %rax
je .LBB4_14
.LBB4_9: # Parent Loop BB4_8 Depth=1
# => This Inner Loop Header: Depth=2
movl 4(%rsp), %r9d
cmpq %r9, %rdx
jae .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=2
cmpq %r9, %r8
jae .LBB4_11
# %bb.21: # in Loop: Header=BB4_9 Depth=2
leal (%rdi,%r8), %r9d
cmpq %r8, %rdx
je .LBB4_22
jmp .LBB4_12
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=2
leal (%rcx,%r8), %r9d
.LBB4_12: # in Loop: Header=BB4_9 Depth=2
movl $1000000000, %r10d # imm = 0x3B9ACA00
jmp .LBB4_23
.LBB4_15: # %_ZL13hipHostMallocIiE10hipError_tPPT_mj.exit._crit_edge
leaq 48(%rsp), %r15
leaq 28(%rsp), %r12
leaq 24(%rsp), %r13
leaq 20(%rsp), %rbx
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
.Ltmp8:
movl $4, %edx
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSi4readEPcl
.Ltmp9:
# %bb.17: # in Loop: Header=BB4_16 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB4_26
# %bb.18: # in Loop: Header=BB4_16 Depth=1
.Ltmp32:
movl $4, %edx
movq %r15, %rdi
movq %r13, %rsi
callq _ZNSi4readEPcl
.Ltmp33:
# %bb.19: # in Loop: Header=BB4_16 Depth=1
.Ltmp34:
movl $4, %edx
movq %r15, %rdi
movq %rbx, %rsi
callq _ZNSi4readEPcl
.Ltmp35:
# %bb.20: # in Loop: Header=BB4_16 Depth=1
movl 20(%rsp), %eax
movq distance_host(%rip), %rcx
movslq 28(%rsp), %rdx
imulq %rbp, %rdx
movslq 24(%rsp), %rsi
addq %rdx, %rsi
movl %eax, (%rcx,%rsi,4)
jmp .LBB4_16
.LBB4_26:
leaq 64(%rsp), %rdi
.Ltmp10:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp11:
# %bb.27: # %.noexc
testq %rax, %rax
jne .LBB4_29
# %bb.28:
movq 48(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $48, %rdi
movl 80(%rsp,%rax), %esi
orl $4, %esi
.Ltmp12:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp13:
.LBB4_29: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp14:
movl 8(%rsp), %edi # 4-byte Reload
movl %r14d, %edx
callq _Z8block_FWiii
.Ltmp15:
# %bb.30:
movq 32(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rsi
.Ltmp17:
leaq 568(%rsp), %rdi
movl $20, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp18:
# %bb.31: # %.preheader67
cmpl $0, 4(%rsp)
je .LBB4_38
# %bb.32: # %.preheader.preheader
shlq $2, %rbp
xorl %r14d, %r14d
leaq 568(%rsp), %rbx
xorl %r15d, %r15d
jmp .LBB4_33
.p2align 4, 0x90
.LBB4_37: # %._crit_edge
# in Loop: Header=BB4_33 Depth=1
incq %r15
addq %rbp, %r14
cmpl %r15d, 4(%rsp)
jbe .LBB4_38
.LBB4_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_35 Depth 2
cmpl $0, 4(%rsp)
je .LBB4_37
# %bb.34: # %.lr.ph
# in Loop: Header=BB4_33 Depth=1
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB4_35: # Parent Loop BB4_33 Depth=1
# => This Inner Loop Header: Depth=2
movq distance_host(%rip), %rsi
addq %r13, %rsi
.Ltmp20:
movl $4, %edx
movq %rbx, %rdi
callq _ZNSo5writeEPKcl
.Ltmp21:
# %bb.36: # in Loop: Header=BB4_35 Depth=2
addq $4, %r13
incl %r12d
cmpl %r12d, 4(%rsp)
ja .LBB4_35
jmp .LBB4_37
.LBB4_38: # %._crit_edge73
leaq 576(%rsp), %rdi
.Ltmp23:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp24:
# %bb.39: # %.noexc65
testq %rax, %rax
jne .LBB4_41
# %bb.40:
movq 568(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $568, %rdi # imm = 0x238
movl 600(%rsp,%rax), %esi
orl $4, %esi
.Ltmp25:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp26:
.LBB4_41: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq distance_host(%rip), %rdi
.Ltmp27:
callq hipFree
.Ltmp28:
# %bb.42:
movq distance_dev(%rip), %rdi
.Ltmp29:
callq hipFree
.Ltmp30:
# %bb.43:
leaq 568(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 48(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $2552, %rsp # imm = 0x9F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_44:
.cfi_def_cfa_offset 2608
.Ltmp19:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_13:
.Ltmp7:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_49:
.Ltmp4:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_25: # %.loopexit.split-lp
.Ltmp16:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_46:
.Ltmp31:
jmp .LBB4_47
.LBB4_24: # %.loopexit
.Ltmp36:
movq %rax, %rbx
jmp .LBB4_48
.LBB4_45:
.Ltmp22:
.LBB4_47:
movq %rax, %rbx
leaq 568(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB4_48:
leaq 48(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp35-.Ltmp8 # Call between .Ltmp8 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp10 # Call between .Ltmp10 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp30-.Ltmp23 # Call between .Ltmp23 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end4-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW1Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW2Piiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3FW3Piiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type distance_host,@object # @distance_host
.bss
.globl distance_host
.p2align 3, 0x0
distance_host:
.quad 0
.size distance_host, 8
.type distance_dev,@object # @distance_dev
.globl distance_dev
.p2align 3, 0x0
distance_dev:
.quad 0
.size distance_dev, 8
.type _Z3FW1Piii,@object # @_Z3FW1Piii
.section .rodata,"a",@progbits
.globl _Z3FW1Piii
.p2align 3, 0x0
_Z3FW1Piii:
.quad _Z18__device_stub__FW1Piii
.size _Z3FW1Piii, 8
.type _Z3FW2Piiii,@object # @_Z3FW2Piiii
.globl _Z3FW2Piiii
.p2align 3, 0x0
_Z3FW2Piiii:
.quad _Z18__device_stub__FW2Piiii
.size _Z3FW2Piiii, 8
.type _Z3FW3Piiii,@object # @_Z3FW3Piiii
.globl _Z3FW3Piiii
.p2align 3, 0x0
_Z3FW3Piiii:
.quad _Z18__device_stub__FW3Piiii
.size _Z3FW3Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3FW1Piii"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3FW2Piiii"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3FW3Piiii"
.size .L__unnamed_3, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__FW1Piii
.addrsig_sym _Z18__device_stub__FW2Piiii
.addrsig_sym _Z18__device_stub__FW3Piiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym distance_host
.addrsig_sym distance_dev
.addrsig_sym _Z3FW1Piii
.addrsig_sym _Z3FW2Piiii
.addrsig_sym _Z3FW3Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
cudaError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return cudaGetLastError();
} | code for sm_80
Function : _Z14actiune_threadPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
cudaError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return cudaGetLastError();
} | .file "tmpxft_00048ec6_00000000-6_cudaCode.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14actiune_threadPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.type _Z14actiune_threadPfS_S_i, @function
_Z14actiune_threadPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14actiune_threadPfS_S_i, .-_Z14actiune_threadPfS_S_i
.globl launch_actiune_thread
.type launch_actiune_thread, @function
launch_actiune_thread:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %rdi
movl %r9d, %esi
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaGetLastError@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
jmp .L12
.cfi_endproc
.LFE2027:
.size launch_actiune_thread, .-launch_actiune_thread
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14actiune_threadPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14actiune_threadPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
cudaError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return cudaGetLastError();
} | #include <hip/hip_runtime.h>
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
hipError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return hipGetLastError();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
hipError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return hipGetLastError();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14actiune_threadPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.p2align 8
.type _Z14actiune_threadPfS_S_i,@function
_Z14actiune_threadPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14actiune_threadPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14actiune_threadPfS_S_i, .Lfunc_end0-_Z14actiune_threadPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14actiune_threadPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14actiune_threadPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N);
// Kernelul ce se executa pe device-ul CUDA
__global__ void actiune_thread(float* a_d, float* b_d,float *r_d,int N)
{
// Identificarea pozitiei exacte a thread-ului
int x,y;
x = (blockIdx.x * blockDim.x + threadIdx.x);
//y = (blockIdx.y * blockDim.y + threadIdx.y);
r_d[x] = a_d[x]+1.f;
//for(int j=0;j<N;j++)
//for(int k=0;k<N;k++)
//r_d[x] += sqrt(a_d[j]+b_d[j]) / sqrt(a_d[k]+b_d[k]);
//Operatii adaugate codului anterior
//r_d[x] = 0;
//for(int j = 0; j < N; j++){
//r_d[x] = a_d[x] + a_d[j]*a_d[j];
//}
}
extern "C"
hipError_t launch_actiune_thread(float* a_d, float* b_d,float *r_d,int N,dim3 DIM_GRID, dim3 DIM_BLOCK)
{
actiune_thread <<<DIM_GRID, DIM_BLOCK>>> (a_d, b_d,r_d,N);
return hipGetLastError();
} | .text
.file "cudaCode.hip"
.globl _Z29__device_stub__actiune_threadPfS_S_i # -- Begin function _Z29__device_stub__actiune_threadPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__actiune_threadPfS_S_i,@function
_Z29__device_stub__actiune_threadPfS_S_i: # @_Z29__device_stub__actiune_threadPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14actiune_threadPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__actiune_threadPfS_S_i, .Lfunc_end0-_Z29__device_stub__actiune_threadPfS_S_i
.cfi_endproc
# -- End function
.globl launch_actiune_thread # -- Begin function launch_actiune_thread
.p2align 4, 0x90
.type launch_actiune_thread,@function
launch_actiune_thread: # @launch_actiune_thread
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 160(%rsp), %rdx
movl 168(%rsp), %ecx
movq %r8, %rdi
movl %r9d, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14actiune_threadPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size launch_actiune_thread, .Lfunc_end1-launch_actiune_thread
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14actiune_threadPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14actiune_threadPfS_S_i,@object # @_Z14actiune_threadPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14actiune_threadPfS_S_i
.p2align 3, 0x0
_Z14actiune_threadPfS_S_i:
.quad _Z29__device_stub__actiune_threadPfS_S_i
.size _Z14actiune_threadPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14actiune_threadPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__actiune_threadPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14actiune_threadPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14actiune_threadPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14actiune_threadPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.p2align 8
.type _Z14actiune_threadPfS_S_i,@function
_Z14actiune_threadPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14actiune_threadPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14actiune_threadPfS_S_i, .Lfunc_end0-_Z14actiune_threadPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14actiune_threadPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14actiune_threadPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00048ec6_00000000-6_cudaCode.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14actiune_threadPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.type _Z14actiune_threadPfS_S_i, @function
_Z14actiune_threadPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14actiune_threadPfS_S_i, .-_Z14actiune_threadPfS_S_i
.globl launch_actiune_thread
.type launch_actiune_thread, @function
launch_actiune_thread:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %rdi
movl %r9d, %esi
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaGetLastError@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
jmp .L12
.cfi_endproc
.LFE2027:
.size launch_actiune_thread, .-launch_actiune_thread
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14actiune_threadPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14actiune_threadPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaCode.hip"
.globl _Z29__device_stub__actiune_threadPfS_S_i # -- Begin function _Z29__device_stub__actiune_threadPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__actiune_threadPfS_S_i,@function
_Z29__device_stub__actiune_threadPfS_S_i: # @_Z29__device_stub__actiune_threadPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14actiune_threadPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__actiune_threadPfS_S_i, .Lfunc_end0-_Z29__device_stub__actiune_threadPfS_S_i
.cfi_endproc
# -- End function
.globl launch_actiune_thread # -- Begin function launch_actiune_thread
.p2align 4, 0x90
.type launch_actiune_thread,@function
launch_actiune_thread: # @launch_actiune_thread
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 160(%rsp), %rdx
movl 168(%rsp), %ecx
movq %r8, %rdi
movl %r9d, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14actiune_threadPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size launch_actiune_thread, .Lfunc_end1-launch_actiune_thread
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14actiune_threadPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14actiune_threadPfS_S_i,@object # @_Z14actiune_threadPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14actiune_threadPfS_S_i
.p2align 3, 0x0
_Z14actiune_threadPfS_S_i:
.quad _Z29__device_stub__actiune_threadPfS_S_i
.size _Z14actiune_threadPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14actiune_threadPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__actiune_threadPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14actiune_threadPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
cudaMallocManaged(&adj, n * n * sizeof(int));
cudaMallocManaged(&idxmin, sizeof(int));
cudaMallocManaged(&minval, sizeof(int));
cudaMallocManaged(&min_edge, n * sizeof(pair<int, int>));
cudaMallocManaged(&result, n * sizeof(pair<int, int>));
cudaMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
cudaDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
cudaFree(adj);
cudaFree(idxmin);
cudaFree(minval);
cudaFree(min_edge);
cudaFree(result);
cudaFree(visited);
return 0;
} | code for sm_80
Function : _Z9reduceMiniPSt4pairIiiEPbPiS3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B1, 0xa40 ; /* 0x00000a0000017945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3b9aca07 ; /* 0x3b9aca07ff027424 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R4, R9, c[0x0][0x0], R10 ; /* 0x0000000009047a24 */
/* 0x001fca00078e020a */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xa30 ; /* 0x0000099000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x850 ; /* 0x0000079000007945 */
/* 0x000fe60003800000 */
/*00c0*/ IMAD R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a24 */
/* 0x000fc800078e02ff */
/*00d0*/ I2F.U32.RP R2, R3 ; /* 0x0000000300027306 */
/* 0x000e220000209000 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*00f0*/ IADD3 R8, R3.reuse, R4, RZ ; /* 0x0000000403087210 */
/* 0x040fe40007ffe0ff */
/*0100*/ ISETP.NE.U32.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f45070 */
/*0110*/ LOP3.LUT R0, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff007212 */
/* 0x000fc800078e33ff */
/*0120*/ IADD3 R0, R0, c[0x0][0x160], R3 ; /* 0x0000580000007a10 */
/* 0x000fe20007ffe003 */
/*0130*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD R5, R5, R7, RZ ; /* 0x0000000705057224 */
/* 0x002fc800078e02ff */
/*0180*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0190*/ IMAD.HI.U32 R7, R7, R0, RZ ; /* 0x0000000007077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R2, RZ, RZ, -R7 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a07 */
/*01b0*/ IMAD R0, R3, R2, R0 ; /* 0x0000000203007224 */
/* 0x000fe200078e0200 */
/*01c0*/ HFMA2.MMA R2, -RZ, RZ, 0.9501953125, -12.0546875 ; /* 0x3b9aca07ff027435 */
/* 0x000fc800000001ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100000824 */
/* 0x000fe200078e0a03 */
/*01f0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe20003f26070 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fd800078e00ff */
/*0220*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P2 LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff07a212 */
/* 0x000fc800078e33ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x3, PT ; /* 0x000000030700780c */
/* 0x040fe40003f06070 */
/*0250*/ IADD3 R12, R7, 0x1, RZ ; /* 0x00000001070c7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ LOP3.LUT R5, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c057812 */
/* 0x000fce00078ec0ff */
/*0270*/ @!P0 BRA 0x840 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R2, 0x3b9aca07 ; /* 0x3b9aca0700027802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*02b0*/ IMAD R7, R0.reuse, 0x3, R9.reuse ; /* 0x0000000300077824 */
/* 0x140fe400078e0209 */
/*02c0*/ IMAD R9, R0, 0x2, R9 ; /* 0x0000000200097824 */
/* 0x000fe400078e0209 */
/*02d0*/ IMAD R8, R7, c[0x0][0x0], R10.reuse ; /* 0x0000000007087a24 */
/* 0x100fe400078e020a */
/*02e0*/ IMAD R10, R9, c[0x0][0x0], R10 ; /* 0x00000000090a7a24 */
/* 0x000fe200078e020a */
/*02f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R3 ; /* 0x0000001fff097819 */
/* 0x000fe20000011403 */
/*0300*/ IMAD.IADD R7, R12, 0x1, -R5 ; /* 0x000000010c077824 */
/* 0x000fc400078e0a05 */
/*0310*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe400078e00ff */
/*0320*/ SHF.R.S32.HI R11, RZ, 0x1f, R4 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011404 */
/*0330*/ IADD3 R12, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c00040c7a10 */
/* 0x000fc80007f1e0ff */
/*0340*/ IADD3.X R13, R11, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000b0d7a10 */
/* 0x000fca00007fe4ff */
/*0350*/ LDG.E.U8 R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000ea2000c1e1100 */
/*0360*/ BSSY B2, 0x460 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x004fda0003f05270 */
/*0380*/ @P0 BRA 0x450 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0390*/ LEA R14, P0, R4, c[0x0][0x168], 0x3 ; /* 0x00005a00040e7a11 */
/* 0x000fc800078018ff */
/*03a0*/ LEA.HI.X R15, R4, c[0x0][0x16c], R11, 0x3, P0 ; /* 0x00005b00040f7a11 */
/* 0x000fca00000f1c0b */
/*03b0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*03c0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x430 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x001fc800078e00ff */
/*03f0*/ IMAD.WIDE R14, R0, R15, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fcc00078e020f */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0420*/ @P0 BRA 0x450 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0440*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0450*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fc80007f1e0ff */
/*0470*/ IADD3.X R13, R9, R13, RZ, P0, !PT ; /* 0x0000000d090d7210 */
/* 0x000fca00007fe4ff */
/*0480*/ LDG.E.U8 R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000ea2000c1e1100 */
/*0490*/ BSSY B2, 0x580 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*04a0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 BRA 0x570 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE R14, R6, R17, c[0x0][0x168] ; /* 0x00005a00060e7625 */
/* 0x000fca00078e0211 */
/*04e0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*04f0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0500*/ @!P0 BRA 0x550 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.WIDE R14, R0, R17, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x001fcc00078e0211 */
/*0520*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0540*/ @P0 BRA 0x570 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0560*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*0570*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0580*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fca0007f1e0ff */
/*0590*/ IMAD.X R13, R9, 0x1, R13, P0 ; /* 0x00000001090d7824 */
/* 0x000fca00000e060d */
/*05a0*/ LDG.E.U8 R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000ea2000c1e1100 */
/*05b0*/ BSSY B2, 0x6a0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x004fda0003f05270 */
/*05d0*/ @P0 BRA 0x690 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R17, 0x8 ; /* 0x0000000800117802 */
/* 0x000fca0000000f00 */
/*05f0*/ IMAD.WIDE R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fca00078e0211 */
/*0600*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*0610*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0620*/ @!P0 BRA 0x670 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.WIDE R14, R0, R17, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x001fcc00078e0211 */
/*0640*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0650*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0660*/ @P0 BRA 0x690 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0680*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000a */
/*0690*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*06a0*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fca0007f1e0ff */
/*06b0*/ IMAD.X R13, R9, 0x1, R13, P0 ; /* 0x00000001090d7824 */
/* 0x000fca00000e060d */
/*06c0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ BSSY B2, 0x7c0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*06e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fda0003f05270 */
/*06f0*/ @P0 BRA 0x7b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fc800078e00ff */
/*0710*/ IMAD.WIDE R12, R8, R15, c[0x0][0x168] ; /* 0x00005a00080c7625 */
/* 0x000fca00078e020f */
/*0720*/ LDG.E R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000162000c1e1900 */
/*0730*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x790 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.WIDE R12, R0, R15, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x001fcc00078e020f */
/*0760*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea4000c1e1900 */
/*0770*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x024fda0003f06270 */
/*0780*/ @P0 BRA 0x7b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0790*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x021fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*07b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD R8, R3.reuse, 0x4, R8 ; /* 0x0000000403087824 */
/* 0x040fe200078e0208 */
/*07e0*/ IADD3 R4, R3.reuse, R4, R3.reuse ; /* 0x0000000403047210 */
/* 0x140fe20007ffe003 */
/*07f0*/ IMAD R10, R3, 0x4, R10 ; /* 0x00000004030a7824 */
/* 0x000fe200078e020a */
/*0800*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0810*/ IMAD R6, R3.reuse, 0x4, R6 ; /* 0x0000000403067824 */
/* 0x040fe200078e0206 */
/*0820*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fd60007ffe003 */
/*0830*/ @P0 BRA 0x320 ; /* 0xfffffae000000947 */
/* 0x000fea000383ffff */
/*0840*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0860*/ @!P0 BRA 0xa30 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0870*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0880*/ IADD3 R10, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c00040a7a10 */
/* 0x000fc80007f1e0ff */
/*0890*/ LEA.HI.X.SX32 R11, R4, c[0x0][0x174], 0x1, P0 ; /* 0x00005d00040b7a11 */
/* 0x000fca00000f0eff */
/*08a0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0207 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*08c0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000b */
/*08d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1100 */
/*08e0*/ BSSY B0, 0x9c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*08f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0900*/ @P0 BRA 0x9b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000162000c1e1900 */
/*0920*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0930*/ @!P0 BRA 0x990 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0940*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fc800078e00ff */
/*0950*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*0960*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*0970*/ ISETP.GE.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x024fda0003f06270 */
/*0980*/ @P0 BRA 0x9b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x021fe200078e000d */
/*09a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*09b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09c0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ IMAD.IADD R4, R3.reuse, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x040fe200078e0204 */
/*09e0*/ IADD3 R10, P1, R3.reuse, R10, RZ ; /* 0x0000000a030a7210 */
/* 0x040fe20007f3e0ff */
/*09f0*/ IMAD.WIDE R6, R3, 0x8, R6 ; /* 0x0000000803067825 */
/* 0x000fe200078e0206 */
/*0a00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0a10*/ LEA.HI.X.SX32 R11, R3, R11, 0x1, P1 ; /* 0x0000000b030b7211 */
/* 0x000fd600008f0eff */
/*0a20*/ @P0 BRA 0x8b0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a40*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*0a50*/ REDUX.MIN.S32 UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e620000010200 */
/*0a60*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0a80*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0aa0*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x001fe4000bf02070 */
/*0ab0*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x002fd60008000f00 */
/*0ac0*/ @P0 RED.E.MIN.S32.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x0001e8000c90e386 */
/*0ad0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ae0*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea4000c1e1900 */
/*0af0*/ ISETP.NE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x004fda0003f05270 */
/*0b00*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b10*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x001fe400078e00ff */
/*0b20*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*0b30*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101906 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
cudaMallocManaged(&adj, n * n * sizeof(int));
cudaMallocManaged(&idxmin, sizeof(int));
cudaMallocManaged(&minval, sizeof(int));
cudaMallocManaged(&min_edge, n * sizeof(pair<int, int>));
cudaMallocManaged(&result, n * sizeof(pair<int, int>));
cudaMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
cudaDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
cudaFree(adj);
cudaFree(idxmin);
cudaFree(minval);
cudaFree(min_edge);
cudaFree(result);
cudaFree(visited);
return 0;
} | .file "tmpxft_00116cd0_00000000-6_MST_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.globl _Z3cmpSt4pairIiiES0_
.type _Z3cmpSt4pairIiiES0_, @function
_Z3cmpSt4pairIiiES0_:
.LFB3924:
.cfi_startproc
endbr64
cmpl %esi, %edi
setl %al
je .L4
.L1:
ret
.L4:
sarq $32, %rdi
sarq $32, %rsi
cmpl %esi, %edi
setl %al
ret
.cfi_endproc
.LFE3924:
.size _Z3cmpSt4pairIiiES0_, .-_Z3cmpSt4pairIiiES0_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3928:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3928:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_
.type _Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_, @function
_Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_:
.LFB3950:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9reduceMiniPSt4pairIiiEPbPiS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_, .-_Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_
.globl _Z9reduceMiniPSt4pairIiiEPbPiS3_
.type _Z9reduceMiniPSt4pairIiiEPbPiS3_, @function
_Z9reduceMiniPSt4pairIiiEPbPiS3_:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _Z9reduceMiniPSt4pairIiiEPbPiS3_, .-_Z9reduceMiniPSt4pairIiiEPbPiS3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z9reduceMiniPSt4pairIiiEPbPiS3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduceMiniPSt4pairIiiEPbPiS3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_,"axG",@progbits,_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_,comdat
.weak _ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_
.type _ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_, @function
_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_:
.LFB4596:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbp
movl (%rdi), %r12d
movl 4(%rdi), %r14d
leaq -8(%rdi), %rbx
movq %r14, %r13
salq $32, %r13
jmp .L18
.L19:
movl (%rbx), %eax
movl %eax, 8(%rbx)
movl 4(%rbx), %eax
movl %eax, 12(%rbx)
subq $8, %rbx
.L18:
movl %r12d, %edi
orq %r13, %rdi
movq (%rbx), %rsi
call *%rbp
testb %al, %al
jne .L19
movl %r12d, 8(%rbx)
movl %r14d, 12(%rbx)
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4596:
.size _ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_, .-_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_
.section .text._ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_,"axG",@progbits,_ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_,comdat
.weak _ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_
.type _ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_, @function
_ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_:
.LFB4560:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
je .L31
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %r13
movq %rdx, %r12
leaq 8(%rdi), %rbx
cmpq %rbx, %rsi
jne .L27
.L21:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
subq $8, %rax
movl (%rax), %edx
movl %edx, 8(%rax)
movl 4(%rax), %edx
movl %edx, 12(%rax)
cmpq %rcx, %rax
jne .L25
.L24:
movl %edi, 0(%rbp)
movl %esi, 4(%rbp)
.L26:
addq $8, %rbx
cmpq %rbx, %r13
je .L21
.L27:
movq 0(%rbp), %rsi
movq (%rbx), %rdi
call *%r12
testb %al, %al
je .L23
movl (%rbx), %edi
movl 4(%rbx), %esi
movq %rbx, %rdx
subq %rbp, %rdx
movq %rdx, %rax
sarq $3, %rax
testq %rdx, %rdx
jle .L24
negq %rax
leaq (%rbx,%rax,8), %rcx
movq %rbx, %rax
jmp .L25
.L23:
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_
jmp .L26
.L31:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE4560:
.size _ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_, .-_ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_
.section .text._ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_,comdat
.weak _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
.type _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_, @function
_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_:
.LFB4622:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, 16(%rsp)
movq %rdx, %r15
movq %rcx, 8(%rsp)
movq %r8, %r14
leaq -1(%rdx), %rax
movq %rax, %r13
shrq $63, %r13
addq %rax, %r13
sarq %r13
cmpq %r13, %rsi
jge .L35
movq %rsi, %r12
jmp .L37
.L43:
movq %rbx, %r12
.L37:
leaq 1(%r12), %rax
leaq (%rax,%rax), %rbx
salq $4, %rax
movq -8(%rbp,%rax), %rsi
movq 0(%rbp,%rax), %rdi
call *%r14
cmpb $1, %al
adcq $-1, %rbx
leaq 0(%rbp,%rbx,8), %rdx
leaq 0(%rbp,%r12,8), %rax
movl (%rdx), %ecx
movl %ecx, (%rax)
movl 4(%rdx), %edx
movl %edx, 4(%rax)
cmpq %r13, %rbx
jl .L43
testb $1, %r15b
jne .L38
.L41:
leaq -2(%r15), %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
cmpq %rbx, %rax
je .L49
.L38:
movq 8(%rsp), %rax
movl %eax, 8(%rsp)
shrq $32, %rax
movl %eax, %ecx
movl %eax, 28(%rsp)
leaq -1(%rbx), %rax
movq %rax, %r12
shrq $63, %r12
addq %rax, %r12
sarq %r12
movq 16(%rsp), %rax
cmpq %rax, %rbx
jle .L39
movq %rcx, %r15
salq $32, %r15
jmp .L40
.L45:
movq 16(%rsp), %rbx
jmp .L41
.L49:
leaq 1(%rbx), %rax
movq %rax, %rdx
salq $4, %rdx
leaq -8(%rbp,%rdx), %rcx
leaq 0(%rbp,%rbx,8), %rdx
movl (%rcx), %esi
movl %esi, (%rdx)
movl 4(%rcx), %ecx
movl %ecx, 4(%rdx)
leaq -1(%rax,%rax), %rbx
jmp .L38
.L44:
movq %rax, %r12
.L40:
leaq 0(%rbp,%r12,8), %r13
movl 8(%rsp), %esi
orq %r15, %rsi
movq 0(%r13), %rdi
call *%r14
testb %al, %al
je .L39
leaq 0(%rbp,%rbx,8), %rax
movl 0(%r13), %edx
movl %edx, (%rax)
movl 4(%r13), %edx
movl %edx, 4(%rax)
leaq -1(%r12), %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
movq %r12, %rbx
cmpq %r12, 16(%rsp)
jl .L44
.L39:
leaq 0(%rbp,%rbx,8), %rax
movl 8(%rsp), %ecx
movl %ecx, (%rax)
movl 28(%rsp), %ecx
movl %ecx, 4(%rax)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
testb $1, %dl
je .L45
movq 8(%rsp), %rax
movl %eax, 8(%rsp)
shrq $32, %rax
movl %eax, 28(%rsp)
movq 16(%rsp), %rbx
jmp .L39
.cfi_endproc
.LFE4622:
.size _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_, .-_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
.section .text._ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
.type _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_, @function
_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_:
.LFB4496:
.cfi_startproc
endbr64
movq %rsi, %rax
subq %rdi, %rax
cmpq $128, %rax
jle .L79
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %r12
testq %rdx, %rdx
jne .L53
movq %r13, %rbx
.L71:
sarq $3, %rax
movq %rax, %r13
leaq -2(%rax), %rax
movq %rax, %r14
shrq $63, %r14
addq %rax, %r14
sarq %r14
jmp .L57
.L79:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.L54:
.cfi_def_cfa_offset 80
.cfi_offset 3, -56
.cfi_offset 6, -48
.cfi_offset 12, -40
.cfi_offset 13, -32
.cfi_offset 14, -24
.cfi_offset 15, -16
subq $1, %r14
.L57:
movq 0(%rbp,%r14,8), %rcx
movq %r12, %r8
movq %r13, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
testq %r14, %r14
jne .L54
movq %rbx, %rax
subq %rbp, %rax
cmpq $8, %rax
jle .L50
.L55:
subq $8, %rbx
movq (%rbx), %rcx
movl 0(%rbp), %eax
movl %eax, (%rbx)
movl 4(%rbp), %eax
movl %eax, 4(%rbx)
movq %rbx, %r13
subq %rbp, %r13
movq %r13, %rdx
sarq $3, %rdx
movq %r12, %r8
movl $0, %esi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
cmpq $8, %r13
jg .L55
.L50:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
movq 8(%rsp), %rax
movq (%rax), %rsi
movq 8(%rbp), %rdi
call *%r12
testb %al, %al
je .L61
movl 0(%rbp), %eax
movl -8(%r13), %edx
movl %edx, 0(%rbp)
movl %eax, -8(%r13)
movl 4(%rbp), %eax
movl -4(%r13), %edx
movl %edx, 4(%rbp)
movl %eax, -4(%r13)
jmp .L60
.L61:
movl 0(%rbp), %eax
movl 8(%rbp), %edx
movl %edx, 0(%rbp)
movl %eax, 8(%rbp)
movl 4(%rbp), %eax
movl 12(%rbp), %edx
movl %edx, 4(%rbp)
movl %eax, 12(%rbp)
jmp .L60
.L58:
movq -8(%r13), %rsi
movq 8(%rbp), %rdi
call *%r12
testb %al, %al
je .L62
movl 0(%rbp), %eax
movl 8(%rbp), %edx
movl %edx, 0(%rbp)
movl %eax, 8(%rbp)
movl 4(%rbp), %eax
movl 12(%rbp), %edx
movl %edx, 4(%rbp)
movl %eax, 12(%rbp)
jmp .L60
.L62:
movq 8(%rsp), %rax
movq (%rax), %rsi
movq (%r15), %rdi
call *%r12
testb %al, %al
je .L63
movl 0(%rbp), %eax
movl -8(%r13), %edx
movl %edx, 0(%rbp)
movl %eax, -8(%r13)
movl 4(%rbp), %eax
movl -4(%r13), %edx
movl %edx, 4(%rbp)
movl %eax, -4(%r13)
jmp .L60
.L63:
movl 0(%rbp), %eax
movl (%r15), %edx
movl %edx, 0(%rbp)
movl %eax, (%r15)
movl 4(%rbp), %eax
movl 4(%r15), %edx
movl %edx, 4(%rbp)
movl %eax, 4(%r15)
jmp .L60
.L65:
addq $8, %rbx
.L64:
movq 0(%rbp), %rsi
movq (%rbx), %rdi
call *%r12
testb %al, %al
jne .L65
subq $8, %r15
jmp .L66
.L67:
subq $8, %r15
.L66:
movq (%r15), %rsi
movq 0(%rbp), %rdi
call *%r12
testb %al, %al
jne .L67
cmpq %r15, %rbx
jnb .L80
movl (%rbx), %eax
movl (%r15), %edx
movl %edx, (%rbx)
movl %eax, (%r15)
movl 4(%rbx), %eax
movl 4(%r15), %edx
movl %edx, 4(%rbx)
movl %eax, 4(%r15)
addq $8, %rbx
jmp .L64
.L80:
movq %r12, %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
movq %rbx, %rax
subq %rbp, %rax
cmpq $128, %rax
jle .L50
testq %r14, %r14
je .L71
movq %rbx, %r13
.L53:
subq $1, %r14
movq %rax, %rdx
sarq $3, %rdx
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 0(%rbp,%rax,8), %r15
leaq -8(%r13), %rax
movq %rax, 8(%rsp)
leaq 8(%rbp), %rbx
movq (%r15), %rsi
movq 8(%rbp), %rdi
call *%r12
testb %al, %al
je .L58
movq -8(%r13), %rsi
movq (%r15), %rdi
call *%r12
testb %al, %al
je .L59
movl 0(%rbp), %eax
movl (%r15), %edx
movl %edx, 0(%rbp)
movl %eax, (%r15)
movl 4(%rbp), %eax
movl 4(%r15), %edx
movl %edx, 4(%rbp)
movl %eax, 4(%r15)
.L60:
movq %r13, %r15
jmp .L64
.cfi_endproc
.LFE4496:
.size _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_, .-_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Waktu Eksekusi: "
.LC2:
.string " ms\n"
.text
.globl main
.type main, @function
main:
.LFB3925:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 12(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movslq 12(%rsp), %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movslq 12(%rsp), %rsi
salq $3, %rsi
leaq 48(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movslq 12(%rsp), %rsi
leaq 56(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl $0, %r13d
leaq _ZSt3cin(%rip), %r12
cmpl $0, 12(%rsp)
jg .L82
.L83:
movq 40(%rsp), %rax
movl $0, (%rax)
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .L87
movl $0, %ebp
movl $0, %ebx
movl $0, %r13d
jmp .L93
.L84:
addl $1, %ebx
movl 12(%rsp), %eax
cmpl %ebx, %eax
jle .L86
.L85:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
movl %ebp, %eax
imull 12(%rsp), %eax
addl %ebx, %eax
cltq
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rax
cmpl $-1, (%rax)
jne .L84
movl $1000000007, (%rax)
jmp .L84
.L86:
movq 56(%rsp), %rax
movb $0, (%rax,%r13)
movq 40(%rsp), %rax
movl $1000000007, (%rax,%r13,8)
movq 40(%rsp), %rax
movl $-1, 4(%rax,%r13,8)
addq $1, %r13
cmpl %r13d, 12(%rsp)
jle .L83
.L82:
movl %r13d, %ebp
movl 12(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L85
jmp .L86
.L119:
movq 24(%rsp), %r8
movq 32(%rsp), %rcx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movl 12(%rsp), %edi
call _Z46__device_stub__Z9reduceMiniPSt4pairIiiEPbPiS3_iPSt4pairIiiEPbPiS3_
jmp .L88
.L91:
movl 12(%rsp), %eax
addq $1, %rdx
cmpl %edx, %eax
jle .L90
.L92:
imull %edi, %eax
addl %edx, %eax
cltq
movq 16(%rsp), %rcx
movl (%rcx,%rax,4), %esi
leaq 0(,%rdx,8), %rax
movq %rax, %rcx
addq 40(%rsp), %rcx
cmpl (%rcx), %esi
jge .L91
movl %esi, (%rcx)
movq 40(%rsp), %rcx
movl %edi, 4(%rcx,%rax)
jmp .L91
.L90:
addl $1, %ebp
movl 12(%rsp), %eax
cmpl %ebp, %eax
jle .L118
.L93:
movq 24(%rsp), %rdx
movl $-1, (%rdx)
movq 32(%rsp), %rdx
movl $1000000007, (%rdx)
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
leal 510(%rax), %edx
addl $255, %eax
cmovs %edx, %eax
sarl $8, %eax
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L88:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movl (%rax), %edi
movslq %edi, %rax
movq 56(%rsp), %rdx
movb $1, (%rdx,%rax)
salq $3, %rax
movq %rax, %rdx
addq 40(%rsp), %rdx
addl (%rdx), %r13d
movl %r13d, %r12d
movl 4(%rdx), %edx
cmpl $-1, %edx
je .L89
movslq %ebx, %rcx
cmpl %edi, %edx
cmovg %edi, %edx
movq 48(%rsp), %rsi
movl %edx, (%rsi,%rcx,8)
movq 40(%rsp), %rdx
movl 4(%rdx,%rax), %eax
cmpl %edi, %eax
cmovl %edi, %eax
movq 48(%rsp), %rdx
movl %eax, 4(%rdx,%rcx,8)
addl $1, %ebx
.L89:
movl 12(%rsp), %eax
testl %eax, %eax
jle .L90
movl $0, %edx
jmp .L92
.L118:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %r14
movslq %ebx, %rbp
salq $3, %rbp
leaq (%r14,%rbp), %r13
cmpq %r13, %r14
je .L94
movq %rbp, %rdx
sarq $3, %rdx
movl $64, %eax
je .L95
bsrq %rdx, %rax
xorl $63, %eax
.L95:
leaq _Z3cmpSt4pairIiiES0_(%rip), %r15
movl $63, %edx
subl %eax, %edx
movslq %edx, %rdx
addq %rdx, %rdx
movq %r15, %rcx
movq %r13, %rsi
movq %r14, %rdi
call _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
cmpq $128, %rbp
jle .L96
leaq 128(%r14), %rbp
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_
cmpq %rbp, %r13
je .L94
movq %r15, %r14
.L98:
movq %r14, %rsi
movq %rbp, %rdi
call _ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_
addq $8, %rbp
cmpq %rbp, %r13
jne .L98
jmp .L94
.L96:
movq %r15, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_
.L94:
movl %r12d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
testl %ebx, %ebx
jle .L99
movslq %ebx, %rbx
leaq 0(,%rbx,8), %r12
movl $0, %ebp
leaq _ZSt4cout(%rip), %r13
jmp .L104
.L100:
movl $45, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L101
.L102:
movl $10, %esi
call _ZNSo3putEc@PLT
.L103:
addq $8, %rbp
cmpq %r12, %rbp
je .L99
.L104:
movq 48(%rsp), %rax
movl (%rax,%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $45, 68(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L100
leaq 68(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L101:
movq 48(%rsp), %rax
movl 4(%rax,%rbp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $10, 68(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L102
leaq 68(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L103
.L87:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
.L99:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 80(%rsp), %rcx
subq 96(%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 88(%rsp), %rsi
subq 104(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
leaq (%rcx,%rdx), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L120
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L120:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3925:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
cudaMallocManaged(&adj, n * n * sizeof(int));
cudaMallocManaged(&idxmin, sizeof(int));
cudaMallocManaged(&minval, sizeof(int));
cudaMallocManaged(&min_edge, n * sizeof(pair<int, int>));
cudaMallocManaged(&result, n * sizeof(pair<int, int>));
cudaMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
cudaDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
cudaFree(adj);
cudaFree(idxmin);
cudaFree(minval);
cudaFree(min_edge);
cudaFree(result);
cudaFree(visited);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
hipMallocManaged(&adj, n * n * sizeof(int));
hipMallocManaged(&idxmin, sizeof(int));
hipMallocManaged(&minval, sizeof(int));
hipMallocManaged(&min_edge, n * sizeof(pair<int, int>));
hipMallocManaged(&result, n * sizeof(pair<int, int>));
hipMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
hipDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
hipFree(adj);
hipFree(idxmin);
hipFree(minval);
hipFree(min_edge);
hipFree(result);
hipFree(visited);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
hipMallocManaged(&adj, n * n * sizeof(int));
hipMallocManaged(&idxmin, sizeof(int));
hipMallocManaged(&minval, sizeof(int));
hipMallocManaged(&min_edge, n * sizeof(pair<int, int>));
hipMallocManaged(&result, n * sizeof(pair<int, int>));
hipMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
hipDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
hipFree(adj);
hipFree(idxmin);
hipFree(minval);
hipFree(min_edge);
hipFree(result);
hipFree(visited);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reduceMiniPSt4pairIiiEPbPiS3_
.globl _Z9reduceMiniPSt4pairIiiEPbPiS3_
.p2align 8
.type _Z9reduceMiniPSt4pairIiiEPbPiS3_,@function
_Z9reduceMiniPSt4pairIiiEPbPiS3_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v8, 0x3b9aca07
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
v_mov_b32_e32 v0, -1
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v0, -1
v_mov_b32_e32 v8, 0x3b9aca07
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[8:9], 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, s8, v2
v_add_co_u32 v4, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v2
v_add_co_u32 v6, s2, v6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v7, s2, s7, v7, s2
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_9
.LBB0_4:
global_load_u8 v1, v[4:5], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v1
s_cbranch_execz .LBB0_3
v_cmp_eq_u32_e64 s12, -1, v0
s_mov_b32 s13, exec_lo
v_cmpx_ne_u32_e32 -1, v0
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
s_and_not1_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[0:1]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v1, v[6:7], off
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v3
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s14
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s12
s_cbranch_execz .LBB0_2
global_load_b32 v8, v[6:7], off
v_mov_b32_e32 v0, v2
s_branch .LBB0_2
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
s_mov_b32 s2, exec_lo
s_brev_b32 s4, -2
.LBB0_11:
s_ctz_i32_b32 s3, s2
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v8, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s3
s_min_i32 s4, s4, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_11
s_load_b64 s[2:3], s[0:1], 0x18
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4
s_waitcnt lgkmcnt(0)
global_atomic_min_i32 v1, v2, s[2:3]
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v2, v8
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reduceMiniPSt4pairIiiEPbPiS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reduceMiniPSt4pairIiiEPbPiS3_, .Lfunc_end0-_Z9reduceMiniPSt4pairIiiEPbPiS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reduceMiniPSt4pairIiiEPbPiS3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reduceMiniPSt4pairIiiEPbPiS3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <utility>
#include <algorithm>
#include <sys/time.h>
using namespace std;
const int INF = 1e9 + 7;
bool cmp(pair<int, int> a, pair<int, int> b) {
if(a.first == b.first) {
return a.second < b.second;
} else {
return a.first < b.first;
}
}
__global__
void reduceMin(int n ,pair<int, int> *min_edge, bool *visited, int* minval, int* idxmin)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int localmin = INF;
int localidxmin = -1;
for(int j = index; j < n; j += stride) {
if(visited[j] == 0 && (localidxmin == -1 || min_edge[j].first < min_edge[localidxmin].first)) {
localidxmin = j;
localmin = min_edge[j].first;
}
}
atomicMin(minval, localmin);
__syncthreads();
if(*minval == localmin) {
*idxmin = localidxmin;
}
}
int main(){
int n;
cin >> n;
int *adj, *idxmin, *minval;
pair<int, int> *min_edge, *result;
bool *visited;
hipMallocManaged(&adj, n * n * sizeof(int));
hipMallocManaged(&idxmin, sizeof(int));
hipMallocManaged(&minval, sizeof(int));
hipMallocManaged(&min_edge, n * sizeof(pair<int, int>));
hipMallocManaged(&result, n * sizeof(pair<int, int>));
hipMallocManaged(&visited, n * sizeof(bool));
for(int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
cin >> adj[i * n + j];
// akses tidak bisa [][]. harus [], maka diflatten
if(adj[i * n + j] == -1) adj[i * n + j] = INF;
}
visited[i] = 0;
// first: weight, second: terhubung sama apa
min_edge[i].first = INF;
min_edge[i].second = -1;
}
int total_weight = 0;
min_edge[0].first = 0;
int cur = 0;
struct timeval stop, start;
gettimeofday(&start, NULL);
for(int i = 0; i < n; i++) {
int blockSize = 256;
int numBlocks = (n + blockSize - 1) / blockSize;
*idxmin = -1;
*minval = INF;
reduceMin<<<numBlocks, blockSize>>>(n, min_edge, visited, minval, idxmin);
hipDeviceSynchronize();
int t = *idxmin;
visited[t] = 1;
total_weight += min_edge[t].first;
if(min_edge[t].second != -1) {
result[cur].first = min(t, min_edge[t].second);
result[cur].second = max(t, min_edge[t].second);
cur++;
}
//cout << *idxmin << " this is " << *minval << '\n';
for(int to = 0; to < n; to++) {
if(adj[t * n + to] < min_edge[to].first) {
min_edge[to].first = adj[t * n + to];
min_edge[to].second = t;
}
//cout << min_edge[to].first << " - " << min_edge[to].second << '\n';
}
}
gettimeofday(&stop, NULL);
sort(result, result + cur, cmp);
cout << total_weight << '\n';
for(int i = 0; i < cur; i++) {
cout << result[i].first << '-' << result[i].second << '\n';
}
cout << "Waktu Eksekusi: " << (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000 << " ms\n";
hipFree(adj);
hipFree(idxmin);
hipFree(minval);
hipFree(min_edge);
hipFree(result);
hipFree(visited);
return 0;
} | .text
.file "MST_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z3cmpSt4pairIiiES0_ # -- Begin function _Z3cmpSt4pairIiiES0_
.p2align 4, 0x90
.type _Z3cmpSt4pairIiiES0_,@function
_Z3cmpSt4pairIiiES0_: # @_Z3cmpSt4pairIiiES0_
.cfi_startproc
# %bb.0:
movq %rsi, %rcx
shrq $32, %rcx
movq %rdi, %rdx
shrq $32, %rdx
xorl %eax, %eax
cmpl %ecx, %edx
setl %al
xorl %ecx, %ecx
cmpl %esi, %edi
setl %cl
cmovnel %ecx, %eax
# kill: def $al killed $al killed $eax
retq
.Lfunc_end0:
.size _Z3cmpSt4pairIiiES0_, .Lfunc_end0-_Z3cmpSt4pairIiiES0_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_ # -- Begin function _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_
.p2align 4, 0x90
.type _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_,@function
_Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_: # @_Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reduceMiniPSt4pairIiiEPbPiS3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_, .Lfunc_end1-_Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 4(%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 56(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 48(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 64(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
cmpl $0, 4(%rsp)
jle .LBB2_8
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
movabsq $-3294967289, %r14 # imm = 0xFFFFFFFF3B9ACA07
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 40(%rsp), %rax
movb $0, (%rax,%rbx)
movq 16(%rsp), %rax
movq %r14, (%rax,%rbx,8)
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jge .LBB2_8
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB2_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movslq %ebx, %r15
xorl %r12d, %r12d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
movl 4(%rsp), %eax
incq %r12
cmpl %eax, %r12d
jge .LBB2_7
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %r15d, %eax
movslq %eax, %rsi
addq %r12, %rsi
shlq $2, %rsi
addq 56(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq 56(%rsp), %rax
movslq 4(%rsp), %rcx
imulq %r15, %rcx
addq %r12, %rcx
cmpl $-1, (%rax,%rcx,4)
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl $1000000007, (%rax,%rcx,4) # imm = 0x3B9ACA07
jmp .LBB2_6
.LBB2_8: # %._crit_edge120
movq 16(%rsp), %rax
movl $0, (%rax)
xorl %r12d, %r12d
leaq 184(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %edi
movl $0, %ebx
testl %edi, %edi
jle .LBB2_20
# %bb.9: # %.lr.ph129
xorl %ebx, %ebx
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 256(%r13), %r14
leaq 144(%rsp), %r15
xorl %r12d, %r12d
xorl %ebp, %ebp
jmp .LBB2_10
.p2align 4, 0x90
.LBB2_19: # %._crit_edge124
# in Loop: Header=BB2_10 Depth=1
incl %ebp
movl 4(%rsp), %edi
cmpl %edi, %ebp
jge .LBB2_20
.LBB2_10: # =>This Loop Header: Depth=1
# Child Loop BB2_16 Depth 2
leal 255(%rdi), %eax
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movq 48(%rsp), %rax
movl $-1, (%rax)
movq 64(%rsp), %rax
movl $1000000007, (%rax) # imm = 0x3B9ACA07
orq %r13, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11: # in Loop: Header=BB2_10 Depth=1
movl 4(%rsp), %eax
movq 16(%rsp), %rcx
movq 40(%rsp), %rdx
movq 64(%rsp), %rsi
movq 48(%rsp), %rdi
movl %eax, 76(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z9reduceMiniPSt4pairIiiEPbPiS3_, %edi
movq %r15, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12: # in Loop: Header=BB2_10 Depth=1
callq hipDeviceSynchronize
movq 48(%rsp), %rax
movslq (%rax), %rax
movq 40(%rsp), %rcx
movb $1, (%rcx,%rax)
movq 16(%rsp), %rcx
addl (%rcx,%rax,8), %ebx
movl 4(%rcx,%rax,8), %edx
cmpl $-1, %edx
je .LBB2_14
# %bb.13: # in Loop: Header=BB2_10 Depth=1
cmpl %edx, %eax
movl %edx, %esi
cmovll %eax, %esi
movq 8(%rsp), %rdi
movslq %r12d, %r12
movl %esi, (%rdi,%r12,8)
cmovgl %eax, %edx
movl %edx, 4(%rdi,%r12,8)
incl %r12d
.LBB2_14: # in Loop: Header=BB2_10 Depth=1
movl 4(%rsp), %edi
testl %edi, %edi
jle .LBB2_19
# %bb.15: # %.lr.ph123
# in Loop: Header=BB2_10 Depth=1
movq 56(%rsp), %rdx
xorl %esi, %esi
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_16 Depth=2
incq %rsi
movslq 4(%rsp), %rdi
cmpq %rdi, %rsi
jge .LBB2_19
.LBB2_16: # Parent Loop BB2_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %eax, %edi
movslq %edi, %rdi
addq %rsi, %rdi
movl (%rdx,%rdi,4), %edi
cmpl (%rcx,%rsi,8), %edi
jge .LBB2_18
# %bb.17: # in Loop: Header=BB2_16 Depth=2
movl %edi, (%rcx,%rsi,8)
movl %eax, 4(%rcx,%rsi,8)
jmp .LBB2_18
.LBB2_20: # %._crit_edge130
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r12d, %r12d
je .LBB2_50
# %bb.21:
movq 8(%rsp), %r14
movslq %r12d, %rax
leaq (%r14,%rax,8), %r15
bsrq %rax, %rax
xorl $63, %eax
addl %eax, %eax
movl $126, %edx
subq %rax, %rdx
movl $_Z3cmpSt4pairIiiES0_, %ecx
movq %r14, %rdi
movq %r15, %rsi
callq _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
cmpl $17, %r12d
jl .LBB2_38
# %bb.22:
leaq 8(%r14), %rax
movl $8, %ecx
movl $2, %edx
movq %r14, %r9
jmp .LBB2_23
.p2align 4, 0x90
.LBB2_30: # %_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_.exit.i.i
# in Loop: Header=BB2_23 Depth=1
movl %edi, (%r9)
movl %r8d, 4(%r9)
.LBB2_31: # in Loop: Header=BB2_23 Depth=1
addq $8, %rcx
addq $8, %rax
incq %rdx
movq %rsi, %r9
cmpq $128, %rcx
je .LBB2_32
.LBB2_23: # =>This Loop Header: Depth=1
# Child Loop BB2_29 Depth 2
# Child Loop BB2_25 Depth 2
leaq (%r14,%rcx), %rsi
movl (%r14,%rcx), %edi
movl 12(%r9), %r8d
xorl %r10d, %r10d
cmpl 4(%r14), %r8d
setl %r10b
xorl %r8d, %r8d
cmpl (%r14), %edi
setl %r8b
cmovel %r10d, %r8d
movq (%r14,%rcx), %rdi
cmpb $1, %r8b
jne .LBB2_27
# %bb.24: # %.lr.ph.i.i.i.i.i.preheader.i.i
# in Loop: Header=BB2_23 Depth=1
movq %rdi, %r8
shrq $32, %r8
movq %rdx, %r9
.p2align 4, 0x90
.LBB2_25: # %.lr.ph.i.i.i.i.i.i.i
# Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
movq -16(%r14,%r9,8), %r10
movq %r10, -8(%r14,%r9,8)
decq %r9
cmpq $1, %r9
jg .LBB2_25
# %bb.26: # %_ZSt13move_backwardIPSt4pairIiiES2_ET0_T_S4_S3_.exit.i.i
# in Loop: Header=BB2_23 Depth=1
movl %edi, (%r14)
movl %r8d, 4(%r14)
jmp .LBB2_31
.p2align 4, 0x90
.LBB2_27: # in Loop: Header=BB2_23 Depth=1
movq %rdi, %r8
shrq $32, %r8
xorl %r10d, %r10d
cmpl %r8d, 4(%r9)
setg %r10b
xorl %r11d, %r11d
cmpl %edi, (%r9)
setg %r11b
cmovnel %r11d, %r10d
movq %rsi, %r9
cmpb $1, %r10b
jne .LBB2_30
# %bb.28: # %.lr.ph.i.i.i.preheader
# in Loop: Header=BB2_23 Depth=1
movq %rax, %r10
.p2align 4, 0x90
.LBB2_29: # %.lr.ph.i.i.i
# Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
leaq -8(%r10), %r9
movq -8(%r10), %r11
movq %r11, (%r10)
xorl %r11d, %r11d
cmpl %r8d, -12(%r10)
setg %r11b
xorl %ebp, %ebp
cmpl %edi, -16(%r10)
setg %bpl
cmovel %r11d, %ebp
movq %r9, %r10
testb %bpl, %bpl
jne .LBB2_29
jmp .LBB2_30
.LBB2_38: # %.preheader.i
cmpl $1, %r12d
jne .LBB2_39
.LBB2_50: # %_ZSt4sortIPSt4pairIiiEPFbS1_S1_EEvT_S5_T0_.exit
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movb $10, 24(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_52
# %bb.51:
leaq 24(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r12d, %r12d
jg .LBB2_54
jmp .LBB2_62
.LBB2_52:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
testl %r12d, %r12d
jle .LBB2_62
.LBB2_54: # %.lr.ph133.preheader
movl %r12d, %r15d
xorl %r12d, %r12d
leaq 24(%rsp), %rbx
jmp .LBB2_55
.p2align 4, 0x90
.LBB2_59: # in Loop: Header=BB2_55 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_61: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit67
# in Loop: Header=BB2_55 Depth=1
incq %r12
cmpq %r12, %r15
je .LBB2_62
.LBB2_55: # %.lr.ph133
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r12,8), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $45, 24(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_57
# %bb.56: # in Loop: Header=BB2_55 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB2_58
.p2align 4, 0x90
.LBB2_57: # in Loop: Header=BB2_55 Depth=1
movq %rax, %r14
movq %rax, %rdi
movl $45, %esi
callq _ZNSo3putEc
movq %r14, %rdi
.LBB2_58: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit64
# in Loop: Header=BB2_55 Depth=1
movq 8(%rsp), %rax
movl 4(%rax,%r12,8), %esi
callq _ZNSolsEi
movb $10, 24(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB2_59
# %bb.60: # in Loop: Header=BB2_55 Depth=1
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB2_61
.LBB2_62: # %._crit_edge134
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 144(%rsp), %rcx
movq 152(%rsp), %rax
subq 184(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 192(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_32: # %_ZSt16__insertion_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_.exit.i
.cfi_def_cfa_offset 256
leaq 128(%r14), %rax
addq $132, %r14
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_37: # %_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_.exit.i15.i
# in Loop: Header=BB2_33 Depth=1
movl %ecx, (%rsi)
movl %edx, 4(%rsi)
addq $8, %rax
addq $8, %r14
cmpq %r15, %rax
je .LBB2_50
.LBB2_33: # %.lr.ph.i.i
# =>This Loop Header: Depth=1
# Child Loop BB2_35 Depth 2
movq (%rax), %rcx
movq %rcx, %rdx
shrq $32, %rdx
xorl %edi, %edi
cmpl %edx, -4(%rax)
setg %dil
xorl %esi, %esi
cmpl %ecx, -8(%rax)
setg %sil
cmovnel %esi, %edi
movq %rax, %rsi
cmpb $1, %dil
jne .LBB2_37
# %bb.34: # %.lr.ph.i.i21.i.preheader
# in Loop: Header=BB2_33 Depth=1
movq %r14, %rsi
.p2align 4, 0x90
.LBB2_35: # %.lr.ph.i.i21.i
# Parent Loop BB2_33 Depth=1
# => This Inner Loop Header: Depth=2
movq -12(%rsi), %rdi
movq %rdi, -4(%rsi)
xorl %edi, %edi
cmpl %edx, -16(%rsi)
setg %dil
xorl %r8d, %r8d
cmpl %ecx, -20(%rsi)
leaq -8(%rsi), %rsi
setg %r8b
cmovel %edi, %r8d
testb %r8b, %r8b
jne .LBB2_35
# %bb.36: # %_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_.exit.i15.i.loopexit
# in Loop: Header=BB2_33 Depth=1
addq $-4, %rsi
jmp .LBB2_37
.LBB2_39: # %.lr.ph.i
leaq 8(%r14), %rax
movq %r14, %rcx
jmp .LBB2_40
.p2align 4, 0x90
.LBB2_48: # %_ZSt25__unguarded_linear_insertIPSt4pairIiiEN9__gnu_cxx5__ops14_Val_comp_iterIPFbS1_S1_EEEEvT_T0_.exit.i
# in Loop: Header=BB2_40 Depth=1
movl %edx, (%rdi)
movl %esi, 4(%rdi)
.LBB2_49: # in Loop: Header=BB2_40 Depth=1
addq $8, %rax
addq $8, %rcx
cmpq %r15, %rax
je .LBB2_50
.LBB2_40: # =>This Loop Header: Depth=1
# Child Loop BB2_47 Depth 2
# Child Loop BB2_43 Depth 2
movl (%rax), %edx
movl 12(%rcx), %esi
xorl %edi, %edi
cmpl 4(%r14), %esi
setl %dil
xorl %esi, %esi
cmpl (%r14), %edx
setl %sil
cmovel %edi, %esi
movq (%rax), %rdx
cmpb $1, %sil
jne .LBB2_45
# %bb.41: # in Loop: Header=BB2_40 Depth=1
movq %rax, %rsi
subq %r14, %rsi
sarq $3, %rsi
testq %rsi, %rsi
jle .LBB2_44
# %bb.42: # %.lr.ph.i.i.i.i.i.preheader.i
# in Loop: Header=BB2_40 Depth=1
movl $1, %edi
.p2align 4, 0x90
.LBB2_43: # %.lr.ph.i.i.i.i.i.i
# Parent Loop BB2_40 Depth=1
# => This Inner Loop Header: Depth=2
movq -8(%rcx,%rdi,8), %r8
movq %r8, (%rcx,%rdi,8)
leaq (%rsi,%rdi), %r8
decq %r8
decq %rdi
cmpq $1, %r8
jg .LBB2_43
.LBB2_44: # %_ZSt13move_backwardIPSt4pairIiiES2_ET0_T_S4_S3_.exit.i
# in Loop: Header=BB2_40 Depth=1
movq %rdx, %rsi
shrq $32, %rsi
movl %edx, (%r14)
movl %esi, 4(%r14)
jmp .LBB2_49
.p2align 4, 0x90
.LBB2_45: # in Loop: Header=BB2_40 Depth=1
movq %rdx, %rsi
shrq $32, %rsi
xorl %r8d, %r8d
cmpl %esi, 4(%rcx)
setg %r8b
xorl %edi, %edi
cmpl %edx, (%rcx)
setg %dil
cmovnel %edi, %r8d
movq %rax, %rdi
cmpb $1, %r8b
jne .LBB2_48
# %bb.46: # %.lr.ph.i.i72.preheader
# in Loop: Header=BB2_40 Depth=1
movq %rax, %r8
.p2align 4, 0x90
.LBB2_47: # %.lr.ph.i.i72
# Parent Loop BB2_40 Depth=1
# => This Inner Loop Header: Depth=2
leaq -8(%r8), %rdi
movq -8(%r8), %r9
movq %r9, (%r8)
xorl %r9d, %r9d
cmpl %esi, -12(%r8)
setg %r9b
xorl %r10d, %r10d
cmpl %edx, -16(%r8)
setg %r10b
cmovel %r9d, %r10d
movq %rdi, %r8
testb %r10b, %r10b
jne .LBB2_47
jmp .LBB2_48
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_ # -- Begin function _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
.p2align 4, 0x90
.type _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_,@function
_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_: # @_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
subq %rdi, %r13
cmpq $129, %r13
jl .LBB3_15
# %bb.1: # %.lr.ph
movq %rcx, %rbx
movq %rdx, %r12
movq %rsi, %rbp
movq %rdi, %r14
leaq 8(%rdi), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq $-8, %rax
subq %rdi, %rax
movq %rax, 32(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_14: # %_ZSt27__unguarded_partition_pivotIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEET_S9_S9_T0_.exit
# in Loop: Header=BB3_2 Depth=1
movq %r15, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq 24(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movq %rbx, %rcx
callq _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
movq %r15, %rbp
cmpq $128, %r13
jle .LBB3_15
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
# Child Loop BB3_9 Depth 3
# Child Loop BB3_11 Depth 3
subq $1, %r12
movq %rbp, 8(%rsp) # 8-byte Spill
jb .LBB3_3
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movq %r12, 24(%rsp) # 8-byte Spill
shrq $4, %r13
leaq (%r14,%r13,8), %rdx
leaq -8(%rbp), %rcx
movq %r14, %rdi
movq 16(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %rbx, %r8
callq _ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_9 Depth 3
# Child Loop BB3_11 Depth 3
movq 32(%rsp), %rax # 8-byte Reload
leaq (%rax,%r12), %r13
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_8 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r12), %rdi
movq (%r14), %rsi
callq *%rbx
addq $8, %r12
addq $8, %r13
testb %al, %al
jne .LBB3_9
# %bb.10: # %.preheader.i.i.preheader
# in Loop: Header=BB3_8 Depth=2
leaq -8(%r12), %r15
.p2align 4, 0x90
.LBB3_11: # %.preheader.i.i
# Parent Loop BB3_2 Depth=1
# Parent Loop BB3_8 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r14), %rdi
movq -8(%rbp), %rsi
addq $-8, %rbp
callq *%rbx
testb %al, %al
jne .LBB3_11
# %bb.12: # in Loop: Header=BB3_8 Depth=2
cmpq %rbp, %r15
jae .LBB3_14
# %bb.13: # in Loop: Header=BB3_8 Depth=2
movl -8(%r12), %eax
movl (%rbp), %ecx
movl %ecx, -8(%r12)
movl %eax, (%rbp)
movl -4(%r12), %eax
movl 4(%rbp), %ecx
movl %ecx, -4(%r12)
movl %eax, 4(%rbp)
jmp .LBB3_8
.LBB3_3:
shrq $3, %r13
leaq -2(%r13), %r15
shrq %r15
xorl %r12d, %r12d
movq %r15, %rbp
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rcx
movq %r14, %rdi
movq %r15, %rsi
movq %r13, %rdx
movq %rbx, %r8
callq _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
subq $1, %rbp
cmovbq %r12, %rbp
testq %r15, %r15
movq %rbp, %r15
jne .LBB3_4
# %bb.5: # %.lr.ph.i5.i
movq 8(%rsp), %r12 # 8-byte Reload
leaq -8(%r12), %r15
subq %r14, %r12
.p2align 4, 0x90
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq (%r15), %rcx
movl (%r14), %eax
movl %eax, (%r15)
movl 4(%r14), %eax
movl %eax, 4(%r15)
addq $-8, %r12
movq %r12, %rdx
sarq $3, %rdx
movq %r14, %rdi
xorl %esi, %esi
movq %rbx, %r8
callq _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
addq $-8, %r15
cmpq $8, %r12
jg .LBB3_6
.LBB3_15: # %_ZSt14__partial_sortIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_T0_.exit
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_, .Lfunc_end3-_ZSt16__introsort_loopIPSt4pairIiiElN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_T0_T1_
.cfi_endproc
# -- End function
.section .text._ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_,comdat
.weak _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_ # -- Begin function _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
.p2align 4, 0x90
.type _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_,@function
_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_: # @_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movq %rcx, 16(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %r14
leaq -1(%rdx), %rax
shrq $63, %rax
movq %rdx, 8(%rsp) # 8-byte Spill
leaq (%rdx,%rax), %rbx
decq %rbx
sarq %rbx
movq %rsi, %r12
cmpq %rsi, %rbx
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
movq %r13, %rbp
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# in Loop: Header=BB4_4 Depth=1
leaq 2(,%rbp,2), %r12
.LBB4_3: # %.lr.ph
# in Loop: Header=BB4_4 Depth=1
movl (%r14,%r12,8), %eax
movl %eax, (%r14,%rbp,8)
movl 4(%r14,%r12,8), %eax
movl %eax, 4(%r14,%rbp,8)
movq %r12, %rbp
cmpq %rbx, %r12
jge .LBB4_6
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (,%rbp,2), %rax
movq 8(%r14,%rax,8), %rsi
movq 16(%r14,%rax,8), %rdi
callq *%r15
testb %al, %al
je .LBB4_2
# %bb.5: # in Loop: Header=BB4_4 Depth=1
leaq 1(,%rbp,2), %r12
jmp .LBB4_3
.LBB4_6: # %._crit_edge
movq 8(%rsp), %rax # 8-byte Reload
testb $1, %al
jne .LBB4_9
# %bb.7:
addq $-2, %rax
sarq %rax
cmpq %rax, %r12
jne .LBB4_9
# %bb.8:
leaq (%r12,%r12), %rax
movl 8(%r14,%rax,8), %ecx
movl %ecx, (%r14,%r12,8)
movl 12(%r14,%rax,8), %eax
movl %eax, 4(%r14,%r12,8)
leaq 1(,%r12,2), %r12
.LBB4_9:
cmpq %r13, %r12
movq 16(%rsp), %rbp # 8-byte Reload
jle .LBB4_13
.p2align 4, 0x90
.LBB4_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq -1(%r12), %rax
shrq $63, %rax
leaq (%r12,%rax), %rbx
decq %rbx
sarq %rbx
movq (%r14,%rbx,8), %rdi
movq %rbp, %rsi
callq *%r15
testb %al, %al
je .LBB4_13
# %bb.11: # in Loop: Header=BB4_10 Depth=1
movl (%r14,%rbx,8), %eax
movl %eax, (%r14,%r12,8)
movl 4(%r14,%rbx,8), %eax
movl %eax, 4(%r14,%r12,8)
movq %rbx, %r12
cmpq %r13, %rbx
jg .LBB4_10
jmp .LBB4_14
.LBB4_13:
movq %r12, %rbx
.LBB4_14: # %_ZSt11__push_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops14_Iter_comp_valIPFbS1_S1_EEEEvT_T0_SA_T1_RT2_.exit
movq %rbp, (%r14,%rbx,8)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_, .Lfunc_end4-_ZSt13__adjust_heapIPSt4pairIiiElS1_N9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_T0_SA_T1_T2_
.cfi_endproc
# -- End function
.section .text._ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_,"axG",@progbits,_ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_,comdat
.weak _ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_ # -- Begin function _ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_
.p2align 4, 0x90
.type _ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_,@function
_ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_: # @_ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r13
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
leaq 4(%rsi), %rax
movq %rax, 16(%rsp) # 8-byte Spill
leaq 4(%rdx), %rbp
movq (%rsi), %rdi
movq (%rdx), %rsi
callq *%r8
leaq 4(%r14), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movq (%r14), %rsi
testb %al, %al
je .LBB5_6
# %bb.1:
movq (%r15), %rdi
callq *%r13
testb %al, %al
je .LBB5_3
# %bb.2:
movl (%rbx), %eax
movl (%r15), %ecx
movl %ecx, (%rbx)
movl %eax, (%r15)
jmp .LBB5_10
.LBB5_6:
movq (%r12), %rdi
callq *%r13
testb %al, %al
je .LBB5_8
# %bb.7:
movl (%rbx), %eax
movl (%r12), %ecx
movl %ecx, (%rbx)
movl %eax, (%r12)
movq 16(%rsp), %rbp # 8-byte Reload
jmp .LBB5_10
.LBB5_3:
movq (%r12), %rdi
movq (%r14), %rsi
callq *%r13
movl (%rbx), %ecx
testb %al, %al
jne .LBB5_4
# %bb.5:
movl (%r12), %eax
movl %eax, (%rbx)
movl %ecx, (%r12)
movq 16(%rsp), %rbp # 8-byte Reload
jmp .LBB5_10
.LBB5_8:
movq (%r15), %rdi
movq (%r14), %rsi
callq *%r13
movl (%rbx), %ecx
testb %al, %al
je .LBB5_9
.LBB5_4:
movl (%r14), %eax
movl %eax, (%rbx)
movl %ecx, (%r14)
movq 8(%rsp), %rbp # 8-byte Reload
jmp .LBB5_10
.LBB5_9:
movl (%r15), %eax
movl %eax, (%rbx)
movl %ecx, (%r15)
.LBB5_10:
movl 4(%rbx), %eax
movl (%rbp), %ecx
movl %ecx, 4(%rbx)
movl %eax, (%rbp)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_, .Lfunc_end5-_ZSt22__move_median_to_firstIPSt4pairIiiEN9__gnu_cxx5__ops15_Iter_comp_iterIPFbS1_S1_EEEEvT_S9_S9_S9_T0_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reduceMiniPSt4pairIiiEPbPiS3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reduceMiniPSt4pairIiiEPbPiS3_,@object # @_Z9reduceMiniPSt4pairIiiEPbPiS3_
.section .rodata,"a",@progbits
.globl _Z9reduceMiniPSt4pairIiiEPbPiS3_
.p2align 3, 0x0
_Z9reduceMiniPSt4pairIiiEPbPiS3_:
.quad _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_
.size _Z9reduceMiniPSt4pairIiiEPbPiS3_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Waktu Eksekusi: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms\n"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reduceMiniPSt4pairIiiEPbPiS3_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z3cmpSt4pairIiiES0_
.addrsig_sym _Z24__device_stub__reduceMiniPSt4pairIiiEPbPiS3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reduceMiniPSt4pairIiiEPbPiS3_
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reduceMiniPSt4pairIiiEPbPiS3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B1, 0xa40 ; /* 0x00000a0000017945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3b9aca07 ; /* 0x3b9aca07ff027424 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R4, R9, c[0x0][0x0], R10 ; /* 0x0000000009047a24 */
/* 0x001fca00078e020a */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xa30 ; /* 0x0000099000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x850 ; /* 0x0000079000007945 */
/* 0x000fe60003800000 */
/*00c0*/ IMAD R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a24 */
/* 0x000fc800078e02ff */
/*00d0*/ I2F.U32.RP R2, R3 ; /* 0x0000000300027306 */
/* 0x000e220000209000 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*00f0*/ IADD3 R8, R3.reuse, R4, RZ ; /* 0x0000000403087210 */
/* 0x040fe40007ffe0ff */
/*0100*/ ISETP.NE.U32.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f45070 */
/*0110*/ LOP3.LUT R0, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff007212 */
/* 0x000fc800078e33ff */
/*0120*/ IADD3 R0, R0, c[0x0][0x160], R3 ; /* 0x0000580000007a10 */
/* 0x000fe20007ffe003 */
/*0130*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD R5, R5, R7, RZ ; /* 0x0000000705057224 */
/* 0x002fc800078e02ff */
/*0180*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0190*/ IMAD.HI.U32 R7, R7, R0, RZ ; /* 0x0000000007077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R2, RZ, RZ, -R7 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a07 */
/*01b0*/ IMAD R0, R3, R2, R0 ; /* 0x0000000203007224 */
/* 0x000fe200078e0200 */
/*01c0*/ HFMA2.MMA R2, -RZ, RZ, 0.9501953125, -12.0546875 ; /* 0x3b9aca07ff027435 */
/* 0x000fc800000001ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100000824 */
/* 0x000fe200078e0a03 */
/*01f0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe20003f26070 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fd800078e00ff */
/*0220*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P2 LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff07a212 */
/* 0x000fc800078e33ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x3, PT ; /* 0x000000030700780c */
/* 0x040fe40003f06070 */
/*0250*/ IADD3 R12, R7, 0x1, RZ ; /* 0x00000001070c7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ LOP3.LUT R5, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c057812 */
/* 0x000fce00078ec0ff */
/*0270*/ @!P0 BRA 0x840 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R2, 0x3b9aca07 ; /* 0x3b9aca0700027802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*02b0*/ IMAD R7, R0.reuse, 0x3, R9.reuse ; /* 0x0000000300077824 */
/* 0x140fe400078e0209 */
/*02c0*/ IMAD R9, R0, 0x2, R9 ; /* 0x0000000200097824 */
/* 0x000fe400078e0209 */
/*02d0*/ IMAD R8, R7, c[0x0][0x0], R10.reuse ; /* 0x0000000007087a24 */
/* 0x100fe400078e020a */
/*02e0*/ IMAD R10, R9, c[0x0][0x0], R10 ; /* 0x00000000090a7a24 */
/* 0x000fe200078e020a */
/*02f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R3 ; /* 0x0000001fff097819 */
/* 0x000fe20000011403 */
/*0300*/ IMAD.IADD R7, R12, 0x1, -R5 ; /* 0x000000010c077824 */
/* 0x000fc400078e0a05 */
/*0310*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe400078e00ff */
/*0320*/ SHF.R.S32.HI R11, RZ, 0x1f, R4 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011404 */
/*0330*/ IADD3 R12, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c00040c7a10 */
/* 0x000fc80007f1e0ff */
/*0340*/ IADD3.X R13, R11, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000b0d7a10 */
/* 0x000fca00007fe4ff */
/*0350*/ LDG.E.U8 R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000ea2000c1e1100 */
/*0360*/ BSSY B2, 0x460 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x004fda0003f05270 */
/*0380*/ @P0 BRA 0x450 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0390*/ LEA R14, P0, R4, c[0x0][0x168], 0x3 ; /* 0x00005a00040e7a11 */
/* 0x000fc800078018ff */
/*03a0*/ LEA.HI.X R15, R4, c[0x0][0x16c], R11, 0x3, P0 ; /* 0x00005b00040f7a11 */
/* 0x000fca00000f1c0b */
/*03b0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*03c0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x430 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x001fc800078e00ff */
/*03f0*/ IMAD.WIDE R14, R0, R15, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fcc00078e020f */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0420*/ @P0 BRA 0x450 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0440*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0450*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fc80007f1e0ff */
/*0470*/ IADD3.X R13, R9, R13, RZ, P0, !PT ; /* 0x0000000d090d7210 */
/* 0x000fca00007fe4ff */
/*0480*/ LDG.E.U8 R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000ea2000c1e1100 */
/*0490*/ BSSY B2, 0x580 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*04a0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 BRA 0x570 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE R14, R6, R17, c[0x0][0x168] ; /* 0x00005a00060e7625 */
/* 0x000fca00078e0211 */
/*04e0*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*04f0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0500*/ @!P0 BRA 0x550 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.WIDE R14, R0, R17, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x001fcc00078e0211 */
/*0520*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0540*/ @P0 BRA 0x570 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0560*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*0570*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0580*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fca0007f1e0ff */
/*0590*/ IMAD.X R13, R9, 0x1, R13, P0 ; /* 0x00000001090d7824 */
/* 0x000fca00000e060d */
/*05a0*/ LDG.E.U8 R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000ea2000c1e1100 */
/*05b0*/ BSSY B2, 0x6a0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x004fda0003f05270 */
/*05d0*/ @P0 BRA 0x690 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R17, 0x8 ; /* 0x0000000800117802 */
/* 0x000fca0000000f00 */
/*05f0*/ IMAD.WIDE R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fca00078e0211 */
/*0600*/ LDG.E R11, [R14.64] ; /* 0x000000060e0b7981 */
/* 0x000162000c1e1900 */
/*0610*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0620*/ @!P0 BRA 0x670 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.WIDE R14, R0, R17, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x001fcc00078e0211 */
/*0640*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*0650*/ ISETP.GE.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720c */
/* 0x024fda0003f06270 */
/*0660*/ @P0 BRA 0x690 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x021fe400078e000b */
/*0680*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000a */
/*0690*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*06a0*/ IADD3 R12, P0, R3, R12, RZ ; /* 0x0000000c030c7210 */
/* 0x000fca0007f1e0ff */
/*06b0*/ IMAD.X R13, R9, 0x1, R13, P0 ; /* 0x00000001090d7824 */
/* 0x000fca00000e060d */
/*06c0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ BSSY B2, 0x7c0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*06e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fda0003f05270 */
/*06f0*/ @P0 BRA 0x7b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fc800078e00ff */
/*0710*/ IMAD.WIDE R12, R8, R15, c[0x0][0x168] ; /* 0x00005a00080c7625 */
/* 0x000fca00078e020f */
/*0720*/ LDG.E R11, [R12.64] ; /* 0x000000060c0b7981 */
/* 0x000162000c1e1900 */
/*0730*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x790 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.WIDE R12, R0, R15, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x001fcc00078e020f */
/*0760*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea4000c1e1900 */
/*0770*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x024fda0003f06270 */
/*0780*/ @P0 BRA 0x7b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0790*/ MOV R2, R11 ; /* 0x0000000b00027202 */
/* 0x021fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*07b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ IMAD R8, R3.reuse, 0x4, R8 ; /* 0x0000000403087824 */
/* 0x040fe200078e0208 */
/*07e0*/ IADD3 R4, R3.reuse, R4, R3.reuse ; /* 0x0000000403047210 */
/* 0x140fe20007ffe003 */
/*07f0*/ IMAD R10, R3, 0x4, R10 ; /* 0x00000004030a7824 */
/* 0x000fe200078e020a */
/*0800*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0810*/ IMAD R6, R3.reuse, 0x4, R6 ; /* 0x0000000403067824 */
/* 0x040fe200078e0206 */
/*0820*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fd60007ffe003 */
/*0830*/ @P0 BRA 0x320 ; /* 0xfffffae000000947 */
/* 0x000fea000383ffff */
/*0840*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0860*/ @!P0 BRA 0xa30 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0870*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0880*/ IADD3 R10, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c00040a7a10 */
/* 0x000fc80007f1e0ff */
/*0890*/ LEA.HI.X.SX32 R11, R4, c[0x0][0x174], 0x1, P0 ; /* 0x00005d00040b7a11 */
/* 0x000fca00000f0eff */
/*08a0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0207 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*08c0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000b */
/*08d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1100 */
/*08e0*/ BSSY B0, 0x9c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*08f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0900*/ @P0 BRA 0x9b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000162000c1e1900 */
/*0920*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fda0003f05270 */
/*0930*/ @!P0 BRA 0x990 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0940*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fc800078e00ff */
/*0950*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*0960*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*0970*/ ISETP.GE.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x024fda0003f06270 */
/*0980*/ @P0 BRA 0x9b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x021fe200078e000d */
/*09a0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*09b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09c0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ IMAD.IADD R4, R3.reuse, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x040fe200078e0204 */
/*09e0*/ IADD3 R10, P1, R3.reuse, R10, RZ ; /* 0x0000000a030a7210 */
/* 0x040fe20007f3e0ff */
/*09f0*/ IMAD.WIDE R6, R3, 0x8, R6 ; /* 0x0000000803067825 */
/* 0x000fe200078e0206 */
/*0a00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0a10*/ LEA.HI.X.SX32 R11, R3, R11, 0x1, P1 ; /* 0x0000000b030b7211 */
/* 0x000fd600008f0eff */
/*0a20*/ @P0 BRA 0x8b0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a40*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*0a50*/ REDUX.MIN.S32 UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e620000010200 */
/*0a60*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0a80*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*0aa0*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x001fe4000bf02070 */
/*0ab0*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x002fd60008000f00 */
/*0ac0*/ @P0 RED.E.MIN.S32.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */
/* 0x0001e8000c90e386 */
/*0ad0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ae0*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea4000c1e1900 */
/*0af0*/ ISETP.NE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x004fda0003f05270 */
/*0b00*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b10*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x001fe400078e00ff */
/*0b20*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*0b30*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101906 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reduceMiniPSt4pairIiiEPbPiS3_
.globl _Z9reduceMiniPSt4pairIiiEPbPiS3_
.p2align 8
.type _Z9reduceMiniPSt4pairIiiEPbPiS3_,@function
_Z9reduceMiniPSt4pairIiiEPbPiS3_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v8, 0x3b9aca07
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
v_mov_b32_e32 v0, -1
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v0, -1
v_mov_b32_e32 v8, 0x3b9aca07
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[8:9], 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, s8, v2
v_add_co_u32 v4, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v2
v_add_co_u32 v6, s2, v6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v7, s2, s7, v7, s2
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_9
.LBB0_4:
global_load_u8 v1, v[4:5], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v1
s_cbranch_execz .LBB0_3
v_cmp_eq_u32_e64 s12, -1, v0
s_mov_b32 s13, exec_lo
v_cmpx_ne_u32_e32 -1, v0
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
s_and_not1_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[0:1]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v1, v[6:7], off
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v3
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s14
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s12
s_cbranch_execz .LBB0_2
global_load_b32 v8, v[6:7], off
v_mov_b32_e32 v0, v2
s_branch .LBB0_2
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
s_mov_b32 s2, exec_lo
s_brev_b32 s4, -2
.LBB0_11:
s_ctz_i32_b32 s3, s2
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v8, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s3
s_min_i32 s4, s4, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_11
s_load_b64 s[2:3], s[0:1], 0x18
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4
s_waitcnt lgkmcnt(0)
global_atomic_min_i32 v1, v2, s[2:3]
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v2, v8
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reduceMiniPSt4pairIiiEPbPiS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reduceMiniPSt4pairIiiEPbPiS3_, .Lfunc_end0-_Z9reduceMiniPSt4pairIiiEPbPiS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reduceMiniPSt4pairIiiEPbPiS3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reduceMiniPSt4pairIiiEPbPiS3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "TerrainModifier.cuh"
__global__ void submerge(float** map, int width, int height){
//Gets the thread numbers
int threadX = threadIdx.x + blockIdx.x * blockDim.x;
int threadY = threadIdx.y + blockIdx.y * blockDim.y;
//Gets the stride to increase
int strideX = gridDim.x*blockDim.x;
int strideY = gridDim.y*blockDim.y;
for (int y = threadY; y < height; y+=strideY) {
for (int x = threadX; x < width; x+=strideX) {
if (map[y][x]<=WATERLEVEL) {
map[y][x] *= -1;
}
}
}
}
void submergeTerrain(float** map, int width, int height) {
submerge<<<dim3(BLOCKSIZE, BLOCKSIZE), dim3(MAXBLOCKS, MAXBLOCKS)>>>(map, width, height);
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z8submergePPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R8, R8, c[0x0][0x4], R3 ; /* 0x0000010008087a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x002fe200078e00ff */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e620000209000 */
/*00c0*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0206 */
/*0100*/ IMAD.IADD R9, R7, 0x1, R0 ; /* 0x0000000107097824 */
/* 0x000fe200078e0200 */
/*0110*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011407 */
/*0120*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x000fe400078e33ff */
/*0130*/ SHF.R.S32.HI R12, RZ, 0x1f, R9 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011409 */
/*0140*/ IADD3 R5, R5, c[0x0][0x168], R0 ; /* 0x00005a0005057a10 */
/* 0x000fe40007ffe000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fe40007ffe0ff */
/*0160*/ SHF.L.U64.HI R10, R7, 0x2, R10 ; /* 0x00000002070a7819 */
/* 0x000fe4000001020a */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*0180*/ SHF.L.U64.HI R12, R9, 0x2, R12 ; /* 0x00000002090c7819 */
/* 0x000fe2000001020c */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*01a0*/ IMAD R11, R11, R3, RZ ; /* 0x000000030b0b7224 */
/* 0x002fd200078e02ff */
/*01b0*/ IMAD.HI.U32 R6, R3, R11, R2 ; /* 0x0000000b03067227 */
/* 0x000fc800078e0002 */
/*01c0*/ IMAD.IADD R11, R0, 0x1, R9 ; /* 0x00000001000b7824 */
/* 0x000fe400078e0209 */
/*01d0*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fc600078e00ff */
/*01e0*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x000fe2000001140b */
/*01f0*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0a06 */
/*0200*/ IADD3 R13, R0.reuse, R11, RZ ; /* 0x0000000b000d7210 */
/* 0x040fe40007ffe0ff */
/*0210*/ SHF.L.U64.HI R14, R11, 0x2, R14 ; /* 0x000000020b0e7819 */
/* 0x000fe2000001020e */
/*0220*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0250*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f7810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ LOP3.LUT R15, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f0f7812 */
/* 0x000fe400078ec0ff */
/*02b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ BSSY B0, 0x730 ; /* 0x0000046000007945 */
/* 0x000fd80003800000 */
/*02d0*/ @P0 BRA 0x720 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*02e0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05270 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0300*/ BSSY B1, 0x520 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0310*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0007 */
/*0320*/ IMAD.WIDE R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fd000078e0203 */
/*0330*/ @!P0 BRA 0x510 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0350*/ LEA R4, P0, R7, R4, 0x2 ; /* 0x0000000407047211 */
/* 0x004fca00078010ff */
/*0360*/ IMAD.X R5, R5, 0x1, R10, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060a */
/*0370*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0380*/ MOV R19, R9 ; /* 0x0000000900137202 */
/* 0x000fe40000000f00 */
/*0390*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*03a0*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*03b0*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x510 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea4000c1e1b00 */
/*03f0*/ LEA R4, P0, R9, R4, 0x2 ; /* 0x0000000409047211 */
/* 0x004fca00078010ff */
/*0400*/ IMAD.X R5, R5, 0x1, R12, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060c */
/*0410*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0420*/ IMAD.MOV.U32 R19, RZ, RZ, R11 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000b */
/*0430*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*0440*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*0450*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e2000c101904 */
/*0460*/ ISETP.NE.AND P0, PT, R15, 0x2, PT ; /* 0x000000020f00780c */
/* 0x000fda0003f05270 */
/*0470*/ @!P0 BRA 0x510 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea4000c1e1b00 */
/*0490*/ LEA R4, P0, R11, R4, 0x2 ; /* 0x000000040b047211 */
/* 0x004fca00078010ff */
/*04a0*/ IMAD.X R5, R5, 0x1, R14, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060e */
/*04b0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ MOV R19, R13 ; /* 0x0000000d00137202 */
/* 0x000fe40000000f00 */
/*04d0*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*04e0*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fe40000000100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff138224 */
/* 0x000fc600078e000d */
/*0500*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e8000c101904 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f06070 */
/*0530*/ @!P0 BRA 0x720 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0540*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0550*/ IMAD.WIDE R16, R19, 0x4, R4 ; /* 0x0000000413107825 */
/* 0x004fca00078e0204 */
/*0560*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FSETP.GTU.AND P0, PT, R23, 128, PT ; /* 0x430000001700780b */
/* 0x004fda0003f0c000 */
/*0580*/ @!P0 FADD R23, -R23, -RZ ; /* 0x800000ff17178221 */
/* 0x000fca0000000100 */
/*0590*/ @!P0 STG.E [R16.64], R23 ; /* 0x0000001710008986 */
/* 0x0001e8000c101904 */
/*05a0*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ IMAD.IADD R21, R0, 0x1, R19 ; /* 0x0000000100157824 */
/* 0x000fc800078e0213 */
/*05c0*/ IMAD.WIDE R18, R21, 0x4, R4 ; /* 0x0000000415127825 */
/* 0x004fca00078e0204 */
/*05d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FSETP.GTU.AND P0, PT, R25, 128, PT ; /* 0x430000001900780b */
/* 0x004fda0003f0c000 */
/*05f0*/ @!P0 FADD R25, -R25, -RZ ; /* 0x800000ff19198221 */
/* 0x000fca0000000100 */
/*0600*/ @!P0 STG.E [R18.64], R25 ; /* 0x0000001912008986 */
/* 0x0003e8000c101904 */
/*0610*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*0620*/ IMAD.IADD R27, R0, 0x1, R21 ; /* 0x00000001001b7824 */
/* 0x000fc800078e0215 */
/*0630*/ IMAD.WIDE R20, R27, 0x4, R4 ; /* 0x000000041b147825 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x001ea4000c1e1900 */
/*0650*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*0660*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*0670*/ @!P0 STG.E [R20.64], R17 ; /* 0x0000001114008986 */
/* 0x0001e8000c101904 */
/*0680*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*0690*/ IADD3 R27, R0, R27, RZ ; /* 0x0000001b001b7210 */
/* 0x000fca0007ffe0ff */
/*06a0*/ IMAD.WIDE R4, R27, 0x4, R4 ; /* 0x000000041b047825 */
/* 0x004fca00078e0204 */
/*06b0*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.IADD R19, R0, 0x1, R27 ; /* 0x0000000100137824 */
/* 0x002fe200078e021b */
/*06d0*/ FSETP.GTU.AND P0, PT, R23, 128, PT ; /* 0x430000001700780b */
/* 0x004fda0003f0c000 */
/*06e0*/ @!P0 FADD R23, -R23, -RZ ; /* 0x800000ff17178221 */
/* 0x000fca0000000100 */
/*06f0*/ @!P0 STG.E [R4.64], R23 ; /* 0x0000001704008986 */
/* 0x0001e2000c101904 */
/*0700*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x168], PT ; /* 0x00005a0013007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @!P0 BRA 0x540 ; /* 0xfffffe2000008947 */
/* 0x001fea000383ffff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff037624 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD R8, R3, c[0x0][0x4], R8 ; /* 0x0000010003087a24 */
/* 0x000fca00078e0208 */
/*0750*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0760*/ @!P0 BRA 0x2b0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "TerrainModifier.cuh"
__global__ void submerge(float** map, int width, int height){
//Gets the thread numbers
int threadX = threadIdx.x + blockIdx.x * blockDim.x;
int threadY = threadIdx.y + blockIdx.y * blockDim.y;
//Gets the stride to increase
int strideX = gridDim.x*blockDim.x;
int strideY = gridDim.y*blockDim.y;
for (int y = threadY; y < height; y+=strideY) {
for (int x = threadX; x < width; x+=strideX) {
if (map[y][x]<=WATERLEVEL) {
map[y][x] *= -1;
}
}
}
}
void submergeTerrain(float** map, int width, int height) {
submerge<<<dim3(BLOCKSIZE, BLOCKSIZE), dim3(MAXBLOCKS, MAXBLOCKS)>>>(map, width, height);
cudaDeviceSynchronize();
} | .file "tmpxft_00000bf8_00000000-6_TerrainModifier.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8submergePPfiiPPfii
.type _Z30__device_stub__Z8submergePPfiiPPfii, @function
_Z30__device_stub__Z8submergePPfiiPPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8submergePPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8submergePPfiiPPfii, .-_Z30__device_stub__Z8submergePPfiiPPfii
.globl _Z8submergePPfii
.type _Z8submergePPfii, @function
_Z8submergePPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8submergePPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8submergePPfii, .-_Z8submergePPfii
.globl _Z15submergeTerrainPPfii
.type _Z15submergeTerrainPPfii, @function
_Z15submergeTerrainPPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl $8, 20(%rsp)
movl $8, 24(%rsp)
movl $256, 8(%rsp)
movl $256, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z30__device_stub__Z8submergePPfiiPPfii
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z15submergeTerrainPPfii, .-_Z15submergeTerrainPPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8submergePPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8submergePPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "TerrainModifier.cuh"
__global__ void submerge(float** map, int width, int height){
//Gets the thread numbers
int threadX = threadIdx.x + blockIdx.x * blockDim.x;
int threadY = threadIdx.y + blockIdx.y * blockDim.y;
//Gets the stride to increase
int strideX = gridDim.x*blockDim.x;
int strideY = gridDim.y*blockDim.y;
for (int y = threadY; y < height; y+=strideY) {
for (int x = threadX; x < width; x+=strideX) {
if (map[y][x]<=WATERLEVEL) {
map[y][x] *= -1;
}
}
}
}
void submergeTerrain(float** map, int width, int height) {
submerge<<<dim3(BLOCKSIZE, BLOCKSIZE), dim3(MAXBLOCKS, MAXBLOCKS)>>>(map, width, height);
cudaDeviceSynchronize();
} | #ifndef TERRAINMODIFIER_CUH
#define TERRAINMODIFIER_CUH
#include <stdio.h>
#define MAXBLOCKS 8
#define BLOCKSIZE 256
#define WATERLEVEL 128
void submergeTerrain(float** map, int width, int height);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef TERRAINMODIFIER_CUH
#define TERRAINMODIFIER_CUH
#include <stdio.h>
#define MAXBLOCKS 8
#define BLOCKSIZE 256
#define WATERLEVEL 128
void submergeTerrain(float** map, int width, int height);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef TERRAINMODIFIER_CUH
#define TERRAINMODIFIER_CUH
#include <stdio.h>
#define MAXBLOCKS 8
#define BLOCKSIZE 256
#define WATERLEVEL 128
void submergeTerrain(float** map, int width, int height);
#endif | .text
.file "TerrainModifier.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8submergePPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R8, R8, c[0x0][0x4], R3 ; /* 0x0000010008087a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x002fe200078e00ff */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e620000209000 */
/*00c0*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0206 */
/*0100*/ IMAD.IADD R9, R7, 0x1, R0 ; /* 0x0000000107097824 */
/* 0x000fe200078e0200 */
/*0110*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011407 */
/*0120*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x000fe400078e33ff */
/*0130*/ SHF.R.S32.HI R12, RZ, 0x1f, R9 ; /* 0x0000001fff0c7819 */
/* 0x000fe40000011409 */
/*0140*/ IADD3 R5, R5, c[0x0][0x168], R0 ; /* 0x00005a0005057a10 */
/* 0x000fe40007ffe000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fe40007ffe0ff */
/*0160*/ SHF.L.U64.HI R10, R7, 0x2, R10 ; /* 0x00000002070a7819 */
/* 0x000fe4000001020a */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*0180*/ SHF.L.U64.HI R12, R9, 0x2, R12 ; /* 0x00000002090c7819 */
/* 0x000fe2000001020c */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*01a0*/ IMAD R11, R11, R3, RZ ; /* 0x000000030b0b7224 */
/* 0x002fd200078e02ff */
/*01b0*/ IMAD.HI.U32 R6, R3, R11, R2 ; /* 0x0000000b03067227 */
/* 0x000fc800078e0002 */
/*01c0*/ IMAD.IADD R11, R0, 0x1, R9 ; /* 0x00000001000b7824 */
/* 0x000fe400078e0209 */
/*01d0*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fc600078e00ff */
/*01e0*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x000fe2000001140b */
/*01f0*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0a06 */
/*0200*/ IADD3 R13, R0.reuse, R11, RZ ; /* 0x0000000b000d7210 */
/* 0x040fe40007ffe0ff */
/*0210*/ SHF.L.U64.HI R14, R11, 0x2, R14 ; /* 0x000000020b0e7819 */
/* 0x000fe2000001020e */
/*0220*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0250*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f7810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ LOP3.LUT R15, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f0f7812 */
/* 0x000fe400078ec0ff */
/*02b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ BSSY B0, 0x730 ; /* 0x0000046000007945 */
/* 0x000fd80003800000 */
/*02d0*/ @P0 BRA 0x720 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*02e0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05270 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0300*/ BSSY B1, 0x520 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0310*/ IMAD.MOV.U32 R19, RZ, RZ, R7 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0007 */
/*0320*/ IMAD.WIDE R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fd000078e0203 */
/*0330*/ @!P0 BRA 0x510 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0350*/ LEA R4, P0, R7, R4, 0x2 ; /* 0x0000000407047211 */
/* 0x004fca00078010ff */
/*0360*/ IMAD.X R5, R5, 0x1, R10, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060a */
/*0370*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0380*/ MOV R19, R9 ; /* 0x0000000900137202 */
/* 0x000fe40000000f00 */
/*0390*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*03a0*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*03b0*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 BRA 0x510 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea4000c1e1b00 */
/*03f0*/ LEA R4, P0, R9, R4, 0x2 ; /* 0x0000000409047211 */
/* 0x004fca00078010ff */
/*0400*/ IMAD.X R5, R5, 0x1, R12, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060c */
/*0410*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0420*/ IMAD.MOV.U32 R19, RZ, RZ, R11 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000b */
/*0430*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*0440*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*0450*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e2000c101904 */
/*0460*/ ISETP.NE.AND P0, PT, R15, 0x2, PT ; /* 0x000000020f00780c */
/* 0x000fda0003f05270 */
/*0470*/ @!P0 BRA 0x510 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea4000c1e1b00 */
/*0490*/ LEA R4, P0, R11, R4, 0x2 ; /* 0x000000040b047211 */
/* 0x004fca00078010ff */
/*04a0*/ IMAD.X R5, R5, 0x1, R14, P0 ; /* 0x0000000105057824 */
/* 0x000fca00000e060e */
/*04b0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ MOV R19, R13 ; /* 0x0000000d00137202 */
/* 0x000fe40000000f00 */
/*04d0*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*04e0*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fe40000000100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff138224 */
/* 0x000fc600078e000d */
/*0500*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x0001e8000c101904 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f06070 */
/*0530*/ @!P0 BRA 0x720 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0540*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0550*/ IMAD.WIDE R16, R19, 0x4, R4 ; /* 0x0000000413107825 */
/* 0x004fca00078e0204 */
/*0560*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FSETP.GTU.AND P0, PT, R23, 128, PT ; /* 0x430000001700780b */
/* 0x004fda0003f0c000 */
/*0580*/ @!P0 FADD R23, -R23, -RZ ; /* 0x800000ff17178221 */
/* 0x000fca0000000100 */
/*0590*/ @!P0 STG.E [R16.64], R23 ; /* 0x0000001710008986 */
/* 0x0001e8000c101904 */
/*05a0*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ IMAD.IADD R21, R0, 0x1, R19 ; /* 0x0000000100157824 */
/* 0x000fc800078e0213 */
/*05c0*/ IMAD.WIDE R18, R21, 0x4, R4 ; /* 0x0000000415127825 */
/* 0x004fca00078e0204 */
/*05d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FSETP.GTU.AND P0, PT, R25, 128, PT ; /* 0x430000001900780b */
/* 0x004fda0003f0c000 */
/*05f0*/ @!P0 FADD R25, -R25, -RZ ; /* 0x800000ff19198221 */
/* 0x000fca0000000100 */
/*0600*/ @!P0 STG.E [R18.64], R25 ; /* 0x0000001912008986 */
/* 0x0003e8000c101904 */
/*0610*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*0620*/ IMAD.IADD R27, R0, 0x1, R21 ; /* 0x00000001001b7824 */
/* 0x000fc800078e0215 */
/*0630*/ IMAD.WIDE R20, R27, 0x4, R4 ; /* 0x000000041b147825 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x001ea4000c1e1900 */
/*0650*/ FSETP.GTU.AND P0, PT, R17, 128, PT ; /* 0x430000001100780b */
/* 0x004fda0003f0c000 */
/*0660*/ @!P0 FADD R17, -R17, -RZ ; /* 0x800000ff11118221 */
/* 0x000fca0000000100 */
/*0670*/ @!P0 STG.E [R20.64], R17 ; /* 0x0000001114008986 */
/* 0x0001e8000c101904 */
/*0680*/ @!P0 LDG.E.64 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1b00 */
/*0690*/ IADD3 R27, R0, R27, RZ ; /* 0x0000001b001b7210 */
/* 0x000fca0007ffe0ff */
/*06a0*/ IMAD.WIDE R4, R27, 0x4, R4 ; /* 0x000000041b047825 */
/* 0x004fca00078e0204 */
/*06b0*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.IADD R19, R0, 0x1, R27 ; /* 0x0000000100137824 */
/* 0x002fe200078e021b */
/*06d0*/ FSETP.GTU.AND P0, PT, R23, 128, PT ; /* 0x430000001700780b */
/* 0x004fda0003f0c000 */
/*06e0*/ @!P0 FADD R23, -R23, -RZ ; /* 0x800000ff17178221 */
/* 0x000fca0000000100 */
/*06f0*/ @!P0 STG.E [R4.64], R23 ; /* 0x0000001704008986 */
/* 0x0001e2000c101904 */
/*0700*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x168], PT ; /* 0x00005a0013007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @!P0 BRA 0x540 ; /* 0xfffffe2000008947 */
/* 0x001fea000383ffff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff037624 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD R8, R3, c[0x0][0x4], R8 ; /* 0x0000010003087a24 */
/* 0x000fca00078e0208 */
/*0750*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0760*/ @!P0 BRA 0x2b0 ; /* 0xfffffb4000008947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00000bf8_00000000-6_TerrainModifier.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8submergePPfiiPPfii
.type _Z30__device_stub__Z8submergePPfiiPPfii, @function
_Z30__device_stub__Z8submergePPfiiPPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8submergePPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8submergePPfiiPPfii, .-_Z30__device_stub__Z8submergePPfiiPPfii
.globl _Z8submergePPfii
.type _Z8submergePPfii, @function
_Z8submergePPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8submergePPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8submergePPfii, .-_Z8submergePPfii
.globl _Z15submergeTerrainPPfii
.type _Z15submergeTerrainPPfii, @function
_Z15submergeTerrainPPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl $8, 20(%rsp)
movl $8, 24(%rsp)
movl $256, 8(%rsp)
movl $256, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z30__device_stub__Z8submergePPfiiPPfii
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z15submergeTerrainPPfii, .-_Z15submergeTerrainPPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8submergePPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8submergePPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TerrainModifier.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#define MASK_N 2
#define MASK_X 5
#define MASK_Y 5
#define SCALE 8
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
using namespace std;
unsigned char *image_s = NULL; // source image array
unsigned char *image_t = NULL; // target image array
FILE *fp_s = NULL; // source file handler
FILE *fp_t = NULL; // target file handler
unsigned int width, height; // image width, image height
unsigned int rgb_raw_data_offset;// rgb raw data offset
unsigned char bit_per_pixel; // bit per pixel
unsigned short byte_per_pixel; // byte per pixel
// bitmap header
unsigned char header[54] = {
0x42, // identity : B
0x4d, // identity : M
0, 0, 0, 0, // file size
0, 0, // reserved1
0, 0, // reserved2
54, 0, 0, 0, // RGB data offset
40, 0, 0, 0, // struct BITMAPINFOHEADER size
0, 0, 0, 0, // bmp width
0, 0, 0, 0, // bmp height
1, 0, // planes
24, 0, // bit per pixel
0, 0, 0, 0, // compression
0, 0, 0, 0, // data size
0, 0, 0, 0, // h resolution
0, 0, 0, 0, // v resolution
0, 0, 0, 0, // used colors
0, 0, 0, 0 // important colors
};
// sobel mask (5x5 version)
// Task 2: Put mask[][][] into Shared Memroy
int _mask[MASK_N][MASK_X][MASK_Y] = {
{{ -1, -4, -6, -4, -1},
{ -2, -8,-12, -8, -2},
{ 0, 0, 0, 0, 0},
{ 2, 8, 12, 8, 2},
{ 1, 4, 6, 4, 1}}
,
{{ -1, -2, 0, 2, 1},
{ -4, -8, 0, 8, 4},
{ -6,-12, 0, 12, 6},
{ -4, -8, 0, 8, 4},
{ -1, -2, 0, 2, 1}}
};
int read_bmp (const char *fname_s) {
fp_s = fopen(fname_s, "rb");
if (fp_s == NULL) {
printf("fopen fp_s error\n");
return -1;
}
// move offset to 10 to find rgb raw data offset
fseek(fp_s, 10, SEEK_SET);
fread(&rgb_raw_data_offset, sizeof(unsigned int), 1, fp_s);
// move offset to 18 to get width & height;
fseek(fp_s, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp_s);
fread(&height, sizeof(unsigned int), 1, fp_s);
// get bit per pixel
fseek(fp_s, 28, SEEK_SET);
fread(&bit_per_pixel, sizeof(unsigned short), 1, fp_s);
byte_per_pixel = bit_per_pixel / 8;
// move offset to rgb_raw_data_offset to get RGB raw data
fseek(fp_s, rgb_raw_data_offset, SEEK_SET);
// Task 3: Assign image_s to Pinnned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
int totalSize = width * height * byte_per_pixel;
totalSize = totalSize < 0 ? -totalSize : totalSize;
//image_s = (unsigned char *) malloc((size_t)totalSize);
cudaError_t err = cudaMallocHost(&image_s, (size_t)totalSize);
cudaCheckErrors("cuda_malloc_images_s error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_s error");
}
*/
/*
if (image_s == NULL) {
printf("malloc images_s errori, %d\n", totalSize);
return -1;
}
*/
// Task 3: Assign image_t to Pinned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
//image_t = (unsigned char *) malloc(totalSize);
err = cudaMallocHost(&image_t, (size_t)totalSize);
cudaCheckErrors("cuda_malloc_images_t error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_t error");
}
*/
/*
if (image_t == NULL) {
printf("malloc image_t error %d\n", totalSize);
return -1;
}
*/
fread(image_s, sizeof(unsigned char), (size_t)(long) totalSize, fp_s);
return 0;
}
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef unsigned short uint16;
// unsigned char *image_s = NULL; // source image array
// unsigned char *image_t = NULL; // target image array
// FILE *fp_s = NULL; // source file handler
//FILE *fp_t = NULL; // target file handler
// unsigned int width, height; // image width, image height
// unsigned int rgb_raw_data_offset;// rgb raw data offset
// unsigned char bit_per_pixel; // bit per pixel
// unsigned short byte_per_pixel; // byte per pixel
void DisplayHeader()
{
const int kb = 1024;
const int mb = kb * kb;
wcout << "NBody.GPU" << endl << "=========" << endl << endl;
//wcout << "CUDA version: v" << CUDART_VERSION << endl;
//wcout << "Thrust version: v" << THRUST_MAJOR_VERSION << "." << THRUST_MINOR_VERSION << endl << endl;
int devCount;
cudaGetDeviceCount(&devCount);
wcout << "CUDA Devices: " << endl << endl;
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
wcout << i << ": " << props.name << ": " << props.major << "." << props.minor << endl;
wcout << " Global memory: " << props.totalGlobalMem / mb << "mb" << endl;
wcout << " Shared memory: " << props.sharedMemPerBlock / kb << "kb" << endl;
wcout << " Constant memory: " << props.totalConstMem / kb << "kb" << endl;
wcout << " Block registers: " << props.regsPerBlock << endl << endl;
wcout << " Warp size: " << props.warpSize << endl;
wcout << " Threads per block: " << props.maxThreadsPerBlock << endl;
wcout << " Max block dimensions: [ " << props.maxThreadsDim[0] << ", " << props.maxThreadsDim[1] << ", " << props.maxThreadsDim[2] << " ]" << endl;
wcout << " Max grid dimensions: [ " << props.maxGridSize[0] << ", " << props.maxGridSize[1] << ", " << props.maxGridSize[2] << " ]" << endl;
wcout << endl;
}
}
__global__ void sobel(unsigned char *c_image_s, unsigned char *c_image_t,
unsigned int *c_width, unsigned int *c_height,
unsigned short *c_byte_per_pixel,
int* c_mask ) {
int x, y, i, v, u; // for loop counter
int R, G, B; // color of R, G, B
double val[MASK_N*3] = {0.0};
int adjustX, adjustY, xBound, yBound;
unsigned char *image_s = c_image_s;
unsigned char *image_t = c_image_t;
int width = *c_width;
int height = *c_height;
unsigned short byte_per_pixel = *c_byte_per_pixel;
__shared__ int mask[MASK_N][MASK_X][MASK_Y];
for (int i = 0; i < MASK_N; ++i) {
for (int j = 0; j < MASK_X; ++j) {
for(int k = 0; k < MASK_Y; ++k) {
mask[i][j][k] =
c_mask[i*MASK_Y*MASK_X + j*MASK_Y + k];
}
}
}
__syncthreads();
// Task 2: Put mask[][][] into Shared Memory
// Hint : Please declare it in kernel function
// Then use some threads to move data from global memory to shared memory
// Remember to __syncthreads() after it's done <WHY?>
// Task 1: Relabel x, y into combination of blockIdx, threadIdx ... etc
// Hint A: We do not have enough threads for each pixels in the image, so what should we do?
// Hint B: Maybe you can map each y to different threads in different blocks
int threadNum = blockDim.x;
int blockPerHeight = (width / threadNum) +
((width % threadNum) > 0 ? 1 : 0) ;
y = blockIdx.x / blockPerHeight;
x = threadNum * (blockIdx.x % blockPerHeight) + threadIdx.x;
if (y < height) {
if (x < width) {
for (i = 0; i < MASK_N; ++i) {
adjustX = (MASK_X % 2) ? 1 : 0;
adjustY = (MASK_Y % 2) ? 1 : 0;
xBound = MASK_X /2;
yBound = MASK_Y /2;
val[i*3+2] = 0.0;
val[i*3+1] = 0.0;
val[i*3] = 0.0;
for (v = -yBound; v < yBound + adjustY; ++v) {
for (u = -xBound; u < xBound + adjustX; ++u) {
if ((x + u) >= 0 && (x + u) < width && y + v >= 0 && y + v < height) {
R = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 2];
G = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 1];
B = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 0];
val[i*3+2] += R * mask[i][u + xBound][v + yBound];
val[i*3+1] += G * mask[i][u + xBound][v + yBound];
val[i*3+0] += B * mask[i][u + xBound][v + yBound];
}
}
}
}
double totalR = 0.0;
double totalG = 0.0;
double totalB = 0.0;
for (i = 0; i < MASK_N; ++i) {
totalR += val[i*3+2] * val[i*3+2];
totalG += val[i*3+1] * val[i*3+1];
totalB += val[i*3+0] * val[i*3+0];
}
totalR = sqrt(totalR) / SCALE;
totalG = sqrt(totalG) / SCALE;
totalB = sqrt(totalB) / SCALE;
const unsigned char cR = (totalR > 255.0) ? 255 : totalR;
const unsigned char cG = (totalG > 255.0) ? 255 : totalG;
const unsigned char cB = (totalB > 255.0) ? 255 : totalB;
image_t[ byte_per_pixel * (width * y + x) + 2 ] = cR;
image_t[ byte_per_pixel * (width * y + x) + 1 ] = cG;
image_t[ byte_per_pixel * (width * y + x) + 0 ] = cB;
}
}
}
int write_bmp (const char *fname_t) {
unsigned int file_size; // file size
fp_t = fopen(fname_t, "wb");
if (fp_t == NULL) {
printf("fopen fname_t error\n");
return -1;
}
// file size
file_size = width * height * byte_per_pixel + rgb_raw_data_offset;
header[2] = (unsigned char)(file_size & 0x000000ff);
header[3] = (file_size >> 8) & 0x000000ff;
header[4] = (file_size >> 16) & 0x000000ff;
header[5] = (file_size >> 24) & 0x000000ff;
// width
header[18] = width & 0x000000ff;
header[19] = (width >> 8) & 0x000000ff;
header[20] = (width >> 16) & 0x000000ff;
header[21] = (width >> 24) & 0x000000ff;
// height
header[22] = height &0x000000ff;
header[23] = (height >> 8) & 0x000000ff;
header[24] = (height >> 16) & 0x000000ff;
header[25] = (height >> 24) & 0x000000ff;
// bit per pixel
header[28] = bit_per_pixel;
// write header
fwrite(header, sizeof(unsigned char), rgb_raw_data_offset, fp_t);
// write image
fwrite(image_t, sizeof(unsigned char), (size_t)(long)width * height * byte_per_pixel, fp_t);
fclose(fp_s);
fclose(fp_t);
return 0;
}
int init_device ()
{ // Task 1: Device (GPU) Initialization
// Hint : cudaSetDevice()
cudaSetDevice(1);
return 0;
}
int
main(int argc, char **argv) {
init_device();
DisplayHeader();
const char *input = "candy.bmp";
if (argc > 1) input = argv[1];
read_bmp(input); // 24 bit gray level image
unsigned char *c_image_s = NULL; // source image array
unsigned char *c_image_t = NULL; // target image array
unsigned int *c_width, *c_height; // image width, image height
unsigned int *c_rgb_raw_data_offset;// rgb raw data offset
unsigned char *c_bit_per_pixel; // bit per pixel
unsigned short *c_byte_per_pixel; // byte per pixel
int *c_mask = NULL;
// Task 1: Allocate memory on GPU
// Hint : cudaMalloc ()
// What do we need to store on GPU? (input image, output image, ...
int mask1D[MASK_N * MASK_Y * MASK_X];
for (int i = 0; i < MASK_N; ++i)
for (int j = 0; j < MASK_X; ++j)
for(int k = 0; k < MASK_Y; ++k)
mask1D[i * MASK_X * MASK_Y + j * MASK_Y + k] = _mask[i][j][k];
cudaMalloc((void**)&c_image_t, (size_t)width * height * byte_per_pixel);
cudaMalloc((void**)&c_image_s, (size_t)width * height * byte_per_pixel);
cudaMalloc((void**)&c_width, (size_t)sizeof(int));
cudaMalloc((void**)&c_height, (size_t)sizeof(int));
cudaMalloc((void**)&c_rgb_raw_data_offset, (size_t)sizeof(int));
cudaMalloc((void**)&c_bit_per_pixel, (size_t)sizeof(char));
cudaMalloc((void**)&c_byte_per_pixel, (size_t)sizeof(short));
cudaMalloc((void**)&c_mask, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X);
cudaCheckErrors("cudamalloc fail");
/*
for (int i = 0; i < MASK_N; ++i)
cudaMalloc((void**)c_mask[i], sizeof(int*) * MASK_X);
*/
cudaMemcpy(c_mask, mask1D, sizeof(mask1D), cudaMemcpyHostToDevice);
// Task 1: Memory copy from Host to Device (GPU)
// Hint : cudaMemcpy ( ... , cudaMemcpyHostToDevice )
cudaMemcpy(c_width, &width, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_height, &height, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_image_t, image_t, width * height * byte_per_pixel, cudaMemcpyHostToDevice);
cudaMemcpy(c_image_s, image_s, width * height * byte_per_pixel, cudaMemcpyHostToDevice);
cudaMemcpy(c_bit_per_pixel, &bit_per_pixel, sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(c_byte_per_pixel, &byte_per_pixel, sizeof(short), cudaMemcpyHostToDevice);
cudaCheckErrors("cuda memcpy fail");
// Hint : sobel_Kernel <<< ??? , ??? >>> ( ??? );
int blockNum = (width / 1024) + ((width % 1024) ? 1 : 0);
wcout << blockNum << endl;
blockNum = blockNum * height;
wcout << blockNum << endl;
sobel<<<blockNum, 1024, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X>>>( c_image_s, c_image_t,
c_width, c_height,
c_byte_per_pixel,
c_mask);
// Task 1: Memory Copy from Device (GPU) to Host
// Hint : cudaMemcpy ( ... , cudaMemcpyDeviceToHost )
// Task 1: Free memory on device
// Hint : cudaFree ( ... )
cudaMemcpy(image_t, c_image_t, (size_t)width * height * byte_per_pixel, cudaMemcpyDeviceToHost);
cudaCheckErrors("cuda memcpy back to host fail");
cudaFree(c_image_t);
cudaFree(c_image_s);
cudaFree(c_width);
cudaFree(c_height);
cudaFree(c_rgb_raw_data_offset);
cudaFree(c_bit_per_pixel);
cudaFree(c_byte_per_pixel);
write_bmp("out.bmp");
// Task 3: Free Pinned memory
// Hint : replace free ( ... ) by cudaFreeHost ( ... )
cudaFreeHost(image_s);
cudaFreeHost(image_t);
} | .file "tmpxft_000aea89_00000000-6_sobel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "fopen fp_s error\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ChihMin/Parallel_Programming/master/cuda_prac/sobel.cu"
.section .rodata.str1.1
.LC3:
.string "cuda_malloc_images_s error"
.section .rodata.str1.8
.align 8
.LC4:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC5:
.string "*** FAILED - ABORTING\n"
.LC6:
.string "cuda_malloc_images_t error"
.text
.globl _Z8read_bmpPKc
.type _Z8read_bmpPKc, @function
_Z8read_bmpPKc:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, fp_s(%rip)
testq %rax, %rax
je .L9
movq %rax, %rdi
movl $0, %edx
movl $10, %esi
call fseek@PLT
movq fp_s(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
leaq rgb_raw_data_offset(%rip), %rdi
call __fread_chk@PLT
movl $0, %edx
movl $18, %esi
movq fp_s(%rip), %rdi
call fseek@PLT
movq fp_s(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
leaq width(%rip), %rdi
call __fread_chk@PLT
movq fp_s(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
leaq height(%rip), %rdi
call __fread_chk@PLT
movl $0, %edx
movl $28, %esi
movq fp_s(%rip), %rdi
call fseek@PLT
movq fp_s(%rip), %r8
movl $1, %ecx
movl $2, %edx
movl $1, %esi
leaq bit_per_pixel(%rip), %rdi
call __fread_chk@PLT
movzbl bit_per_pixel(%rip), %eax
shrb $3, %al
movzbl %al, %eax
movw %ax, byte_per_pixel(%rip)
movl rgb_raw_data_offset(%rip), %esi
movl $0, %edx
movq fp_s(%rip), %rdi
call fseek@PLT
movl width(%rip), %eax
imull height(%rip), %eax
movzwl byte_per_pixel(%rip), %edx
imull %edx, %eax
movl %eax, %ebx
negl %ebx
cmovs %eax, %ebx
movslq %ebx, %rbx
movl $0, %edx
movq %rbx, %rsi
leaq image_s(%rip), %rdi
call cudaHostAlloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L10
movl $0, %edx
movq %rbx, %rsi
leaq image_t(%rip), %rdi
call cudaHostAlloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L11
movq fp_s(%rip), %r8
movq %rbx, %rcx
movl $1, %edx
movq $-1, %rsi
movq image_s(%rip), %rdi
call __fread_chk@PLT
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L3
.L10:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 24
pushq $108
.cfi_def_cfa_offset 32
leaq .LC2(%rip), %r9
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 24
pushq $125
.cfi_def_cfa_offset 32
leaq .LC2(%rip), %r9
leaq .LC6(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z8read_bmpPKc, .-_Z8read_bmpPKc
.section .rodata.str1.1
.LC7:
.string "NBody.GPU"
.LC8:
.string "========="
.LC9:
.string "CUDA Devices: "
.LC10:
.string ": "
.LC11:
.string "."
.LC12:
.string " Global memory: "
.LC13:
.string "mb"
.LC14:
.string " Shared memory: "
.LC15:
.string "kb"
.LC16:
.string " Constant memory: "
.LC17:
.string " Block registers: "
.LC18:
.string " Warp size: "
.LC19:
.string " Threads per block: "
.LC20:
.string " Max block dimensions: [ "
.LC21:
.string ", "
.LC22:
.string " ]"
.LC23:
.string " Max grid dimensions: [ "
.text
.globl _Z13DisplayHeaderv
.type _Z13DisplayHeaderv, @function
_Z13DisplayHeaderv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rsi
leaq _ZSt5wcout(%rip), %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L50
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L51
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L52
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt5wcout(%rip), %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L53
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L54
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
cmpl $0, 12(%rsp)
jle .L12
movl $0, %r12d
leaq _ZSt5wcout(%rip), %rbx
leaq .LC10(%rip), %r13
leaq .LC11(%rip), %r14
leaq .LC12(%rip), %r15
.L46:
leaq 16(%rsp), %rbp
movl %r12d, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 376(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 380(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L55
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq %r15, %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rsi
shrq $20, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L56
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 312(%rsp), %rsi
shrq $10, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L57
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 368(%rsp), %rsi
shrq $10, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L58
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 320(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L59
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L60
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 324(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L61
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC19(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 336(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L62
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 340(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rbp
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 344(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 348(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC22(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L63
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 352(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rbp
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 356(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 360(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC22(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L64
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .L65
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbx, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jg .L46
.L12:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L51:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L68
call _ZSt16__throw_bad_castv@PLT
.L68:
call __stack_chk_fail@PLT
.L52:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L69
call _ZSt16__throw_bad_castv@PLT
.L69:
call __stack_chk_fail@PLT
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L70
call _ZSt16__throw_bad_castv@PLT
.L70:
call __stack_chk_fail@PLT
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L71
call _ZSt16__throw_bad_castv@PLT
.L71:
call __stack_chk_fail@PLT
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L73
call _ZSt16__throw_bad_castv@PLT
.L73:
call __stack_chk_fail@PLT
.L57:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L74
call _ZSt16__throw_bad_castv@PLT
.L74:
call __stack_chk_fail@PLT
.L58:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L75
call _ZSt16__throw_bad_castv@PLT
.L75:
call __stack_chk_fail@PLT
.L59:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L76
call _ZSt16__throw_bad_castv@PLT
.L76:
call __stack_chk_fail@PLT
.L60:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L77
call _ZSt16__throw_bad_castv@PLT
.L77:
call __stack_chk_fail@PLT
.L61:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L62:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L79
call _ZSt16__throw_bad_castv@PLT
.L79:
call __stack_chk_fail@PLT
.L63:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L80
call _ZSt16__throw_bad_castv@PLT
.L80:
call __stack_chk_fail@PLT
.L64:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L81
call _ZSt16__throw_bad_castv@PLT
.L81:
call __stack_chk_fail@PLT
.L65:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L82
call _ZSt16__throw_bad_castv@PLT
.L82:
call __stack_chk_fail@PLT
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z13DisplayHeaderv, .-_Z13DisplayHeaderv
.section .rodata.str1.1
.LC24:
.string "wb"
.LC25:
.string "fopen fname_t error\n"
.text
.globl _Z9write_bmpPKc
.type _Z9write_bmpPKc, @function
_Z9write_bmpPKc:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq .LC24(%rip), %rsi
call fopen@PLT
movq %rax, fp_t(%rip)
testq %rax, %rax
je .L87
movq %rax, %rsi
movl width(%rip), %ebx
movl height(%rip), %ecx
movl rgb_raw_data_offset(%rip), %edx
movl %ebx, %eax
imull %ecx, %eax
movzwl byte_per_pixel(%rip), %edi
imull %edi, %eax
addl %edx, %eax
movb %al, 2+header(%rip)
movb %ah, 3+header(%rip)
movl %eax, %edi
shrl $16, %edi
movb %dil, 4+header(%rip)
shrl $24, %eax
movb %al, 5+header(%rip)
movb %bl, 18+header(%rip)
movb %bh, 19+header(%rip)
movl %ebx, %eax
shrl $16, %eax
movb %al, 20+header(%rip)
shrl $24, %ebx
movb %bl, 21+header(%rip)
movb %cl, 22+header(%rip)
movb %ch, 23+header(%rip)
movl %ecx, %eax
shrl $16, %eax
movb %al, 24+header(%rip)
shrl $24, %ecx
movb %cl, 25+header(%rip)
movzbl bit_per_pixel(%rip), %eax
movb %al, 28+header(%rip)
movl %edx, %edx
movq %rsi, %rcx
movl $1, %esi
leaq header(%rip), %rdi
call fwrite@PLT
movl width(%rip), %edx
movl height(%rip), %eax
imulq %rax, %rdx
movzwl byte_per_pixel(%rip), %eax
imulq %rax, %rdx
movq fp_t(%rip), %rcx
movl $1, %esi
movq image_t(%rip), %rdi
call fwrite@PLT
movq fp_s(%rip), %rdi
call fclose@PLT
movq fp_t(%rip), %rdi
call fclose@PLT
movl $0, %eax
.L83:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L83
.cfi_endproc
.LFE3671:
.size _Z9write_bmpPKc, .-_Z9write_bmpPKc
.globl _Z11init_devicev
.type _Z11init_devicev, @function
_Z11init_devicev:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z11init_devicev, .-_Z11init_devicev
.globl _Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi
.type _Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi, @function
_Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5sobelPhS_PjS0_PtPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi, .-_Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi
.globl _Z5sobelPhS_PjS0_PtPi
.type _Z5sobelPhS_PjS0_PtPi, @function
_Z5sobelPhS_PjS0_PtPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z5sobelPhS_PjS0_PtPi, .-_Z5sobelPhS_PjS0_PtPi
.section .rodata.str1.1
.LC26:
.string "candy.bmp"
.LC27:
.string "cudamalloc fail"
.LC28:
.string "cuda memcpy fail"
.LC29:
.string "cuda memcpy back to host fail"
.LC30:
.string "out.bmp"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $312, %rsp
.cfi_def_cfa_offset 336
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
call _Z11init_devicev
call _Z13DisplayHeaderv
leaq .LC26(%rip), %rdi
cmpl $1, %ebx
jle .L99
movq 8(%rbp), %rdi
.L99:
call _Z8read_bmpPKc
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 64(%rsp)
leaq _mask(%rip), %rsi
leaq 96(%rsp), %rcx
movl $0, %edi
.L101:
movl $0, %eax
.L100:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L100
addl $5, %edi
addq $20, %rsi
addq $20, %rcx
cmpl $25, %edi
jne .L101
leaq 100+_mask(%rip), %rsi
leaq 196(%rsp), %rcx
.L102:
movl $0, %eax
.L103:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L103
addl $5, %edi
addq $20, %rsi
addq $20, %rcx
cmpl $50, %edi
jne .L102
movl width(%rip), %esi
movl height(%rip), %eax
imulq %rax, %rsi
movzwl byte_per_pixel(%rip), %eax
imulq %rax, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl width(%rip), %esi
movl height(%rip), %eax
imulq %rax, %rsi
movzwl byte_per_pixel(%rip), %eax
imulq %rax, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L115
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $200, %edx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
leaq width(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
leaq height(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl width(%rip), %edx
imull height(%rip), %edx
movzwl byte_per_pixel(%rip), %eax
imull %eax, %edx
movl $1, %ecx
movq image_t(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl width(%rip), %edx
imull height(%rip), %edx
movzwl byte_per_pixel(%rip), %eax
imull %eax, %edx
movl $1, %ecx
movq image_s(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1, %edx
leaq bit_per_pixel(%rip), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2, %edx
leaq byte_per_pixel(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L116
movl width(%rip), %eax
testl $1023, %eax
setne %bl
movzbl %bl, %ebx
shrl $10, %eax
addl %eax, %ebx
movl %ebx, %esi
leaq _ZSt5wcout(%rip), %rbp
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
call _ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_@PLT
imull height(%rip), %ebx
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
call _ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl %ebx, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $200, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L107:
movl width(%rip), %edx
movl height(%rip), %eax
imulq %rax, %rdx
movzwl byte_per_pixel(%rip), %eax
imulq %rax, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq image_t(%rip), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L118
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC30(%rip), %rdi
call _Z9write_bmpPKc
movq image_s(%rip), %rdi
call cudaFreeHost@PLT
movq image_t(%rip), %rdi
call cudaFreeHost@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L119
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L115:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq $366
.cfi_def_cfa_offset 352
leaq .LC2(%rip), %r9
leaq .LC27(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq $382
.cfi_def_cfa_offset 352
leaq .LC2(%rip), %r9
leaq .LC28(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L117:
movq 64(%rsp), %r9
movq 56(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z5sobelPhS_PjS0_PtPiPhS_PjS0_PtPi
jmp .L107
.L118:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq $401
.cfi_def_cfa_offset 352
leaq .LC2(%rip), %r9
leaq .LC29(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L119:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC31:
.string "_Z5sobelPhS_PjS0_PtPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sobelPhS_PjS0_PtPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _mask
.data
.align 32
.type _mask, @object
.size _mask, 200
_mask:
.long -1
.long -4
.long -6
.long -4
.long -1
.long -2
.long -8
.long -12
.long -8
.long -2
.long 0
.long 0
.long 0
.long 0
.long 0
.long 2
.long 8
.long 12
.long 8
.long 2
.long 1
.long 4
.long 6
.long 4
.long 1
.long -1
.long -2
.long 0
.long 2
.long 1
.long -4
.long -8
.long 0
.long 8
.long 4
.long -6
.long -12
.long 0
.long 12
.long 6
.long -4
.long -8
.long 0
.long 8
.long 4
.long -1
.long -2
.long 0
.long 2
.long 1
.globl header
.align 32
.type header, @object
.size header, 54
header:
.string "BM"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string "6"
.string ""
.string ""
.string "("
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string "\001"
.string "\030"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.globl byte_per_pixel
.bss
.align 2
.type byte_per_pixel, @object
.size byte_per_pixel, 2
byte_per_pixel:
.zero 2
.globl bit_per_pixel
.type bit_per_pixel, @object
.size bit_per_pixel, 1
bit_per_pixel:
.zero 1
.globl rgb_raw_data_offset
.align 4
.type rgb_raw_data_offset, @object
.size rgb_raw_data_offset, 4
rgb_raw_data_offset:
.zero 4
.globl height
.align 4
.type height, @object
.size height, 4
height:
.zero 4
.globl width
.align 4
.type width, @object
.size width, 4
width:
.zero 4
.globl fp_t
.align 8
.type fp_t, @object
.size fp_t, 8
fp_t:
.zero 8
.globl fp_s
.align 8
.type fp_s, @object
.size fp_s, 8
fp_s:
.zero 8
.globl image_t
.align 8
.type image_t, @object
.size image_t, 8
image_t:
.zero 8
.globl image_s
.align 8
.type image_s, @object
.size image_s, 8
image_s:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#define MASK_N 2
#define MASK_X 5
#define MASK_Y 5
#define SCALE 8
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
using namespace std;
unsigned char *image_s = NULL; // source image array
unsigned char *image_t = NULL; // target image array
FILE *fp_s = NULL; // source file handler
FILE *fp_t = NULL; // target file handler
unsigned int width, height; // image width, image height
unsigned int rgb_raw_data_offset;// rgb raw data offset
unsigned char bit_per_pixel; // bit per pixel
unsigned short byte_per_pixel; // byte per pixel
// bitmap header
unsigned char header[54] = {
0x42, // identity : B
0x4d, // identity : M
0, 0, 0, 0, // file size
0, 0, // reserved1
0, 0, // reserved2
54, 0, 0, 0, // RGB data offset
40, 0, 0, 0, // struct BITMAPINFOHEADER size
0, 0, 0, 0, // bmp width
0, 0, 0, 0, // bmp height
1, 0, // planes
24, 0, // bit per pixel
0, 0, 0, 0, // compression
0, 0, 0, 0, // data size
0, 0, 0, 0, // h resolution
0, 0, 0, 0, // v resolution
0, 0, 0, 0, // used colors
0, 0, 0, 0 // important colors
};
// sobel mask (5x5 version)
// Task 2: Put mask[][][] into Shared Memroy
int _mask[MASK_N][MASK_X][MASK_Y] = {
{{ -1, -4, -6, -4, -1},
{ -2, -8,-12, -8, -2},
{ 0, 0, 0, 0, 0},
{ 2, 8, 12, 8, 2},
{ 1, 4, 6, 4, 1}}
,
{{ -1, -2, 0, 2, 1},
{ -4, -8, 0, 8, 4},
{ -6,-12, 0, 12, 6},
{ -4, -8, 0, 8, 4},
{ -1, -2, 0, 2, 1}}
};
int read_bmp (const char *fname_s) {
fp_s = fopen(fname_s, "rb");
if (fp_s == NULL) {
printf("fopen fp_s error\n");
return -1;
}
// move offset to 10 to find rgb raw data offset
fseek(fp_s, 10, SEEK_SET);
fread(&rgb_raw_data_offset, sizeof(unsigned int), 1, fp_s);
// move offset to 18 to get width & height;
fseek(fp_s, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp_s);
fread(&height, sizeof(unsigned int), 1, fp_s);
// get bit per pixel
fseek(fp_s, 28, SEEK_SET);
fread(&bit_per_pixel, sizeof(unsigned short), 1, fp_s);
byte_per_pixel = bit_per_pixel / 8;
// move offset to rgb_raw_data_offset to get RGB raw data
fseek(fp_s, rgb_raw_data_offset, SEEK_SET);
// Task 3: Assign image_s to Pinnned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
int totalSize = width * height * byte_per_pixel;
totalSize = totalSize < 0 ? -totalSize : totalSize;
//image_s = (unsigned char *) malloc((size_t)totalSize);
cudaError_t err = cudaMallocHost(&image_s, (size_t)totalSize);
cudaCheckErrors("cuda_malloc_images_s error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_s error");
}
*/
/*
if (image_s == NULL) {
printf("malloc images_s errori, %d\n", totalSize);
return -1;
}
*/
// Task 3: Assign image_t to Pinned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
//image_t = (unsigned char *) malloc(totalSize);
err = cudaMallocHost(&image_t, (size_t)totalSize);
cudaCheckErrors("cuda_malloc_images_t error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_t error");
}
*/
/*
if (image_t == NULL) {
printf("malloc image_t error %d\n", totalSize);
return -1;
}
*/
fread(image_s, sizeof(unsigned char), (size_t)(long) totalSize, fp_s);
return 0;
}
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef unsigned short uint16;
// unsigned char *image_s = NULL; // source image array
// unsigned char *image_t = NULL; // target image array
// FILE *fp_s = NULL; // source file handler
//FILE *fp_t = NULL; // target file handler
// unsigned int width, height; // image width, image height
// unsigned int rgb_raw_data_offset;// rgb raw data offset
// unsigned char bit_per_pixel; // bit per pixel
// unsigned short byte_per_pixel; // byte per pixel
void DisplayHeader()
{
const int kb = 1024;
const int mb = kb * kb;
wcout << "NBody.GPU" << endl << "=========" << endl << endl;
//wcout << "CUDA version: v" << CUDART_VERSION << endl;
//wcout << "Thrust version: v" << THRUST_MAJOR_VERSION << "." << THRUST_MINOR_VERSION << endl << endl;
int devCount;
cudaGetDeviceCount(&devCount);
wcout << "CUDA Devices: " << endl << endl;
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
wcout << i << ": " << props.name << ": " << props.major << "." << props.minor << endl;
wcout << " Global memory: " << props.totalGlobalMem / mb << "mb" << endl;
wcout << " Shared memory: " << props.sharedMemPerBlock / kb << "kb" << endl;
wcout << " Constant memory: " << props.totalConstMem / kb << "kb" << endl;
wcout << " Block registers: " << props.regsPerBlock << endl << endl;
wcout << " Warp size: " << props.warpSize << endl;
wcout << " Threads per block: " << props.maxThreadsPerBlock << endl;
wcout << " Max block dimensions: [ " << props.maxThreadsDim[0] << ", " << props.maxThreadsDim[1] << ", " << props.maxThreadsDim[2] << " ]" << endl;
wcout << " Max grid dimensions: [ " << props.maxGridSize[0] << ", " << props.maxGridSize[1] << ", " << props.maxGridSize[2] << " ]" << endl;
wcout << endl;
}
}
__global__ void sobel(unsigned char *c_image_s, unsigned char *c_image_t,
unsigned int *c_width, unsigned int *c_height,
unsigned short *c_byte_per_pixel,
int* c_mask ) {
int x, y, i, v, u; // for loop counter
int R, G, B; // color of R, G, B
double val[MASK_N*3] = {0.0};
int adjustX, adjustY, xBound, yBound;
unsigned char *image_s = c_image_s;
unsigned char *image_t = c_image_t;
int width = *c_width;
int height = *c_height;
unsigned short byte_per_pixel = *c_byte_per_pixel;
__shared__ int mask[MASK_N][MASK_X][MASK_Y];
for (int i = 0; i < MASK_N; ++i) {
for (int j = 0; j < MASK_X; ++j) {
for(int k = 0; k < MASK_Y; ++k) {
mask[i][j][k] =
c_mask[i*MASK_Y*MASK_X + j*MASK_Y + k];
}
}
}
__syncthreads();
// Task 2: Put mask[][][] into Shared Memory
// Hint : Please declare it in kernel function
// Then use some threads to move data from global memory to shared memory
// Remember to __syncthreads() after it's done <WHY?>
// Task 1: Relabel x, y into combination of blockIdx, threadIdx ... etc
// Hint A: We do not have enough threads for each pixels in the image, so what should we do?
// Hint B: Maybe you can map each y to different threads in different blocks
int threadNum = blockDim.x;
int blockPerHeight = (width / threadNum) +
((width % threadNum) > 0 ? 1 : 0) ;
y = blockIdx.x / blockPerHeight;
x = threadNum * (blockIdx.x % blockPerHeight) + threadIdx.x;
if (y < height) {
if (x < width) {
for (i = 0; i < MASK_N; ++i) {
adjustX = (MASK_X % 2) ? 1 : 0;
adjustY = (MASK_Y % 2) ? 1 : 0;
xBound = MASK_X /2;
yBound = MASK_Y /2;
val[i*3+2] = 0.0;
val[i*3+1] = 0.0;
val[i*3] = 0.0;
for (v = -yBound; v < yBound + adjustY; ++v) {
for (u = -xBound; u < xBound + adjustX; ++u) {
if ((x + u) >= 0 && (x + u) < width && y + v >= 0 && y + v < height) {
R = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 2];
G = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 1];
B = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 0];
val[i*3+2] += R * mask[i][u + xBound][v + yBound];
val[i*3+1] += G * mask[i][u + xBound][v + yBound];
val[i*3+0] += B * mask[i][u + xBound][v + yBound];
}
}
}
}
double totalR = 0.0;
double totalG = 0.0;
double totalB = 0.0;
for (i = 0; i < MASK_N; ++i) {
totalR += val[i*3+2] * val[i*3+2];
totalG += val[i*3+1] * val[i*3+1];
totalB += val[i*3+0] * val[i*3+0];
}
totalR = sqrt(totalR) / SCALE;
totalG = sqrt(totalG) / SCALE;
totalB = sqrt(totalB) / SCALE;
const unsigned char cR = (totalR > 255.0) ? 255 : totalR;
const unsigned char cG = (totalG > 255.0) ? 255 : totalG;
const unsigned char cB = (totalB > 255.0) ? 255 : totalB;
image_t[ byte_per_pixel * (width * y + x) + 2 ] = cR;
image_t[ byte_per_pixel * (width * y + x) + 1 ] = cG;
image_t[ byte_per_pixel * (width * y + x) + 0 ] = cB;
}
}
}
int write_bmp (const char *fname_t) {
unsigned int file_size; // file size
fp_t = fopen(fname_t, "wb");
if (fp_t == NULL) {
printf("fopen fname_t error\n");
return -1;
}
// file size
file_size = width * height * byte_per_pixel + rgb_raw_data_offset;
header[2] = (unsigned char)(file_size & 0x000000ff);
header[3] = (file_size >> 8) & 0x000000ff;
header[4] = (file_size >> 16) & 0x000000ff;
header[5] = (file_size >> 24) & 0x000000ff;
// width
header[18] = width & 0x000000ff;
header[19] = (width >> 8) & 0x000000ff;
header[20] = (width >> 16) & 0x000000ff;
header[21] = (width >> 24) & 0x000000ff;
// height
header[22] = height &0x000000ff;
header[23] = (height >> 8) & 0x000000ff;
header[24] = (height >> 16) & 0x000000ff;
header[25] = (height >> 24) & 0x000000ff;
// bit per pixel
header[28] = bit_per_pixel;
// write header
fwrite(header, sizeof(unsigned char), rgb_raw_data_offset, fp_t);
// write image
fwrite(image_t, sizeof(unsigned char), (size_t)(long)width * height * byte_per_pixel, fp_t);
fclose(fp_s);
fclose(fp_t);
return 0;
}
int init_device ()
{ // Task 1: Device (GPU) Initialization
// Hint : cudaSetDevice()
cudaSetDevice(1);
return 0;
}
int
main(int argc, char **argv) {
init_device();
DisplayHeader();
const char *input = "candy.bmp";
if (argc > 1) input = argv[1];
read_bmp(input); // 24 bit gray level image
unsigned char *c_image_s = NULL; // source image array
unsigned char *c_image_t = NULL; // target image array
unsigned int *c_width, *c_height; // image width, image height
unsigned int *c_rgb_raw_data_offset;// rgb raw data offset
unsigned char *c_bit_per_pixel; // bit per pixel
unsigned short *c_byte_per_pixel; // byte per pixel
int *c_mask = NULL;
// Task 1: Allocate memory on GPU
// Hint : cudaMalloc ()
// What do we need to store on GPU? (input image, output image, ...
int mask1D[MASK_N * MASK_Y * MASK_X];
for (int i = 0; i < MASK_N; ++i)
for (int j = 0; j < MASK_X; ++j)
for(int k = 0; k < MASK_Y; ++k)
mask1D[i * MASK_X * MASK_Y + j * MASK_Y + k] = _mask[i][j][k];
cudaMalloc((void**)&c_image_t, (size_t)width * height * byte_per_pixel);
cudaMalloc((void**)&c_image_s, (size_t)width * height * byte_per_pixel);
cudaMalloc((void**)&c_width, (size_t)sizeof(int));
cudaMalloc((void**)&c_height, (size_t)sizeof(int));
cudaMalloc((void**)&c_rgb_raw_data_offset, (size_t)sizeof(int));
cudaMalloc((void**)&c_bit_per_pixel, (size_t)sizeof(char));
cudaMalloc((void**)&c_byte_per_pixel, (size_t)sizeof(short));
cudaMalloc((void**)&c_mask, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X);
cudaCheckErrors("cudamalloc fail");
/*
for (int i = 0; i < MASK_N; ++i)
cudaMalloc((void**)c_mask[i], sizeof(int*) * MASK_X);
*/
cudaMemcpy(c_mask, mask1D, sizeof(mask1D), cudaMemcpyHostToDevice);
// Task 1: Memory copy from Host to Device (GPU)
// Hint : cudaMemcpy ( ... , cudaMemcpyHostToDevice )
cudaMemcpy(c_width, &width, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_height, &height, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c_image_t, image_t, width * height * byte_per_pixel, cudaMemcpyHostToDevice);
cudaMemcpy(c_image_s, image_s, width * height * byte_per_pixel, cudaMemcpyHostToDevice);
cudaMemcpy(c_bit_per_pixel, &bit_per_pixel, sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(c_byte_per_pixel, &byte_per_pixel, sizeof(short), cudaMemcpyHostToDevice);
cudaCheckErrors("cuda memcpy fail");
// Hint : sobel_Kernel <<< ??? , ??? >>> ( ??? );
int blockNum = (width / 1024) + ((width % 1024) ? 1 : 0);
wcout << blockNum << endl;
blockNum = blockNum * height;
wcout << blockNum << endl;
sobel<<<blockNum, 1024, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X>>>( c_image_s, c_image_t,
c_width, c_height,
c_byte_per_pixel,
c_mask);
// Task 1: Memory Copy from Device (GPU) to Host
// Hint : cudaMemcpy ( ... , cudaMemcpyDeviceToHost )
// Task 1: Free memory on device
// Hint : cudaFree ( ... )
cudaMemcpy(image_t, c_image_t, (size_t)width * height * byte_per_pixel, cudaMemcpyDeviceToHost);
cudaCheckErrors("cuda memcpy back to host fail");
cudaFree(c_image_t);
cudaFree(c_image_s);
cudaFree(c_width);
cudaFree(c_height);
cudaFree(c_rgb_raw_data_offset);
cudaFree(c_bit_per_pixel);
cudaFree(c_byte_per_pixel);
write_bmp("out.bmp");
// Task 3: Free Pinned memory
// Hint : replace free ( ... ) by cudaFreeHost ( ... )
cudaFreeHost(image_s);
cudaFreeHost(image_t);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#define MASK_N 2
#define MASK_X 5
#define MASK_Y 5
#define SCALE 8
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
using namespace std;
unsigned char *image_s = NULL; // source image array
unsigned char *image_t = NULL; // target image array
FILE *fp_s = NULL; // source file handler
FILE *fp_t = NULL; // target file handler
unsigned int width, height; // image width, image height
unsigned int rgb_raw_data_offset;// rgb raw data offset
unsigned char bit_per_pixel; // bit per pixel
unsigned short byte_per_pixel; // byte per pixel
// bitmap header
unsigned char header[54] = {
0x42, // identity : B
0x4d, // identity : M
0, 0, 0, 0, // file size
0, 0, // reserved1
0, 0, // reserved2
54, 0, 0, 0, // RGB data offset
40, 0, 0, 0, // struct BITMAPINFOHEADER size
0, 0, 0, 0, // bmp width
0, 0, 0, 0, // bmp height
1, 0, // planes
24, 0, // bit per pixel
0, 0, 0, 0, // compression
0, 0, 0, 0, // data size
0, 0, 0, 0, // h resolution
0, 0, 0, 0, // v resolution
0, 0, 0, 0, // used colors
0, 0, 0, 0 // important colors
};
// sobel mask (5x5 version)
// Task 2: Put mask[][][] into Shared Memroy
int _mask[MASK_N][MASK_X][MASK_Y] = {
{{ -1, -4, -6, -4, -1},
{ -2, -8,-12, -8, -2},
{ 0, 0, 0, 0, 0},
{ 2, 8, 12, 8, 2},
{ 1, 4, 6, 4, 1}}
,
{{ -1, -2, 0, 2, 1},
{ -4, -8, 0, 8, 4},
{ -6,-12, 0, 12, 6},
{ -4, -8, 0, 8, 4},
{ -1, -2, 0, 2, 1}}
};
int read_bmp (const char *fname_s) {
fp_s = fopen(fname_s, "rb");
if (fp_s == NULL) {
printf("fopen fp_s error\n");
return -1;
}
// move offset to 10 to find rgb raw data offset
fseek(fp_s, 10, SEEK_SET);
fread(&rgb_raw_data_offset, sizeof(unsigned int), 1, fp_s);
// move offset to 18 to get width & height;
fseek(fp_s, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp_s);
fread(&height, sizeof(unsigned int), 1, fp_s);
// get bit per pixel
fseek(fp_s, 28, SEEK_SET);
fread(&bit_per_pixel, sizeof(unsigned short), 1, fp_s);
byte_per_pixel = bit_per_pixel / 8;
// move offset to rgb_raw_data_offset to get RGB raw data
fseek(fp_s, rgb_raw_data_offset, SEEK_SET);
// Task 3: Assign image_s to Pinnned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
int totalSize = width * height * byte_per_pixel;
totalSize = totalSize < 0 ? -totalSize : totalSize;
//image_s = (unsigned char *) malloc((size_t)totalSize);
hipError_t err = hipHostMalloc(&image_s, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_s error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_s error");
}
*/
/*
if (image_s == NULL) {
printf("malloc images_s errori, %d\n", totalSize);
return -1;
}
*/
// Task 3: Assign image_t to Pinned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
//image_t = (unsigned char *) malloc(totalSize);
err = hipHostMalloc(&image_t, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_t error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_t error");
}
*/
/*
if (image_t == NULL) {
printf("malloc image_t error %d\n", totalSize);
return -1;
}
*/
fread(image_s, sizeof(unsigned char), (size_t)(long) totalSize, fp_s);
return 0;
}
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef unsigned short uint16;
// unsigned char *image_s = NULL; // source image array
// unsigned char *image_t = NULL; // target image array
// FILE *fp_s = NULL; // source file handler
//FILE *fp_t = NULL; // target file handler
// unsigned int width, height; // image width, image height
// unsigned int rgb_raw_data_offset;// rgb raw data offset
// unsigned char bit_per_pixel; // bit per pixel
// unsigned short byte_per_pixel; // byte per pixel
void DisplayHeader()
{
const int kb = 1024;
const int mb = kb * kb;
wcout << "NBody.GPU" << endl << "=========" << endl << endl;
//wcout << "CUDA version: v" << CUDART_VERSION << endl;
//wcout << "Thrust version: v" << THRUST_MAJOR_VERSION << "." << THRUST_MINOR_VERSION << endl << endl;
int devCount;
hipGetDeviceCount(&devCount);
wcout << "CUDA Devices: " << endl << endl;
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
wcout << i << ": " << props.name << ": " << props.major << "." << props.minor << endl;
wcout << " Global memory: " << props.totalGlobalMem / mb << "mb" << endl;
wcout << " Shared memory: " << props.sharedMemPerBlock / kb << "kb" << endl;
wcout << " Constant memory: " << props.totalConstMem / kb << "kb" << endl;
wcout << " Block registers: " << props.regsPerBlock << endl << endl;
wcout << " Warp size: " << props.warpSize << endl;
wcout << " Threads per block: " << props.maxThreadsPerBlock << endl;
wcout << " Max block dimensions: [ " << props.maxThreadsDim[0] << ", " << props.maxThreadsDim[1] << ", " << props.maxThreadsDim[2] << " ]" << endl;
wcout << " Max grid dimensions: [ " << props.maxGridSize[0] << ", " << props.maxGridSize[1] << ", " << props.maxGridSize[2] << " ]" << endl;
wcout << endl;
}
}
__global__ void sobel(unsigned char *c_image_s, unsigned char *c_image_t,
unsigned int *c_width, unsigned int *c_height,
unsigned short *c_byte_per_pixel,
int* c_mask ) {
int x, y, i, v, u; // for loop counter
int R, G, B; // color of R, G, B
double val[MASK_N*3] = {0.0};
int adjustX, adjustY, xBound, yBound;
unsigned char *image_s = c_image_s;
unsigned char *image_t = c_image_t;
int width = *c_width;
int height = *c_height;
unsigned short byte_per_pixel = *c_byte_per_pixel;
__shared__ int mask[MASK_N][MASK_X][MASK_Y];
for (int i = 0; i < MASK_N; ++i) {
for (int j = 0; j < MASK_X; ++j) {
for(int k = 0; k < MASK_Y; ++k) {
mask[i][j][k] =
c_mask[i*MASK_Y*MASK_X + j*MASK_Y + k];
}
}
}
__syncthreads();
// Task 2: Put mask[][][] into Shared Memory
// Hint : Please declare it in kernel function
// Then use some threads to move data from global memory to shared memory
// Remember to __syncthreads() after it's done <WHY?>
// Task 1: Relabel x, y into combination of blockIdx, threadIdx ... etc
// Hint A: We do not have enough threads for each pixels in the image, so what should we do?
// Hint B: Maybe you can map each y to different threads in different blocks
int threadNum = blockDim.x;
int blockPerHeight = (width / threadNum) +
((width % threadNum) > 0 ? 1 : 0) ;
y = blockIdx.x / blockPerHeight;
x = threadNum * (blockIdx.x % blockPerHeight) + threadIdx.x;
if (y < height) {
if (x < width) {
for (i = 0; i < MASK_N; ++i) {
adjustX = (MASK_X % 2) ? 1 : 0;
adjustY = (MASK_Y % 2) ? 1 : 0;
xBound = MASK_X /2;
yBound = MASK_Y /2;
val[i*3+2] = 0.0;
val[i*3+1] = 0.0;
val[i*3] = 0.0;
for (v = -yBound; v < yBound + adjustY; ++v) {
for (u = -xBound; u < xBound + adjustX; ++u) {
if ((x + u) >= 0 && (x + u) < width && y + v >= 0 && y + v < height) {
R = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 2];
G = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 1];
B = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 0];
val[i*3+2] += R * mask[i][u + xBound][v + yBound];
val[i*3+1] += G * mask[i][u + xBound][v + yBound];
val[i*3+0] += B * mask[i][u + xBound][v + yBound];
}
}
}
}
double totalR = 0.0;
double totalG = 0.0;
double totalB = 0.0;
for (i = 0; i < MASK_N; ++i) {
totalR += val[i*3+2] * val[i*3+2];
totalG += val[i*3+1] * val[i*3+1];
totalB += val[i*3+0] * val[i*3+0];
}
totalR = sqrt(totalR) / SCALE;
totalG = sqrt(totalG) / SCALE;
totalB = sqrt(totalB) / SCALE;
const unsigned char cR = (totalR > 255.0) ? 255 : totalR;
const unsigned char cG = (totalG > 255.0) ? 255 : totalG;
const unsigned char cB = (totalB > 255.0) ? 255 : totalB;
image_t[ byte_per_pixel * (width * y + x) + 2 ] = cR;
image_t[ byte_per_pixel * (width * y + x) + 1 ] = cG;
image_t[ byte_per_pixel * (width * y + x) + 0 ] = cB;
}
}
}
int write_bmp (const char *fname_t) {
unsigned int file_size; // file size
fp_t = fopen(fname_t, "wb");
if (fp_t == NULL) {
printf("fopen fname_t error\n");
return -1;
}
// file size
file_size = width * height * byte_per_pixel + rgb_raw_data_offset;
header[2] = (unsigned char)(file_size & 0x000000ff);
header[3] = (file_size >> 8) & 0x000000ff;
header[4] = (file_size >> 16) & 0x000000ff;
header[5] = (file_size >> 24) & 0x000000ff;
// width
header[18] = width & 0x000000ff;
header[19] = (width >> 8) & 0x000000ff;
header[20] = (width >> 16) & 0x000000ff;
header[21] = (width >> 24) & 0x000000ff;
// height
header[22] = height &0x000000ff;
header[23] = (height >> 8) & 0x000000ff;
header[24] = (height >> 16) & 0x000000ff;
header[25] = (height >> 24) & 0x000000ff;
// bit per pixel
header[28] = bit_per_pixel;
// write header
fwrite(header, sizeof(unsigned char), rgb_raw_data_offset, fp_t);
// write image
fwrite(image_t, sizeof(unsigned char), (size_t)(long)width * height * byte_per_pixel, fp_t);
fclose(fp_s);
fclose(fp_t);
return 0;
}
int init_device ()
{ // Task 1: Device (GPU) Initialization
// Hint : cudaSetDevice()
hipSetDevice(1);
return 0;
}
int
main(int argc, char **argv) {
init_device();
DisplayHeader();
const char *input = "candy.bmp";
if (argc > 1) input = argv[1];
read_bmp(input); // 24 bit gray level image
unsigned char *c_image_s = NULL; // source image array
unsigned char *c_image_t = NULL; // target image array
unsigned int *c_width, *c_height; // image width, image height
unsigned int *c_rgb_raw_data_offset;// rgb raw data offset
unsigned char *c_bit_per_pixel; // bit per pixel
unsigned short *c_byte_per_pixel; // byte per pixel
int *c_mask = NULL;
// Task 1: Allocate memory on GPU
// Hint : cudaMalloc ()
// What do we need to store on GPU? (input image, output image, ...
int mask1D[MASK_N * MASK_Y * MASK_X];
for (int i = 0; i < MASK_N; ++i)
for (int j = 0; j < MASK_X; ++j)
for(int k = 0; k < MASK_Y; ++k)
mask1D[i * MASK_X * MASK_Y + j * MASK_Y + k] = _mask[i][j][k];
hipMalloc((void**)&c_image_t, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_image_s, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_width, (size_t)sizeof(int));
hipMalloc((void**)&c_height, (size_t)sizeof(int));
hipMalloc((void**)&c_rgb_raw_data_offset, (size_t)sizeof(int));
hipMalloc((void**)&c_bit_per_pixel, (size_t)sizeof(char));
hipMalloc((void**)&c_byte_per_pixel, (size_t)sizeof(short));
hipMalloc((void**)&c_mask, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X);
cudaCheckErrors("cudamalloc fail");
/*
for (int i = 0; i < MASK_N; ++i)
cudaMalloc((void**)c_mask[i], sizeof(int*) * MASK_X);
*/
hipMemcpy(c_mask, mask1D, sizeof(mask1D), hipMemcpyHostToDevice);
// Task 1: Memory copy from Host to Device (GPU)
// Hint : cudaMemcpy ( ... , cudaMemcpyHostToDevice )
hipMemcpy(c_width, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_height, &height, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_image_t, image_t, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_image_s, image_s, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_bit_per_pixel, &bit_per_pixel, sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(c_byte_per_pixel, &byte_per_pixel, sizeof(short), hipMemcpyHostToDevice);
cudaCheckErrors("cuda memcpy fail");
// Hint : sobel_Kernel <<< ??? , ??? >>> ( ??? );
int blockNum = (width / 1024) + ((width % 1024) ? 1 : 0);
wcout << blockNum << endl;
blockNum = blockNum * height;
wcout << blockNum << endl;
sobel<<<blockNum, 1024, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X>>>( c_image_s, c_image_t,
c_width, c_height,
c_byte_per_pixel,
c_mask);
// Task 1: Memory Copy from Device (GPU) to Host
// Hint : cudaMemcpy ( ... , cudaMemcpyDeviceToHost )
// Task 1: Free memory on device
// Hint : cudaFree ( ... )
hipMemcpy(image_t, c_image_t, (size_t)width * height * byte_per_pixel, hipMemcpyDeviceToHost);
cudaCheckErrors("cuda memcpy back to host fail");
hipFree(c_image_t);
hipFree(c_image_s);
hipFree(c_width);
hipFree(c_height);
hipFree(c_rgb_raw_data_offset);
hipFree(c_bit_per_pixel);
hipFree(c_byte_per_pixel);
write_bmp("out.bmp");
// Task 3: Free Pinned memory
// Hint : replace free ( ... ) by cudaFreeHost ( ... )
hipHostFree(image_s);
hipHostFree(image_t);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#define MASK_N 2
#define MASK_X 5
#define MASK_Y 5
#define SCALE 8
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
using namespace std;
unsigned char *image_s = NULL; // source image array
unsigned char *image_t = NULL; // target image array
FILE *fp_s = NULL; // source file handler
FILE *fp_t = NULL; // target file handler
unsigned int width, height; // image width, image height
unsigned int rgb_raw_data_offset;// rgb raw data offset
unsigned char bit_per_pixel; // bit per pixel
unsigned short byte_per_pixel; // byte per pixel
// bitmap header
unsigned char header[54] = {
0x42, // identity : B
0x4d, // identity : M
0, 0, 0, 0, // file size
0, 0, // reserved1
0, 0, // reserved2
54, 0, 0, 0, // RGB data offset
40, 0, 0, 0, // struct BITMAPINFOHEADER size
0, 0, 0, 0, // bmp width
0, 0, 0, 0, // bmp height
1, 0, // planes
24, 0, // bit per pixel
0, 0, 0, 0, // compression
0, 0, 0, 0, // data size
0, 0, 0, 0, // h resolution
0, 0, 0, 0, // v resolution
0, 0, 0, 0, // used colors
0, 0, 0, 0 // important colors
};
// sobel mask (5x5 version)
// Task 2: Put mask[][][] into Shared Memroy
int _mask[MASK_N][MASK_X][MASK_Y] = {
{{ -1, -4, -6, -4, -1},
{ -2, -8,-12, -8, -2},
{ 0, 0, 0, 0, 0},
{ 2, 8, 12, 8, 2},
{ 1, 4, 6, 4, 1}}
,
{{ -1, -2, 0, 2, 1},
{ -4, -8, 0, 8, 4},
{ -6,-12, 0, 12, 6},
{ -4, -8, 0, 8, 4},
{ -1, -2, 0, 2, 1}}
};
int read_bmp (const char *fname_s) {
fp_s = fopen(fname_s, "rb");
if (fp_s == NULL) {
printf("fopen fp_s error\n");
return -1;
}
// move offset to 10 to find rgb raw data offset
fseek(fp_s, 10, SEEK_SET);
fread(&rgb_raw_data_offset, sizeof(unsigned int), 1, fp_s);
// move offset to 18 to get width & height;
fseek(fp_s, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp_s);
fread(&height, sizeof(unsigned int), 1, fp_s);
// get bit per pixel
fseek(fp_s, 28, SEEK_SET);
fread(&bit_per_pixel, sizeof(unsigned short), 1, fp_s);
byte_per_pixel = bit_per_pixel / 8;
// move offset to rgb_raw_data_offset to get RGB raw data
fseek(fp_s, rgb_raw_data_offset, SEEK_SET);
// Task 3: Assign image_s to Pinnned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
int totalSize = width * height * byte_per_pixel;
totalSize = totalSize < 0 ? -totalSize : totalSize;
//image_s = (unsigned char *) malloc((size_t)totalSize);
hipError_t err = hipHostMalloc(&image_s, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_s error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_s error");
}
*/
/*
if (image_s == NULL) {
printf("malloc images_s errori, %d\n", totalSize);
return -1;
}
*/
// Task 3: Assign image_t to Pinned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
//image_t = (unsigned char *) malloc(totalSize);
err = hipHostMalloc(&image_t, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_t error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_t error");
}
*/
/*
if (image_t == NULL) {
printf("malloc image_t error %d\n", totalSize);
return -1;
}
*/
fread(image_s, sizeof(unsigned char), (size_t)(long) totalSize, fp_s);
return 0;
}
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef unsigned short uint16;
// unsigned char *image_s = NULL; // source image array
// unsigned char *image_t = NULL; // target image array
// FILE *fp_s = NULL; // source file handler
//FILE *fp_t = NULL; // target file handler
// unsigned int width, height; // image width, image height
// unsigned int rgb_raw_data_offset;// rgb raw data offset
// unsigned char bit_per_pixel; // bit per pixel
// unsigned short byte_per_pixel; // byte per pixel
void DisplayHeader()
{
const int kb = 1024;
const int mb = kb * kb;
wcout << "NBody.GPU" << endl << "=========" << endl << endl;
//wcout << "CUDA version: v" << CUDART_VERSION << endl;
//wcout << "Thrust version: v" << THRUST_MAJOR_VERSION << "." << THRUST_MINOR_VERSION << endl << endl;
int devCount;
hipGetDeviceCount(&devCount);
wcout << "CUDA Devices: " << endl << endl;
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
wcout << i << ": " << props.name << ": " << props.major << "." << props.minor << endl;
wcout << " Global memory: " << props.totalGlobalMem / mb << "mb" << endl;
wcout << " Shared memory: " << props.sharedMemPerBlock / kb << "kb" << endl;
wcout << " Constant memory: " << props.totalConstMem / kb << "kb" << endl;
wcout << " Block registers: " << props.regsPerBlock << endl << endl;
wcout << " Warp size: " << props.warpSize << endl;
wcout << " Threads per block: " << props.maxThreadsPerBlock << endl;
wcout << " Max block dimensions: [ " << props.maxThreadsDim[0] << ", " << props.maxThreadsDim[1] << ", " << props.maxThreadsDim[2] << " ]" << endl;
wcout << " Max grid dimensions: [ " << props.maxGridSize[0] << ", " << props.maxGridSize[1] << ", " << props.maxGridSize[2] << " ]" << endl;
wcout << endl;
}
}
__global__ void sobel(unsigned char *c_image_s, unsigned char *c_image_t,
unsigned int *c_width, unsigned int *c_height,
unsigned short *c_byte_per_pixel,
int* c_mask ) {
int x, y, i, v, u; // for loop counter
int R, G, B; // color of R, G, B
double val[MASK_N*3] = {0.0};
int adjustX, adjustY, xBound, yBound;
unsigned char *image_s = c_image_s;
unsigned char *image_t = c_image_t;
int width = *c_width;
int height = *c_height;
unsigned short byte_per_pixel = *c_byte_per_pixel;
__shared__ int mask[MASK_N][MASK_X][MASK_Y];
for (int i = 0; i < MASK_N; ++i) {
for (int j = 0; j < MASK_X; ++j) {
for(int k = 0; k < MASK_Y; ++k) {
mask[i][j][k] =
c_mask[i*MASK_Y*MASK_X + j*MASK_Y + k];
}
}
}
__syncthreads();
// Task 2: Put mask[][][] into Shared Memory
// Hint : Please declare it in kernel function
// Then use some threads to move data from global memory to shared memory
// Remember to __syncthreads() after it's done <WHY?>
// Task 1: Relabel x, y into combination of blockIdx, threadIdx ... etc
// Hint A: We do not have enough threads for each pixels in the image, so what should we do?
// Hint B: Maybe you can map each y to different threads in different blocks
int threadNum = blockDim.x;
int blockPerHeight = (width / threadNum) +
((width % threadNum) > 0 ? 1 : 0) ;
y = blockIdx.x / blockPerHeight;
x = threadNum * (blockIdx.x % blockPerHeight) + threadIdx.x;
if (y < height) {
if (x < width) {
for (i = 0; i < MASK_N; ++i) {
adjustX = (MASK_X % 2) ? 1 : 0;
adjustY = (MASK_Y % 2) ? 1 : 0;
xBound = MASK_X /2;
yBound = MASK_Y /2;
val[i*3+2] = 0.0;
val[i*3+1] = 0.0;
val[i*3] = 0.0;
for (v = -yBound; v < yBound + adjustY; ++v) {
for (u = -xBound; u < xBound + adjustX; ++u) {
if ((x + u) >= 0 && (x + u) < width && y + v >= 0 && y + v < height) {
R = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 2];
G = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 1];
B = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 0];
val[i*3+2] += R * mask[i][u + xBound][v + yBound];
val[i*3+1] += G * mask[i][u + xBound][v + yBound];
val[i*3+0] += B * mask[i][u + xBound][v + yBound];
}
}
}
}
double totalR = 0.0;
double totalG = 0.0;
double totalB = 0.0;
for (i = 0; i < MASK_N; ++i) {
totalR += val[i*3+2] * val[i*3+2];
totalG += val[i*3+1] * val[i*3+1];
totalB += val[i*3+0] * val[i*3+0];
}
totalR = sqrt(totalR) / SCALE;
totalG = sqrt(totalG) / SCALE;
totalB = sqrt(totalB) / SCALE;
const unsigned char cR = (totalR > 255.0) ? 255 : totalR;
const unsigned char cG = (totalG > 255.0) ? 255 : totalG;
const unsigned char cB = (totalB > 255.0) ? 255 : totalB;
image_t[ byte_per_pixel * (width * y + x) + 2 ] = cR;
image_t[ byte_per_pixel * (width * y + x) + 1 ] = cG;
image_t[ byte_per_pixel * (width * y + x) + 0 ] = cB;
}
}
}
int write_bmp (const char *fname_t) {
unsigned int file_size; // file size
fp_t = fopen(fname_t, "wb");
if (fp_t == NULL) {
printf("fopen fname_t error\n");
return -1;
}
// file size
file_size = width * height * byte_per_pixel + rgb_raw_data_offset;
header[2] = (unsigned char)(file_size & 0x000000ff);
header[3] = (file_size >> 8) & 0x000000ff;
header[4] = (file_size >> 16) & 0x000000ff;
header[5] = (file_size >> 24) & 0x000000ff;
// width
header[18] = width & 0x000000ff;
header[19] = (width >> 8) & 0x000000ff;
header[20] = (width >> 16) & 0x000000ff;
header[21] = (width >> 24) & 0x000000ff;
// height
header[22] = height &0x000000ff;
header[23] = (height >> 8) & 0x000000ff;
header[24] = (height >> 16) & 0x000000ff;
header[25] = (height >> 24) & 0x000000ff;
// bit per pixel
header[28] = bit_per_pixel;
// write header
fwrite(header, sizeof(unsigned char), rgb_raw_data_offset, fp_t);
// write image
fwrite(image_t, sizeof(unsigned char), (size_t)(long)width * height * byte_per_pixel, fp_t);
fclose(fp_s);
fclose(fp_t);
return 0;
}
int init_device ()
{ // Task 1: Device (GPU) Initialization
// Hint : cudaSetDevice()
hipSetDevice(1);
return 0;
}
int
main(int argc, char **argv) {
init_device();
DisplayHeader();
const char *input = "candy.bmp";
if (argc > 1) input = argv[1];
read_bmp(input); // 24 bit gray level image
unsigned char *c_image_s = NULL; // source image array
unsigned char *c_image_t = NULL; // target image array
unsigned int *c_width, *c_height; // image width, image height
unsigned int *c_rgb_raw_data_offset;// rgb raw data offset
unsigned char *c_bit_per_pixel; // bit per pixel
unsigned short *c_byte_per_pixel; // byte per pixel
int *c_mask = NULL;
// Task 1: Allocate memory on GPU
// Hint : cudaMalloc ()
// What do we need to store on GPU? (input image, output image, ...
int mask1D[MASK_N * MASK_Y * MASK_X];
for (int i = 0; i < MASK_N; ++i)
for (int j = 0; j < MASK_X; ++j)
for(int k = 0; k < MASK_Y; ++k)
mask1D[i * MASK_X * MASK_Y + j * MASK_Y + k] = _mask[i][j][k];
hipMalloc((void**)&c_image_t, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_image_s, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_width, (size_t)sizeof(int));
hipMalloc((void**)&c_height, (size_t)sizeof(int));
hipMalloc((void**)&c_rgb_raw_data_offset, (size_t)sizeof(int));
hipMalloc((void**)&c_bit_per_pixel, (size_t)sizeof(char));
hipMalloc((void**)&c_byte_per_pixel, (size_t)sizeof(short));
hipMalloc((void**)&c_mask, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X);
cudaCheckErrors("cudamalloc fail");
/*
for (int i = 0; i < MASK_N; ++i)
cudaMalloc((void**)c_mask[i], sizeof(int*) * MASK_X);
*/
hipMemcpy(c_mask, mask1D, sizeof(mask1D), hipMemcpyHostToDevice);
// Task 1: Memory copy from Host to Device (GPU)
// Hint : cudaMemcpy ( ... , cudaMemcpyHostToDevice )
hipMemcpy(c_width, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_height, &height, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_image_t, image_t, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_image_s, image_s, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_bit_per_pixel, &bit_per_pixel, sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(c_byte_per_pixel, &byte_per_pixel, sizeof(short), hipMemcpyHostToDevice);
cudaCheckErrors("cuda memcpy fail");
// Hint : sobel_Kernel <<< ??? , ??? >>> ( ??? );
int blockNum = (width / 1024) + ((width % 1024) ? 1 : 0);
wcout << blockNum << endl;
blockNum = blockNum * height;
wcout << blockNum << endl;
sobel<<<blockNum, 1024, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X>>>( c_image_s, c_image_t,
c_width, c_height,
c_byte_per_pixel,
c_mask);
// Task 1: Memory Copy from Device (GPU) to Host
// Hint : cudaMemcpy ( ... , cudaMemcpyDeviceToHost )
// Task 1: Free memory on device
// Hint : cudaFree ( ... )
hipMemcpy(image_t, c_image_t, (size_t)width * height * byte_per_pixel, hipMemcpyDeviceToHost);
cudaCheckErrors("cuda memcpy back to host fail");
hipFree(c_image_t);
hipFree(c_image_s);
hipFree(c_width);
hipFree(c_height);
hipFree(c_rgb_raw_data_offset);
hipFree(c_bit_per_pixel);
hipFree(c_byte_per_pixel);
write_bmp("out.bmp");
// Task 3: Free Pinned memory
// Hint : replace free ( ... ) by cudaFreeHost ( ... )
hipHostFree(image_s);
hipHostFree(image_t);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobelPhS_PjS0_PtPi
.globl _Z5sobelPhS_PjS0_PtPi
.p2align 8
.type _Z5sobelPhS_PjS0_PtPi,@function
_Z5sobelPhS_PjS0_PtPi:
s_load_b256 s[4:11], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_load_u16 v1, v1, s[8:9]
s_load_b32 s18, s[4:5], 0x0
s_load_b32 s20, s[6:7], 0x0
s_mov_b32 s6, 0
s_mov_b32 s7, 0
.p2align 6
.LBB0_1:
s_mov_b32 s8, s6
s_mov_b64 s[2:3], s[10:11]
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
s_mov_b32 s12, 0
s_mov_b64 s[4:5], s[2:3]
.LBB0_3:
s_load_b32 s13, s[4:5], 0x0
s_add_i32 s14, s8, s12
s_add_i32 s12, s12, 4
v_mov_b32_e32 v2, s14
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s12, 20
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v3, s13
ds_store_b32 v2, v3
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 1
s_add_u32 s2, s2, 20
s_addc_u32 s3, s3, 0
s_add_i32 s8, s8, 20
s_cmp_eq_u32 s9, 5
s_cbranch_scc0 .LBB0_2
s_add_i32 s2, s7, 1
s_add_u32 s10, s10, 0x64
s_addc_u32 s11, s11, 0
s_addk_i32 s6, 0x64
s_cmp_lg_u32 s7, 0
s_mov_b32 s7, s2
s_cbranch_scc0 .LBB0_1
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x3c
s_ashr_i32 s7, s18, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s18, s7
s_xor_b32 s8, s8, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
s_xor_b32 s3, s7, s3
v_cvt_f32_u32_e32 v2, s4
s_sub_i32 s6, 0, s4
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s4
s_add_i32 s7, s5, 1
s_sub_i32 s6, s8, s6
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s5, s7, s5
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s5, 1
s_cmp_ge_u32 s6, s4
s_cselect_b32 s4, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
s_sub_i32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s3, s2
s_sub_i32 s4, s18, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_gt_i32 s4, 0
s_cselect_b32 s4, -1, 0
s_cmp_lg_u32 s4, 0
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s3
s_sub_i32 s5, 0, s3
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s5
s_mul_hi_u32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s15, s5
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s19, s6, s4
s_mov_b32 s4, 0
s_mul_i32 s3, s19, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_sub_i32 s3, s15, s3
s_cmp_lt_i32 s19, s20
s_mul_i32 s2, s3, s2
s_cselect_b32 s3, -1, 0
v_add_nc_u32_e32 v16, s2, v0
v_cmp_gt_i32_e32 vcc_lo, s18, v16
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_19
s_load_b64 s[16:17], s[0:1], 0x0
v_add3_u32 v17, v0, s2, -2
s_add_i32 s2, s19, -2
s_mov_b32 s5, s4
s_mov_b32 s6, s4
s_mov_b32 s7, s4
s_mov_b32 s8, s4
s_mov_b32 s9, s4
s_mov_b32 s10, s4
s_mov_b32 s11, s4
s_mov_b32 s12, s4
s_mov_b32 s13, s4
s_mov_b32 s14, s4
s_mov_b32 s15, s4
v_and_b32_e32 v23, 0xffff, v1
v_mad_u64_u32 v[0:1], null, s18, s2, v[17:18]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v18, v0, v23
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
v_mul_lo_u32 v19, s18, v23
v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v4, s8
v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v6, s10
v_dual_mov_b32 v7, s11 :: v_dual_mov_b32 v8, s12
v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
v_dual_mov_b32 v11, s15 :: v_dual_mov_b32 v12, s16
v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
v_mov_b32_e32 v15, s19
.LBB0_8:
s_mul_i32 s2, s3, 3
v_mov_b32_e32 v20, v18
s_add_i32 s5, s2, 2
s_mov_b32 s8, s4
s_lshl_b32 s6, s5, 1
s_lshl_b32 s5, s5, 1
s_mov_b32 m0, s6
s_add_i32 s6, s2, 1
v_movreld_b32_e32 v0, 0
s_lshl_b32 s7, s6, 1
v_movreld_b32_e32 v1, 0
s_mov_b32 m0, s7
s_lshl_b32 s7, s2, 1
v_movreld_b32_e32 v0, 0
v_movreld_b32_e32 v1, 0
s_mov_b32 m0, s7
s_lshl_b32 s6, s6, 1
s_lshl_b32 s7, s2, 1
s_mov_b32 s9, -2
v_movreld_b32_e32 v0, 0
v_movreld_b32_e32 v1, 0
s_branch .LBB0_10
.LBB0_9:
v_add_nc_u32_e32 v20, v20, v19
s_add_i32 s9, s9, 1
s_add_i32 s8, s8, 4
s_cmp_lg_u32 s9, 3
s_cbranch_scc0 .LBB0_14
.LBB0_10:
s_add_i32 s2, s9, s19
v_dual_mov_b32 v21, v20 :: v_dual_mov_b32 v22, v17
s_cmp_lt_i32 s2, 0
s_movk_i32 s11, 0xff9c
s_cselect_b32 s10, -1, 0
s_cmp_ge_i32 s2, s20
s_cselect_b32 s12, -1, 0
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v22, 1, v22
v_add_nc_u32_e32 v21, v21, v23
s_add_i32 s11, s11, 20
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_cbranch_scc0 .LBB0_9
.LBB0_12:
v_cmp_gt_i32_e32 vcc_lo, 0, v22
v_cmp_le_i32_e64 s2, s18, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_or_b32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s12
s_xor_b32 s13, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s13
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v25, 31, v21
v_add_co_u32 v24, vcc_lo, s16, v21
s_add_i32 s13, s8, s11
s_mov_b32 m0, s5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v25, vcc_lo, s17, v25, vcc_lo
v_movrels_b32_e32 v27, v1
s_clause 0x2
global_load_u8 v26, v[24:25], off offset:2
global_load_u8 v28, v[24:25], off offset:1
global_load_u8 v29, v[24:25], off
v_mov_b32_e32 v24, s13
ds_load_b32 v30, v24 offset:100
s_waitcnt vmcnt(2) lgkmcnt(0)
v_mul_lo_u32 v24, v30, v26
v_movrels_b32_e32 v26, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[24:25], v24
v_add_f64 v[24:25], v[26:27], v[24:25]
s_waitcnt vmcnt(1)
v_mul_lo_u32 v26, v30, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[26:27], v26
v_movreld_b32_e32 v0, v24
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_movreld_b32_e32 v1, v25
s_mov_b32 m0, s6
v_movrels_b32_e32 v25, v1
v_movrels_b32_e32 v24, v0
v_add_f64 v[24:25], v[24:25], v[26:27]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v26, v30, v29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[26:27], v26
v_movreld_b32_e32 v0, v24
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_movreld_b32_e32 v1, v25
s_mov_b32 m0, s7
v_movrels_b32_e32 v25, v1
v_movrels_b32_e32 v24, v0
v_add_f64 v[24:25], v[24:25], v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_movreld_b32_e32 v0, v24
v_movreld_b32_e32 v1, v25
s_branch .LBB0_11
.LBB0_14:
s_add_i32 s2, s3, 1
s_addk_i32 s4, 0x64
s_cmp_eq_u32 s3, 0
s_cbranch_scc0 .LBB0_16
s_mov_b32 s3, s2
s_branch .LBB0_8
.LBB0_16:
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_mov_b64 s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v20, v18 :: v_dual_mov_b32 v19, v17
v_dual_mov_b32 v22, v18 :: v_dual_mov_b32 v21, v17
.p2align 6
.LBB0_17:
s_lshl_b32 s4, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s4, 3
s_add_i32 s6, s4, 2
s_mov_b32 m0, s5
v_movrels_b32_e32 v25, v0
s_mov_b32 m0, s6
v_movrels_b32_e32 v24, v0
s_mov_b32 m0, s4
v_movrels_b32_e32 v27, v1
v_movrels_b32_e32 v26, v0
s_add_i32 m0, s4, -1
v_fma_f64 v[21:22], v[24:25], v[24:25], v[21:22]
v_movrels_b32_e32 v29, v0
s_add_i32 m0, s4, -2
v_fma_f64 v[19:20], v[26:27], v[26:27], v[19:20]
v_movrels_b32_e32 v28, v0
s_add_u32 s2, s2, 3
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[17:18], v[28:29], v[28:29], v[17:18]
s_cbranch_scc1 .LBB0_17
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_f64_e64 s2, 0x10000000, v[19:20]
v_cmp_gt_f64_e64 s3, 0x10000000, v[17:18]
s_load_b64 s[0:1], s[0:1], 0x8
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, 0, 1, s2
v_cndmask_b32_e64 v2, 0, 1, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v0, 8, v0
v_lshlrev_b32_e32 v3, 8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v4, 8, v2
v_ldexp_f64 v[0:1], v[21:22], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[2:3], v[19:20], v3
v_rsq_f64_e32 v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_rsq_f64_e32 v[8:9], v[2:3]
s_waitcnt_depctr 0xfff
v_mul_f64 v[12:13], v[0:1], v[6:7]
v_mul_f64 v[6:7], v[6:7], 0.5
v_mul_f64 v[14:15], v[2:3], v[8:9]
v_mul_f64 v[8:9], v[8:9], 0.5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[19:20], -v[6:7], v[12:13], 0.5
v_fma_f64 v[21:22], -v[8:9], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[12:13], v[19:20], v[12:13]
v_fma_f64 v[6:7], v[6:7], v[19:20], v[6:7]
v_fma_f64 v[14:15], v[14:15], v[21:22], v[14:15]
v_fma_f64 v[8:9], v[8:9], v[21:22], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[19:20], -v[12:13], v[12:13], v[0:1]
v_fma_f64 v[21:22], -v[14:15], v[14:15], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[19:20], v[6:7], v[12:13]
v_fma_f64 v[14:15], v[21:22], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[19:20], -v[12:13], v[12:13], v[0:1]
v_fma_f64 v[21:22], -v[14:15], v[14:15], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], v[19:20], v[6:7], v[12:13]
v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
v_fma_f64 v[8:9], v[21:22], v[8:9], v[14:15]
v_cndmask_b32_e64 v13, 0, 0xffffff80, s2
v_cndmask_b32_e64 v14, 0, 0xffffff80, s3
v_cmp_class_f64_e64 s2, v[2:3], 0x260
v_ldexp_f64 v[6:7], v[6:7], v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[8:9], v[8:9], v13
v_dual_cndmask_b32 v1, v7, v1 :: v_dual_cndmask_b32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v9, v3, s2
v_cndmask_b32_e64 v2, v8, v2, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[0:1], v[0:1], -3
v_ldexp_f64 v[2:3], v[2:3], -3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[0:1]
v_cmp_nlt_f64_e64 s2, 0x406fe000, v[2:3]
v_cndmask_b32_e32 v1, 0x406fe000, v1, vcc_lo
v_ldexp_f64 v[4:5], v[17:18], v4
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, 0x406fe000, v3, s2
v_cndmask_b32_e64 v2, 0, v2, s2
v_cvt_i32_f64_e32 v6, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[2:3]
v_rsq_f64_e32 v[10:11], v[4:5]
v_cmp_class_f64_e64 s3, v[4:5], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[17:18], v[4:5], v[10:11]
v_mul_f64 v[10:11], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[24:25], -v[10:11], v[17:18], 0.5
v_fma_f64 v[17:18], v[17:18], v[24:25], v[17:18]
v_fma_f64 v[10:11], v[10:11], v[24:25], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[24:25], -v[17:18], v[17:18], v[4:5]
v_fma_f64 v[17:18], v[24:25], v[10:11], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[24:25], -v[17:18], v[17:18], v[4:5]
v_mad_u64_u32 v[0:1], null, s19, s18, v[16:17]
v_mul_lo_u32 v0, v0, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_fma_f64 v[10:11], v[24:25], v[10:11], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[10:11], v[10:11], v14
v_cndmask_b32_e64 v5, v11, v5, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v10, v4, s3
v_ldexp_f64 v[4:5], v[4:5], -3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e64 s3, 0x406fe000, v[4:5]
v_cndmask_b32_e64 v5, 0x406fe000, v5, s3
v_cndmask_b32_e64 v4, 0, v4, s3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v3, v[4:5]
s_clause 0x2
global_store_b8 v[0:1], v6, off offset:2
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v3, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sobelPhS_PjS0_PtPi
.amdhsa_group_segment_fixed_size 200
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sobelPhS_PjS0_PtPi, .Lfunc_end0-_Z5sobelPhS_PjS0_PtPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 200
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sobelPhS_PjS0_PtPi
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z5sobelPhS_PjS0_PtPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#define MASK_N 2
#define MASK_X 5
#define MASK_Y 5
#define SCALE 8
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
using namespace std;
unsigned char *image_s = NULL; // source image array
unsigned char *image_t = NULL; // target image array
FILE *fp_s = NULL; // source file handler
FILE *fp_t = NULL; // target file handler
unsigned int width, height; // image width, image height
unsigned int rgb_raw_data_offset;// rgb raw data offset
unsigned char bit_per_pixel; // bit per pixel
unsigned short byte_per_pixel; // byte per pixel
// bitmap header
unsigned char header[54] = {
0x42, // identity : B
0x4d, // identity : M
0, 0, 0, 0, // file size
0, 0, // reserved1
0, 0, // reserved2
54, 0, 0, 0, // RGB data offset
40, 0, 0, 0, // struct BITMAPINFOHEADER size
0, 0, 0, 0, // bmp width
0, 0, 0, 0, // bmp height
1, 0, // planes
24, 0, // bit per pixel
0, 0, 0, 0, // compression
0, 0, 0, 0, // data size
0, 0, 0, 0, // h resolution
0, 0, 0, 0, // v resolution
0, 0, 0, 0, // used colors
0, 0, 0, 0 // important colors
};
// sobel mask (5x5 version)
// Task 2: Put mask[][][] into Shared Memroy
int _mask[MASK_N][MASK_X][MASK_Y] = {
{{ -1, -4, -6, -4, -1},
{ -2, -8,-12, -8, -2},
{ 0, 0, 0, 0, 0},
{ 2, 8, 12, 8, 2},
{ 1, 4, 6, 4, 1}}
,
{{ -1, -2, 0, 2, 1},
{ -4, -8, 0, 8, 4},
{ -6,-12, 0, 12, 6},
{ -4, -8, 0, 8, 4},
{ -1, -2, 0, 2, 1}}
};
int read_bmp (const char *fname_s) {
fp_s = fopen(fname_s, "rb");
if (fp_s == NULL) {
printf("fopen fp_s error\n");
return -1;
}
// move offset to 10 to find rgb raw data offset
fseek(fp_s, 10, SEEK_SET);
fread(&rgb_raw_data_offset, sizeof(unsigned int), 1, fp_s);
// move offset to 18 to get width & height;
fseek(fp_s, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp_s);
fread(&height, sizeof(unsigned int), 1, fp_s);
// get bit per pixel
fseek(fp_s, 28, SEEK_SET);
fread(&bit_per_pixel, sizeof(unsigned short), 1, fp_s);
byte_per_pixel = bit_per_pixel / 8;
// move offset to rgb_raw_data_offset to get RGB raw data
fseek(fp_s, rgb_raw_data_offset, SEEK_SET);
// Task 3: Assign image_s to Pinnned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
int totalSize = width * height * byte_per_pixel;
totalSize = totalSize < 0 ? -totalSize : totalSize;
//image_s = (unsigned char *) malloc((size_t)totalSize);
hipError_t err = hipHostMalloc(&image_s, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_s error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_s error");
}
*/
/*
if (image_s == NULL) {
printf("malloc images_s errori, %d\n", totalSize);
return -1;
}
*/
// Task 3: Assign image_t to Pinned Memory
// Hint : err = cudaMallocHost ( ... )
// if (err != CUDA_SUCCESS)
//image_t = (unsigned char *) malloc(totalSize);
err = hipHostMalloc(&image_t, (size_t)totalSize, hipHostMallocDefault);
cudaCheckErrors("cuda_malloc_images_t error");
/*
if (err != CUDA_SUCCESS) {
cudaCheckErrors("cuda_malloc_images_t error");
}
*/
/*
if (image_t == NULL) {
printf("malloc image_t error %d\n", totalSize);
return -1;
}
*/
fread(image_s, sizeof(unsigned char), (size_t)(long) totalSize, fp_s);
return 0;
}
typedef unsigned char uint8;
typedef unsigned int uint32;
typedef unsigned short uint16;
// unsigned char *image_s = NULL; // source image array
// unsigned char *image_t = NULL; // target image array
// FILE *fp_s = NULL; // source file handler
//FILE *fp_t = NULL; // target file handler
// unsigned int width, height; // image width, image height
// unsigned int rgb_raw_data_offset;// rgb raw data offset
// unsigned char bit_per_pixel; // bit per pixel
// unsigned short byte_per_pixel; // byte per pixel
void DisplayHeader()
{
const int kb = 1024;
const int mb = kb * kb;
wcout << "NBody.GPU" << endl << "=========" << endl << endl;
//wcout << "CUDA version: v" << CUDART_VERSION << endl;
//wcout << "Thrust version: v" << THRUST_MAJOR_VERSION << "." << THRUST_MINOR_VERSION << endl << endl;
int devCount;
hipGetDeviceCount(&devCount);
wcout << "CUDA Devices: " << endl << endl;
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
wcout << i << ": " << props.name << ": " << props.major << "." << props.minor << endl;
wcout << " Global memory: " << props.totalGlobalMem / mb << "mb" << endl;
wcout << " Shared memory: " << props.sharedMemPerBlock / kb << "kb" << endl;
wcout << " Constant memory: " << props.totalConstMem / kb << "kb" << endl;
wcout << " Block registers: " << props.regsPerBlock << endl << endl;
wcout << " Warp size: " << props.warpSize << endl;
wcout << " Threads per block: " << props.maxThreadsPerBlock << endl;
wcout << " Max block dimensions: [ " << props.maxThreadsDim[0] << ", " << props.maxThreadsDim[1] << ", " << props.maxThreadsDim[2] << " ]" << endl;
wcout << " Max grid dimensions: [ " << props.maxGridSize[0] << ", " << props.maxGridSize[1] << ", " << props.maxGridSize[2] << " ]" << endl;
wcout << endl;
}
}
__global__ void sobel(unsigned char *c_image_s, unsigned char *c_image_t,
unsigned int *c_width, unsigned int *c_height,
unsigned short *c_byte_per_pixel,
int* c_mask ) {
int x, y, i, v, u; // for loop counter
int R, G, B; // color of R, G, B
double val[MASK_N*3] = {0.0};
int adjustX, adjustY, xBound, yBound;
unsigned char *image_s = c_image_s;
unsigned char *image_t = c_image_t;
int width = *c_width;
int height = *c_height;
unsigned short byte_per_pixel = *c_byte_per_pixel;
__shared__ int mask[MASK_N][MASK_X][MASK_Y];
for (int i = 0; i < MASK_N; ++i) {
for (int j = 0; j < MASK_X; ++j) {
for(int k = 0; k < MASK_Y; ++k) {
mask[i][j][k] =
c_mask[i*MASK_Y*MASK_X + j*MASK_Y + k];
}
}
}
__syncthreads();
// Task 2: Put mask[][][] into Shared Memory
// Hint : Please declare it in kernel function
// Then use some threads to move data from global memory to shared memory
// Remember to __syncthreads() after it's done <WHY?>
// Task 1: Relabel x, y into combination of blockIdx, threadIdx ... etc
// Hint A: We do not have enough threads for each pixels in the image, so what should we do?
// Hint B: Maybe you can map each y to different threads in different blocks
int threadNum = blockDim.x;
int blockPerHeight = (width / threadNum) +
((width % threadNum) > 0 ? 1 : 0) ;
y = blockIdx.x / blockPerHeight;
x = threadNum * (blockIdx.x % blockPerHeight) + threadIdx.x;
if (y < height) {
if (x < width) {
for (i = 0; i < MASK_N; ++i) {
adjustX = (MASK_X % 2) ? 1 : 0;
adjustY = (MASK_Y % 2) ? 1 : 0;
xBound = MASK_X /2;
yBound = MASK_Y /2;
val[i*3+2] = 0.0;
val[i*3+1] = 0.0;
val[i*3] = 0.0;
for (v = -yBound; v < yBound + adjustY; ++v) {
for (u = -xBound; u < xBound + adjustX; ++u) {
if ((x + u) >= 0 && (x + u) < width && y + v >= 0 && y + v < height) {
R = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 2];
G = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 1];
B = image_s[byte_per_pixel * (width * (y+v) + (x+u)) + 0];
val[i*3+2] += R * mask[i][u + xBound][v + yBound];
val[i*3+1] += G * mask[i][u + xBound][v + yBound];
val[i*3+0] += B * mask[i][u + xBound][v + yBound];
}
}
}
}
double totalR = 0.0;
double totalG = 0.0;
double totalB = 0.0;
for (i = 0; i < MASK_N; ++i) {
totalR += val[i*3+2] * val[i*3+2];
totalG += val[i*3+1] * val[i*3+1];
totalB += val[i*3+0] * val[i*3+0];
}
totalR = sqrt(totalR) / SCALE;
totalG = sqrt(totalG) / SCALE;
totalB = sqrt(totalB) / SCALE;
const unsigned char cR = (totalR > 255.0) ? 255 : totalR;
const unsigned char cG = (totalG > 255.0) ? 255 : totalG;
const unsigned char cB = (totalB > 255.0) ? 255 : totalB;
image_t[ byte_per_pixel * (width * y + x) + 2 ] = cR;
image_t[ byte_per_pixel * (width * y + x) + 1 ] = cG;
image_t[ byte_per_pixel * (width * y + x) + 0 ] = cB;
}
}
}
int write_bmp (const char *fname_t) {
unsigned int file_size; // file size
fp_t = fopen(fname_t, "wb");
if (fp_t == NULL) {
printf("fopen fname_t error\n");
return -1;
}
// file size
file_size = width * height * byte_per_pixel + rgb_raw_data_offset;
header[2] = (unsigned char)(file_size & 0x000000ff);
header[3] = (file_size >> 8) & 0x000000ff;
header[4] = (file_size >> 16) & 0x000000ff;
header[5] = (file_size >> 24) & 0x000000ff;
// width
header[18] = width & 0x000000ff;
header[19] = (width >> 8) & 0x000000ff;
header[20] = (width >> 16) & 0x000000ff;
header[21] = (width >> 24) & 0x000000ff;
// height
header[22] = height &0x000000ff;
header[23] = (height >> 8) & 0x000000ff;
header[24] = (height >> 16) & 0x000000ff;
header[25] = (height >> 24) & 0x000000ff;
// bit per pixel
header[28] = bit_per_pixel;
// write header
fwrite(header, sizeof(unsigned char), rgb_raw_data_offset, fp_t);
// write image
fwrite(image_t, sizeof(unsigned char), (size_t)(long)width * height * byte_per_pixel, fp_t);
fclose(fp_s);
fclose(fp_t);
return 0;
}
int init_device ()
{ // Task 1: Device (GPU) Initialization
// Hint : cudaSetDevice()
hipSetDevice(1);
return 0;
}
int
main(int argc, char **argv) {
init_device();
DisplayHeader();
const char *input = "candy.bmp";
if (argc > 1) input = argv[1];
read_bmp(input); // 24 bit gray level image
unsigned char *c_image_s = NULL; // source image array
unsigned char *c_image_t = NULL; // target image array
unsigned int *c_width, *c_height; // image width, image height
unsigned int *c_rgb_raw_data_offset;// rgb raw data offset
unsigned char *c_bit_per_pixel; // bit per pixel
unsigned short *c_byte_per_pixel; // byte per pixel
int *c_mask = NULL;
// Task 1: Allocate memory on GPU
// Hint : cudaMalloc ()
// What do we need to store on GPU? (input image, output image, ...
int mask1D[MASK_N * MASK_Y * MASK_X];
for (int i = 0; i < MASK_N; ++i)
for (int j = 0; j < MASK_X; ++j)
for(int k = 0; k < MASK_Y; ++k)
mask1D[i * MASK_X * MASK_Y + j * MASK_Y + k] = _mask[i][j][k];
hipMalloc((void**)&c_image_t, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_image_s, (size_t)width * height * byte_per_pixel);
hipMalloc((void**)&c_width, (size_t)sizeof(int));
hipMalloc((void**)&c_height, (size_t)sizeof(int));
hipMalloc((void**)&c_rgb_raw_data_offset, (size_t)sizeof(int));
hipMalloc((void**)&c_bit_per_pixel, (size_t)sizeof(char));
hipMalloc((void**)&c_byte_per_pixel, (size_t)sizeof(short));
hipMalloc((void**)&c_mask, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X);
cudaCheckErrors("cudamalloc fail");
/*
for (int i = 0; i < MASK_N; ++i)
cudaMalloc((void**)c_mask[i], sizeof(int*) * MASK_X);
*/
hipMemcpy(c_mask, mask1D, sizeof(mask1D), hipMemcpyHostToDevice);
// Task 1: Memory copy from Host to Device (GPU)
// Hint : cudaMemcpy ( ... , cudaMemcpyHostToDevice )
hipMemcpy(c_width, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_height, &height, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c_image_t, image_t, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_image_s, image_s, width * height * byte_per_pixel, hipMemcpyHostToDevice);
hipMemcpy(c_bit_per_pixel, &bit_per_pixel, sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(c_byte_per_pixel, &byte_per_pixel, sizeof(short), hipMemcpyHostToDevice);
cudaCheckErrors("cuda memcpy fail");
// Hint : sobel_Kernel <<< ??? , ??? >>> ( ??? );
int blockNum = (width / 1024) + ((width % 1024) ? 1 : 0);
wcout << blockNum << endl;
blockNum = blockNum * height;
wcout << blockNum << endl;
sobel<<<blockNum, 1024, (size_t)sizeof(int) * MASK_N * MASK_Y * MASK_X>>>( c_image_s, c_image_t,
c_width, c_height,
c_byte_per_pixel,
c_mask);
// Task 1: Memory Copy from Device (GPU) to Host
// Hint : cudaMemcpy ( ... , cudaMemcpyDeviceToHost )
// Task 1: Free memory on device
// Hint : cudaFree ( ... )
hipMemcpy(image_t, c_image_t, (size_t)width * height * byte_per_pixel, hipMemcpyDeviceToHost);
cudaCheckErrors("cuda memcpy back to host fail");
hipFree(c_image_t);
hipFree(c_image_s);
hipFree(c_width);
hipFree(c_height);
hipFree(c_rgb_raw_data_offset);
hipFree(c_bit_per_pixel);
hipFree(c_byte_per_pixel);
write_bmp("out.bmp");
// Task 3: Free Pinned memory
// Hint : replace free ( ... ) by cudaFreeHost ( ... )
hipHostFree(image_s);
hipHostFree(image_t);
} | .text
.file "sobel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8read_bmpPKc # -- Begin function _Z8read_bmpPKc
.p2align 4, 0x90
.type _Z8read_bmpPKc,@function
_Z8read_bmpPKc: # @_Z8read_bmpPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.L.str, %esi
callq fopen
movq %rax, fp_s(%rip)
testq %rax, %rax
je .LBB0_1
# %bb.2:
movl $10, %esi
movq %rax, %rdi
xorl %edx, %edx
callq fseek
movq fp_s(%rip), %rcx
movl $rgb_raw_data_offset, %edi
movl $4, %esi
movl $1, %edx
callq fread
movq fp_s(%rip), %rdi
movl $18, %esi
xorl %edx, %edx
callq fseek
movq fp_s(%rip), %rcx
movl $width, %edi
movl $4, %esi
movl $1, %edx
callq fread
movq fp_s(%rip), %rcx
movl $height, %edi
movl $4, %esi
movl $1, %edx
callq fread
movq fp_s(%rip), %rdi
movl $28, %esi
xorl %edx, %edx
callq fseek
movq fp_s(%rip), %rcx
movl $bit_per_pixel, %edi
movl $2, %esi
movl $1, %edx
callq fread
movzbl bit_per_pixel(%rip), %eax
shrl $3, %eax
movw %ax, byte_per_pixel(%rip)
movq fp_s(%rip), %rdi
movl rgb_raw_data_offset(%rip), %esi
xorl %edx, %edx
callq fseek
movl height(%rip), %eax
imull width(%rip), %eax
movzwl byte_per_pixel(%rip), %ecx
imull %eax, %ecx
movl %ecx, %ebx
negl %ebx
cmovsl %ecx, %ebx
movl $image_s, %edi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_3
# %bb.5:
xorl %ebp, %ebp
movl $image_t, %edi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_6
# %bb.7:
movq image_s(%rip), %rdi
movq fp_s(%rip), %rcx
movl $1, %esi
movq %rbx, %rdx
callq fread
jmp .LBB0_8
.LBB0_1:
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %ebp
.LBB0_8:
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $108, %r9d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.6, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $125, %r9d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8read_bmpPKc, .Lfunc_end0-_Z8read_bmpPKc
.cfi_endproc
# -- End function
.globl _Z13DisplayHeaderv # -- Begin function _Z13DisplayHeaderv
.p2align 4, 0x90
.type _Z13DisplayHeaderv,@function
_Z13DisplayHeaderv: # @_Z13DisplayHeaderv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt5wcout, %edi
movl $.L.str.7, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.1: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.2: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit5
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.3: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit7
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt5wcout, %edi
movl $.L.str.9, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.4: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit9
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.5: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit11
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
cmpl $0, 12(%rsp)
jle .LBB1_19
# %bb.6: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt5wcout, %edi
movl %ebx, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.10, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl $.L.str.10, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 376(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.11, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 380(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.8: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit13
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.12, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq 304(%rsp), %rsi
shrq $20, %rsi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_
movl $.L.str.13, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.9: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.14, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq 312(%rsp), %rsi
shrq $10, %rsi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.10: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit17
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.16, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq 368(%rsp), %rsi
shrq $10, %rsi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.11: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit19
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.17, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 320(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.12: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit21
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.13: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.18, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 324(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.14: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit25
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.19, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 336(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.15: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit27
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.20, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 340(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.21, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 344(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.21, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 348(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.22, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.16: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit29
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl $_ZSt5wcout, %edi
movl $.L.str.23, %esi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 352(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.21, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 356(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.21, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movl 360(%rsp), %esi
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movl $.L.str.22, %esi
movq %rax, %rdi
callq _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.17: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit31
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r15, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movq _ZSt5wcout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt5wcout+240(%rax), %rdi
testq %rdi, %rdi
je .LBB1_20
# %bb.18: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB1_7 Depth=1
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movl $_ZSt5wcout, %edi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB1_7
.LBB1_19: # %._crit_edge
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_20:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z13DisplayHeaderv, .Lfunc_end1-_Z13DisplayHeaderv
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sobelPhS_PjS0_PtPi # -- Begin function _Z20__device_stub__sobelPhS_PjS0_PtPi
.p2align 4, 0x90
.type _Z20__device_stub__sobelPhS_PjS0_PtPi,@function
_Z20__device_stub__sobelPhS_PjS0_PtPi: # @_Z20__device_stub__sobelPhS_PjS0_PtPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sobelPhS_PjS0_PtPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z20__device_stub__sobelPhS_PjS0_PtPi, .Lfunc_end2-_Z20__device_stub__sobelPhS_PjS0_PtPi
.cfi_endproc
# -- End function
.globl _Z9write_bmpPKc # -- Begin function _Z9write_bmpPKc
.p2align 4, 0x90
.type _Z9write_bmpPKc,@function
_Z9write_bmpPKc: # @_Z9write_bmpPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $.L.str.24, %esi
callq fopen
movq %rax, fp_t(%rip)
testq %rax, %rax
je .LBB3_1
# %bb.2:
movl width(%rip), %ebx
movl height(%rip), %ecx
movl %ecx, %edx
imull %ebx, %edx
movzwl byte_per_pixel(%rip), %esi
imull %edx, %esi
movl rgb_raw_data_offset(%rip), %r8d
leal (%r8,%rsi), %edx
movb %dl, header+2(%rip)
movb %dh, header+3(%rip)
movl %edx, %esi
shrl $16, %esi
movb %sil, header+4(%rip)
shrl $24, %edx
movb %dl, header+5(%rip)
movb %bl, header+18(%rip)
movb %bh, header+19(%rip)
movl %ebx, %edx
shrl $16, %edx
movb %dl, header+20(%rip)
shrl $24, %ebx
movb %bl, header+21(%rip)
movb %cl, header+22(%rip)
movb %ch, header+23(%rip)
movl %ecx, %edx
shrl $16, %edx
movb %dl, header+24(%rip)
shrl $24, %ecx
movb %cl, header+25(%rip)
movzbl bit_per_pixel(%rip), %ecx
movb %cl, header+28(%rip)
movl $header, %edi
movl $1, %esi
movq %r8, %rdx
movq %rax, %rcx
callq fwrite
movq image_t(%rip), %rdi
movl width(%rip), %eax
movl height(%rip), %ecx
imulq %rax, %rcx
movzwl byte_per_pixel(%rip), %edx
imulq %rcx, %rdx
movq fp_t(%rip), %rcx
movl $1, %esi
callq fwrite
movq fp_s(%rip), %rdi
callq fclose
movq fp_t(%rip), %rdi
callq fclose
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9write_bmpPKc, .Lfunc_end3-_Z9write_bmpPKc
.cfi_endproc
# -- End function
.globl _Z11init_devicev # -- Begin function _Z11init_devicev
.p2align 4, 0x90
.type _Z11init_devicev,@function
_Z11init_devicev: # @_Z11init_devicev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11init_devicev, .Lfunc_end4-_Z11init_devicev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $1, %edi
callq hipSetDevice
callq _Z13DisplayHeaderv
movl $.L.str.26, %edi
cmpl $2, %ebp
jl .LBB5_2
# %bb.1:
movq 8(%rbx), %rdi
.LBB5_2:
callq _Z8read_bmpPKc
movq $0, 8(%rsp)
movq $0, (%rsp)
movq $0, 16(%rsp)
leaq 208(%rsp), %rdi
movl $_mask, %esi
movl $200, %edx
callq memcpy@PLT
movl width(%rip), %eax
movl height(%rip), %ecx
imulq %rax, %rcx
movzwl byte_per_pixel(%rip), %esi
imulq %rcx, %rsi
movq %rsp, %rdi
callq hipMalloc
movl width(%rip), %eax
movl height(%rip), %ecx
imulq %rax, %rcx
movzwl byte_per_pixel(%rip), %esi
imulq %rcx, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $1, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $2, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200, %esi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB5_3
# %bb.5:
movq 16(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $200, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $width, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $height, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq image_t(%rip), %rsi
movl height(%rip), %eax
imull width(%rip), %eax
movzwl byte_per_pixel(%rip), %edx
imull %eax, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq image_s(%rip), %rsi
movl height(%rip), %eax
imull width(%rip), %eax
movzwl byte_per_pixel(%rip), %edx
imull %eax, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $bit_per_pixel, %esi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $byte_per_pixel, %esi
movl $2, %edx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB5_6
# %bb.7:
movl width(%rip), %eax
movl %eax, %ebx
shrl $10, %ebx
andl $1023, %eax # imm = 0x3FF
cmpl $1, %eax
sbbl $-1, %ebx
movl $_ZSt5wcout, %edi
movl %ebx, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rdi
testq %rdi, %rdi
je .LBB5_14
# %bb.8: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r14, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
imull height(%rip), %ebx
movl $_ZSt5wcout, %edi
movl %ebx, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rdi
testq %rdi, %rdi
je .LBB5_14
# %bb.9: # %_ZSt4endlIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_.exit38
movq (%rdi), %rax
movl $10, %esi
callq *80(%rax)
movq %r14, %rdi
movl %eax, %esi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw
movq %rax, %rdi
callq _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv
movl %ebx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $200, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_11
# %bb.10:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movq 16(%rsp), %r8
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdi, 120(%rsp)
movq %r8, 112(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5sobelPhS_PjS0_PtPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_11:
movq image_t(%rip), %rdi
movq (%rsp), %rsi
movl width(%rip), %eax
movl height(%rip), %ecx
imulq %rax, %rcx
movzwl byte_per_pixel(%rip), %edx
imulq %rcx, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB5_12
# %bb.13:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.30, %edi
callq _Z9write_bmpPKc
movq image_s(%rip), %rdi
callq hipHostFree
movq image_t(%rip), %rdi
callq hipHostFree
xorl %eax, %eax
addq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_14:
.cfi_def_cfa_offset 448
callq _ZSt16__throw_bad_castv
.LBB5_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.27, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $366, %r9d # imm = 0x16E
jmp .LBB5_4
.LBB5_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.28, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $382, %r9d # imm = 0x17E
jmp .LBB5_4
.LBB5_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.29, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $401, %r9d # imm = 0x191
.LBB5_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sobelPhS_PjS0_PtPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type image_s,@object # @image_s
.bss
.globl image_s
.p2align 3, 0x0
image_s:
.quad 0
.size image_s, 8
.type image_t,@object # @image_t
.globl image_t
.p2align 3, 0x0
image_t:
.quad 0
.size image_t, 8
.type fp_s,@object # @fp_s
.globl fp_s
.p2align 3, 0x0
fp_s:
.quad 0
.size fp_s, 8
.type fp_t,@object # @fp_t
.globl fp_t
.p2align 3, 0x0
fp_t:
.quad 0
.size fp_t, 8
.type width,@object # @width
.globl width
.p2align 2, 0x0
width:
.long 0 # 0x0
.size width, 4
.type height,@object # @height
.globl height
.p2align 2, 0x0
height:
.long 0 # 0x0
.size height, 4
.type rgb_raw_data_offset,@object # @rgb_raw_data_offset
.globl rgb_raw_data_offset
.p2align 2, 0x0
rgb_raw_data_offset:
.long 0 # 0x0
.size rgb_raw_data_offset, 4
.type bit_per_pixel,@object # @bit_per_pixel
.globl bit_per_pixel
bit_per_pixel:
.byte 0 # 0x0
.size bit_per_pixel, 1
.type byte_per_pixel,@object # @byte_per_pixel
.globl byte_per_pixel
.p2align 1, 0x0
byte_per_pixel:
.short 0 # 0x0
.size byte_per_pixel, 2
.type header,@object # @header
.data
.globl header
.p2align 4, 0x0
header:
.ascii "BM\000\000\000\000\000\000\000\0006\000\000\000(\000\000\000\000\000\000\000\000\000\000\000\001\000\030"
.zero 25
.size header, 54
.type _mask,@object # @_mask
.globl _mask
.p2align 4, 0x0
_mask:
.long 4294967295 # 0xffffffff
.long 4294967292 # 0xfffffffc
.long 4294967290 # 0xfffffffa
.long 4294967292 # 0xfffffffc
.long 4294967295 # 0xffffffff
.long 4294967294 # 0xfffffffe
.long 4294967288 # 0xfffffff8
.long 4294967284 # 0xfffffff4
.long 4294967288 # 0xfffffff8
.long 4294967294 # 0xfffffffe
.zero 20
.long 2 # 0x2
.long 8 # 0x8
.long 12 # 0xc
.long 8 # 0x8
.long 2 # 0x2
.long 1 # 0x1
.long 4 # 0x4
.long 6 # 0x6
.long 4 # 0x4
.long 1 # 0x1
.long 4294967295 # 0xffffffff
.long 4294967294 # 0xfffffffe
.long 0 # 0x0
.long 2 # 0x2
.long 1 # 0x1
.long 4294967292 # 0xfffffffc
.long 4294967288 # 0xfffffff8
.long 0 # 0x0
.long 8 # 0x8
.long 4 # 0x4
.long 4294967290 # 0xfffffffa
.long 4294967284 # 0xfffffff4
.long 0 # 0x0
.long 12 # 0xc
.long 6 # 0x6
.long 4294967292 # 0xfffffffc
.long 4294967288 # 0xfffffff8
.long 0 # 0x0
.long 8 # 0x8
.long 4 # 0x4
.long 4294967295 # 0xffffffff
.long 4294967294 # 0xfffffffe
.long 0 # 0x0
.long 2 # 0x2
.long 1 # 0x1
.size _mask, 200
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cuda_malloc_images_s error"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ChihMin/Parallel_Programming/master/cuda_prac/sobel.hip"
.size .L.str.4, 113
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "cuda_malloc_images_t error"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "NBody.GPU"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "========="
.size .L.str.8, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CUDA Devices: "
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz ": "
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "."
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Global memory: "
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "mb"
.size .L.str.13, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Shared memory: "
.size .L.str.14, 20
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "kb"
.size .L.str.15, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Constant memory: "
.size .L.str.16, 20
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Block registers: "
.size .L.str.17, 20
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " Warp size: "
.size .L.str.18, 22
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " Threads per block: "
.size .L.str.19, 22
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Max block dimensions: [ "
.size .L.str.20, 27
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz ", "
.size .L.str.21, 3
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " ]"
.size .L.str.22, 3
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " Max grid dimensions: [ "
.size .L.str.23, 27
.type _Z5sobelPhS_PjS0_PtPi,@object # @_Z5sobelPhS_PjS0_PtPi
.section .rodata,"a",@progbits
.globl _Z5sobelPhS_PjS0_PtPi
.p2align 3, 0x0
_Z5sobelPhS_PjS0_PtPi:
.quad _Z20__device_stub__sobelPhS_PjS0_PtPi
.size _Z5sobelPhS_PjS0_PtPi, 8
.type .L.str.24,@object # @.str.24
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.24:
.asciz "wb"
.size .L.str.24, 3
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "candy.bmp"
.size .L.str.26, 10
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "cudamalloc fail"
.size .L.str.27, 16
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "cuda memcpy fail"
.size .L.str.28, 17
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "cuda memcpy back to host fail"
.size .L.str.29, 30
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "out.bmp"
.size .L.str.30, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sobelPhS_PjS0_PtPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "fopen fp_s error"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "fopen fname_t error"
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sobelPhS_PjS0_PtPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym image_s
.addrsig_sym image_t
.addrsig_sym width
.addrsig_sym height
.addrsig_sym rgb_raw_data_offset
.addrsig_sym bit_per_pixel
.addrsig_sym byte_per_pixel
.addrsig_sym header
.addrsig_sym _ZSt5wcout
.addrsig_sym _Z5sobelPhS_PjS0_PtPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
cudaGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
cudaDeviceProp device_Property;
cudaGetDevice(&device);
cudaGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
cudaDriverGetVersion(&driver_Version);
cudaRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
cudaGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
cudaDeviceProp device_Property;
cudaGetDevice(&device);
cudaGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
cudaDriverGetVersion(&driver_Version);
cudaRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} | .file "tmpxft_000b57ce_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC1:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nDevice %d:\"%s\"\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.align 8
.LC5:
.string "Total amount of global memory:%.0f Mbytes (%1lu bytes)\n"
.section .rodata.str1.1
.LC6:
.string "(%2d) Multiprocessors"
.section .rodata.str1.8
.align 8
.LC9:
.string "GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n"
.align 8
.LC10:
.string "Maximum number of threads per multiprocessor:%d\n"
.align 8
.LC11:
.string "Maximum number of threads per block:%d\n"
.align 8
.LC12:
.string "Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n"
.align 8
.LC13:
.string "Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
movl (%rsp), %edx
testl %edx, %edx
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl 4(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %ecx
movslq %eax, %r8
imulq $1374389535, %r8, %rdx
sarq $37, %rdx
movl %eax, %edi
sarl $31, %edi
subl %edi, %edx
imull $100, %edx, %edx
subl %edx, %eax
movslq %eax, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %eax
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %ecx, %rdx
imulq $1374389535, %rdx, %rsi
sarq $37, %rsi
movl %ecx, %r10d
sarl $31, %r10d
subl %r10d, %esi
imull $100, %esi, %esi
subl %esi, %ecx
movslq %ecx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %ecx
subl %ecx, %esi
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %eax, %r9d
subl %edi, %r8d
movl %esi, %ecx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L7:
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
movaps %xmm0, %xmm1
mulss .LC7(%rip), %xmm1
mulss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L6:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L7
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 897581056
.align 4
.LC7:
.long 897988541
.align 4
.LC8:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
cudaGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
cudaDeviceProp device_Property;
cudaGetDevice(&device);
cudaGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
cudaDriverGetVersion(&driver_Version);
cudaRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
hipGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
hipDeviceProp_t device_Property;
hipGetDevice(&device);
hipGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
hipDriverGetVersion(&driver_Version);
hipRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
hipGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
hipDeviceProp_t device_Property;
hipGetDevice(&device);
hipGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
hipDriverGetVersion(&driver_Version);
hipRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <memory>
/*ÔÚCUDA³ÌÐòÖлñÈ¡GPUÉ豸ÊôÐÔ*/
int main(void) {
int device_count = 0;
hipGetDeviceCount(&device_count);
//¸Ãº¯Êý·µ»ØÖ§³ÖCUDAµÄGPUÉ豸µÄ¸öÊý
if (device_count ==0)
{
printf("There are no available device(s) that support CUDA\n");
}
else
{
printf("Detected %d CUDA Capable device(s)\n", device_count);
}
//ͨÓÃÉ豸ÐÅÏ¢
/*
cudaDeviceProp½á¹¹ÌåÌṩÁË¿ÉÒÔÓÃÀ´Ê¶±ðÉ豸ÒÔ¼°È·¶¨Ê¹Óõİ汾ÐÅÏ¢µÄÊôÐÔ¡£ËüÌṩµÄnameÊôÐÔ£¬¿ÉÒÔÒÔ×Ö·û´®
µÄÐÎʽ·µ»ØÉ豸µÄÃû³Æ¡£»¹¿ÉÒÔͨ¹ý²éѯcudaDriverGetVersionºÍcudaRuntimeGetVersionÊôÐÔ»ñµÃÉ豸ʹÓõÄCUDA Driver
ºÍÔËÐÐʱÒýÇæµÄ°æ±¾¡£Èç¹ûÓжà¸öÉ豸£¬²¢Ï£ÍûʹÓÃÆäÖеľßÓÐ×î¶àÁ÷´¦ÀíÆ÷µÄÄǸö£¬Ôò¿ÉÒÔͨ¹ýmultiProcessorCount
ÊôÐÔÀ´Åжϡ£¸ÃÊôÐÔ·µ»ØÉ豸ÉϵÄÁ÷¶à´¦ÀíÆ÷¸öÊý¡£»¹¿ÉÒÔͨ¹ýʹÓÃclockRateÊôÐÔ»ñÈ¡GPUµÄʱÖÓËÙÂÊ£¬ÒÔKHz·µ»ØʱÖÓ
ËÙÂÊ¡£
*/
int device;
hipDeviceProp_t device_Property;
hipGetDevice(&device);
hipGetDeviceProperties(&device_Property, device);
printf("\nDevice %d:\"%s\"\n", device, device_Property.name);
int driver_Version;
int runtime_Version;
hipDriverGetVersion(&driver_Version);
hipRuntimeGetVersion(&runtime_Version);
printf("CUDA Driver Version / Runtime Version %d.%d / %d.%d\n", driver_Version / 1000, (driver_Version % 100) / 10, runtime_Version / 1000, (runtime_Version % 100) / 10);
printf("Total amount of global memory:%.0f Mbytes (%1lu bytes)\n", (float)device_Property.totalGlobalMem / 1048576.0f, (unsigned long long)device_Property.totalGlobalMem);
printf("(%2d) Multiprocessors", device_Property.multiProcessorCount);
printf("GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n", device_Property.clockRate * 1e-3f, device_Property.clockRate * 1e-6f);
/*
¿éºÍÏ̶߳¼¿ÉÒÔʱ¶àάµÄ£¬dim3ÀàÐÍ¡£Òò´Ë£¬×îºÃÖªµÀÿ¸öά¶ÈÖпÉÒÔ²¢ÐÐÆô¶¯¶àÉÙÏ̺߳Ϳ顣¶ÔÓÚÿ¸ö¶à´¦ÀíÆ÷µÄ
Ïß³ÌÊýÁ¿ºÍÿ¸ö¿éµÄÏß³ÌÊýÁ¿Ò²ÓÐÏÞÖÆ¡£Õâ¸öÊý×Ö¿ÉÒÔͨ¹ýmaxThreadsPerMultiProcessorºÍmaxThreadsPerBlockÕÒµ½¡£
Èç¹ûÿ¸ö¿éÖÐÆô¶¯µÄÏß³ÌÊýÁ¿³¬¹ýÿ¸ö¿éÖпÉÄܵÄ×î´óÏß³ÌÊýÁ¿£¬Ôò³ÌÐò¿ÉÄܱÀÀ£¡£
¿ÉÒÔͨ¹ýmaxThreadsDimÀ´È·¶¨¿éÖÐÿ¸öά¶ÈÉϵÄ×î´óÏß³ÌÊýÁ¿¡£Í¬Ñù£¬Ã¿¸öά¶ÈÖÐÿ¸öÍø¸ñµÄ×î´ó¿é¿ÉÒÔͨ¹ý
maxGridSizeÀ´±êʶ¡£ËüÃǶ¼·µ»ØÒ»¸ö¾ßÓÐÈý¸öÖµµÄÊý×飬·Ö±ðÏÔʾx£¬y£¬zά¶ÈÖеÄ×î´óÖµ¡£
*/
printf("Maximum number of threads per multiprocessor:%d\n", device_Property.maxThreadsPerMultiProcessor);
printf("Maximum number of threads per block:%d\n", device_Property.maxThreadsPerBlock);
printf("Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n", device_Property.maxThreadsDim[0],
device_Property.maxThreadsDim[1],
device_Property.maxThreadsDim[2]);
printf("Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n", device_Property.maxGridSize[0],
device_Property.maxGridSize[1],
device_Property.maxGridSize[2]);
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI0_1:
.long 0x3a83126f # float 0.00100000005
.LCPI0_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
testl %esi, %esi
je .LBB0_1
# %bb.2:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_3
.LBB0_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_3:
movq %rsp, %rdi
callq hipGetDevice
movl (%rsp), %esi
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
movl $.L.str.2, %edi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rdi
callq hipDriverGetVersion
leaq 8(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 8(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
testq %rsi, %rsi
js .LBB0_4
# %bb.5:
cvtsi2ss %rsi, %xmm0
jmp .LBB0_6
.LBB0_4:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB0_6:
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl 404(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm1
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulss .LCPI0_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movb $2, %al
callq printf
movl 640(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nDevice %d:\"%s\"\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total amount of global memory:%.0f Mbytes (%1lu bytes)\n"
.size .L.str.4, 56
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "(%2d) Multiprocessors"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n"
.size .L.str.6, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum number of threads per multiprocessor:%d\n"
.size .L.str.7, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum number of threads per block:%d\n"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n"
.size .L.str.9, 57
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n"
.size .L.str.10, 54
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b57ce_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There are no available device(s) that support CUDA\n"
.align 8
.LC1:
.string "Detected %d CUDA Capable device(s)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nDevice %d:\"%s\"\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.align 8
.LC5:
.string "Total amount of global memory:%.0f Mbytes (%1lu bytes)\n"
.section .rodata.str1.1
.LC6:
.string "(%2d) Multiprocessors"
.section .rodata.str1.8
.align 8
.LC9:
.string "GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n"
.align 8
.LC10:
.string "Maximum number of threads per multiprocessor:%d\n"
.align 8
.LC11:
.string "Maximum number of threads per block:%d\n"
.align 8
.LC12:
.string "Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n"
.align 8
.LC13:
.string "Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
movl (%rsp), %edx
testl %edx, %edx
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl 4(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %ecx
movslq %eax, %r8
imulq $1374389535, %r8, %rdx
sarq $37, %rdx
movl %eax, %edi
sarl $31, %edi
subl %edi, %edx
imull $100, %edx, %edx
subl %edx, %eax
movslq %eax, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %eax
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %ecx, %rdx
imulq $1374389535, %rdx, %rsi
sarq $37, %rsi
movl %ecx, %r10d
sarl $31, %r10d
subl %r10d, %esi
imull $100, %esi, %esi
subl %esi, %ecx
movslq %ecx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %ecx
subl %ecx, %esi
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %eax, %r9d
subl %edi, %r8d
movl %esi, %ecx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L7:
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
movaps %xmm0, %xmm1
mulss .LC7(%rip), %xmm1
mulss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L6:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L7
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 897581056
.align 4
.LC7:
.long 897988541
.align 4
.LC8:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI0_1:
.long 0x3a83126f # float 0.00100000005
.LCPI0_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
testl %esi, %esi
je .LBB0_1
# %bb.2:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_3
.LBB0_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_3:
movq %rsp, %rdi
callq hipGetDevice
movl (%rsp), %esi
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
movl $.L.str.2, %edi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rdi
callq hipDriverGetVersion
leaq 8(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 8(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
testq %rsi, %rsi
js .LBB0_4
# %bb.5:
cvtsi2ss %rsi, %xmm0
jmp .LBB0_6
.LBB0_4:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB0_6:
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl 404(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm1
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulss .LCPI0_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movb $2, %al
callq printf
movl 640(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Detected %d CUDA Capable device(s)\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nDevice %d:\"%s\"\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA Driver Version / Runtime Version %d.%d / %d.%d\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total amount of global memory:%.0f Mbytes (%1lu bytes)\n"
.size .L.str.4, 56
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "(%2d) Multiprocessors"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Max Clock rate:%.0f MHz (%0.2f GHz)\n"
.size .L.str.6, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum number of threads per multiprocessor:%d\n"
.size .L.str.7, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum number of threads per block:%d\n"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Max dimension size of a thread block (x,y,z):(%d,%d,%d)\n"
.size .L.str.9, 57
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max dimension size of a grid size (x,y,z):(%d,%d,%d)\n"
.size .L.str.10, 54
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no available device(s) that support CUDA"
.size .Lstr, 51
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
cudaDeviceProp prop;
cudaGetDeviceCount(&count);
for (i = 0; i < count; i++) {
cudaGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
cudaDeviceProp prop;
cudaGetDeviceCount(&count);
for (i = 0; i < count; i++) {
cudaGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} | .file "tmpxft_0014f4ae_00000000-6_intro7.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
cudaDeviceProp prop;
cudaGetDeviceCount(&count);
for (i = 0; i < count; i++) {
cudaGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
hipDeviceProp_t prop;
hipGetDeviceCount(&count);
for (i = 0; i < count; i++) {
hipGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
hipDeviceProp_t prop;
hipGetDeviceCount(&count);
for (i = 0; i < count; i++) {
hipGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int i, count;
hipDeviceProp_t prop;
hipGetDeviceCount(&count);
for (i = 0; i < count; i++) {
hipGetDeviceProperties(&prop, i);
printf("Device name: %s\n", prop.name);
}
return 0;
} | .text
.file "intro7.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f4ae_00000000-6_intro7.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intro7.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DIV_UP(x,y) (1 + ((x - 1) / y))
__global__ void sum_kernel(int n, float const*const ptr, float *const out) {
extern __shared__ float sum[];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0){
sum[0] = 0;
}
__syncthreads();
if(i < n){
atomicAdd(sum, ptr[i]);
}
__syncthreads();
if (threadIdx.x == 0){
printf("Block %d, sum = %f\n", blockIdx.x, sum[0]);
}
__syncthreads();
if (threadIdx.x == 0){
atomicAdd(out, sum[0]);
}
}
int main(int argc, char** argv) {
int n = argc == 2 ? atoi(argv[1]) : 10000;
float *const ptr = (float*) malloc(sizeof(float) * n);
float* out = (float*) malloc(sizeof(float));
*out = 0;
float *d_ptr, *d_out;
cudaMalloc((void**)&d_ptr, sizeof(float) * n);
cudaMalloc((void**)&d_out, sizeof(float));
for (int i = 0; i < n; i++){
ptr[i] = 1.0 + (2.6458 / (float)((i+20)%1024+1));
}
float check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
for (int i = 0; i < n; i++) ptr[i] /= check;
cudaMemcpy(d_ptr, ptr, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, sizeof(float), cudaMemcpyHostToDevice);
sum_kernel<<<DIV_UP(n, 1024), 1024, 100*sizeof(float)>>>(n, d_ptr, d_out);
cudaMemcpy(out, d_out, sizeof(float), cudaMemcpyDeviceToHost);
check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
printf("CPU : %f\n", check);
printf("GPU : %f\n", *out);
printf("DIFF: %.15f\n", check-*out);
return 0;
} | code for sm_80
Function : _Z10sum_kerneliPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x001fe20003f25270 */
/*0070*/ IMAD R2, R10, c[0x0][0x0], R17 ; /* 0x000000000a027a24 */
/* 0x002fc600078e0211 */
/*0080*/ P2R R0, PR, RZ, 0x2 ; /* 0x00000002ff007803 */
/* 0x000fe40000000000 */
/*0090*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fce0003f06270 */
/*00a0*/ @!P1 STS [RZ], RZ ; /* 0x000000ffff009388 */
/* 0x000fe80000000800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @P0 BRA 0x150 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000164000c1e1900 */
/*0100*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e640000000800 */
/*0110*/ FADD R5, R2, R4 ; /* 0x0000000402057221 */
/* 0x022fcc0000000000 */
/*0120*/ ATOMS.CAST.SPIN R5, [RZ], R4, R5 ; /* 0x00000004ff05738d */
/* 0x000e640001800005 */
/*0130*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x002fda0003f02070 */
/*0140*/ @!P0 BRA 0x100 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0180*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0190*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fcc00000e06ff */
/*01a0*/ @P1 BRA 0x2b0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*01b0*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e620000000800 */
/*01c0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*01e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0005e20000100800 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0200*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x001e220000000a00 */
/*0210*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x002e640000201800 */
/*0220*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0025e40000100a00 */
/*0230*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x005fe20000000000 */
/*0240*/ MOV R11, 0x2b0 ; /* 0x000002b0000b7802 */
/* 0x000fc40000000f00 */
/*0250*/ MOV R20, 0x230 ; /* 0x0000023000147802 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0270*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0280*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0290*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*02a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*02b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.NE.AND P6, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fda0003fc5270 */
/*02e0*/ @P6 EXIT ; /* 0x000000000000694d */
/* 0x000fea0003800000 */
/*02f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x001fca00078e00ff */
/*0320*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e7a4 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DIV_UP(x,y) (1 + ((x - 1) / y))
__global__ void sum_kernel(int n, float const*const ptr, float *const out) {
extern __shared__ float sum[];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0){
sum[0] = 0;
}
__syncthreads();
if(i < n){
atomicAdd(sum, ptr[i]);
}
__syncthreads();
if (threadIdx.x == 0){
printf("Block %d, sum = %f\n", blockIdx.x, sum[0]);
}
__syncthreads();
if (threadIdx.x == 0){
atomicAdd(out, sum[0]);
}
}
int main(int argc, char** argv) {
int n = argc == 2 ? atoi(argv[1]) : 10000;
float *const ptr = (float*) malloc(sizeof(float) * n);
float* out = (float*) malloc(sizeof(float));
*out = 0;
float *d_ptr, *d_out;
cudaMalloc((void**)&d_ptr, sizeof(float) * n);
cudaMalloc((void**)&d_out, sizeof(float));
for (int i = 0; i < n; i++){
ptr[i] = 1.0 + (2.6458 / (float)((i+20)%1024+1));
}
float check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
for (int i = 0; i < n; i++) ptr[i] /= check;
cudaMemcpy(d_ptr, ptr, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, sizeof(float), cudaMemcpyHostToDevice);
sum_kernel<<<DIV_UP(n, 1024), 1024, 100*sizeof(float)>>>(n, d_ptr, d_out);
cudaMemcpy(out, d_out, sizeof(float), cudaMemcpyDeviceToHost);
check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
printf("CPU : %f\n", check);
printf("GPU : %f\n", *out);
printf("DIFF: %.15f\n", check-*out);
return 0;
} | .file "tmpxft_000ad66d_00000000-6_test_cuatomic_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
.type _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf, @function
_Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kerneliPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf, .-_Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
.globl _Z10sum_kerneliPKfPf
.type _Z10sum_kerneliPKfPf, @function
_Z10sum_kerneliPKfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10sum_kerneliPKfPf, .-_Z10sum_kerneliPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "CPU : %f\n"
.LC4:
.string "GPU : %f\n"
.LC5:
.string "DIFF: %.15f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L29
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0x00000000, (%rax)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $10000, %r14d
movl $40000, %ebp
movl $10000, %r12d
.L20:
movl $0, %edx
movsd .LC1(%rip), %xmm3
movsd .LC2(%rip), %xmm2
.L14:
leal 20(%rdx), %eax
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movapd %xmm3, %xmm0
divsd %xmm1, %xmm0
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rdx,4)
addq $1, %rdx
cmpq %rdx, %r12
jne .L14
movq %rbx, %rax
leaq 0(%rbp,%rbx), %rcx
movq %rbx, %rdx
pxor %xmm1, %xmm1
.L15:
addss (%rdx), %xmm1
addq $4, %rdx
cmpq %rcx, %rdx
jne .L15
.L16:
movss (%rax), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L16
.L13:
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $400, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L22
movq %rbx, %rax
addq %rbx, %rbp
movl $0x00000000, 12(%rsp)
.L19:
movss 12(%rsp), %xmm4
addss (%rax), %xmm4
movss %xmm4, 12(%rsp)
addq $4, %rax
cmpq %rbp, %rax
jne .L19
.L18:
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
subss 0(%r13), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r14d
movslq %eax, %r12
leaq 0(,%r12,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0x00000000, (%rax)
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L13
jmp .L20
.L30:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r14d, %edi
call _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
jmp .L17
.L22:
movl $0x00000000, 12(%rsp)
jmp .L18
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10sum_kerneliPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kerneliPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 817761773
.long 1074080409
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DIV_UP(x,y) (1 + ((x - 1) / y))
__global__ void sum_kernel(int n, float const*const ptr, float *const out) {
extern __shared__ float sum[];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0){
sum[0] = 0;
}
__syncthreads();
if(i < n){
atomicAdd(sum, ptr[i]);
}
__syncthreads();
if (threadIdx.x == 0){
printf("Block %d, sum = %f\n", blockIdx.x, sum[0]);
}
__syncthreads();
if (threadIdx.x == 0){
atomicAdd(out, sum[0]);
}
}
int main(int argc, char** argv) {
int n = argc == 2 ? atoi(argv[1]) : 10000;
float *const ptr = (float*) malloc(sizeof(float) * n);
float* out = (float*) malloc(sizeof(float));
*out = 0;
float *d_ptr, *d_out;
cudaMalloc((void**)&d_ptr, sizeof(float) * n);
cudaMalloc((void**)&d_out, sizeof(float));
for (int i = 0; i < n; i++){
ptr[i] = 1.0 + (2.6458 / (float)((i+20)%1024+1));
}
float check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
for (int i = 0; i < n; i++) ptr[i] /= check;
cudaMemcpy(d_ptr, ptr, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, sizeof(float), cudaMemcpyHostToDevice);
sum_kernel<<<DIV_UP(n, 1024), 1024, 100*sizeof(float)>>>(n, d_ptr, d_out);
cudaMemcpy(out, d_out, sizeof(float), cudaMemcpyDeviceToHost);
check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
printf("CPU : %f\n", check);
printf("GPU : %f\n", *out);
printf("DIFF: %.15f\n", check-*out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DIV_UP(x,y) (1 + ((x - 1) / y))
__global__ void sum_kernel(int n, float const*const ptr, float *const out) {
extern __shared__ float sum[];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0){
sum[0] = 0;
}
__syncthreads();
if(i < n){
atomicAdd(sum, ptr[i]);
}
__syncthreads();
if (threadIdx.x == 0){
printf("Block %d, sum = %f\n", blockIdx.x, sum[0]);
}
__syncthreads();
if (threadIdx.x == 0){
atomicAdd(out, sum[0]);
}
}
int main(int argc, char** argv) {
int n = argc == 2 ? atoi(argv[1]) : 10000;
float *const ptr = (float*) malloc(sizeof(float) * n);
float* out = (float*) malloc(sizeof(float));
*out = 0;
float *d_ptr, *d_out;
hipMalloc((void**)&d_ptr, sizeof(float) * n);
hipMalloc((void**)&d_out, sizeof(float));
for (int i = 0; i < n; i++){
ptr[i] = 1.0 + (2.6458 / (float)((i+20)%1024+1));
}
float check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
for (int i = 0; i < n; i++) ptr[i] /= check;
hipMemcpy(d_ptr, ptr, sizeof(float) * n, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, sizeof(float), hipMemcpyHostToDevice);
sum_kernel<<<DIV_UP(n, 1024), 1024, 100*sizeof(float)>>>(n, d_ptr, d_out);
hipMemcpy(out, d_out, sizeof(float), hipMemcpyDeviceToHost);
check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
printf("CPU : %f\n", check);
printf("GPU : %f\n", *out);
printf("DIFF: %.15f\n", check-*out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DIV_UP(x,y) (1 + ((x - 1) / y))
__global__ void sum_kernel(int n, float const*const ptr, float *const out) {
extern __shared__ float sum[];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (threadIdx.x == 0){
sum[0] = 0;
}
__syncthreads();
if(i < n){
atomicAdd(sum, ptr[i]);
}
__syncthreads();
if (threadIdx.x == 0){
printf("Block %d, sum = %f\n", blockIdx.x, sum[0]);
}
__syncthreads();
if (threadIdx.x == 0){
atomicAdd(out, sum[0]);
}
}
int main(int argc, char** argv) {
int n = argc == 2 ? atoi(argv[1]) : 10000;
float *const ptr = (float*) malloc(sizeof(float) * n);
float* out = (float*) malloc(sizeof(float));
*out = 0;
float *d_ptr, *d_out;
hipMalloc((void**)&d_ptr, sizeof(float) * n);
hipMalloc((void**)&d_out, sizeof(float));
for (int i = 0; i < n; i++){
ptr[i] = 1.0 + (2.6458 / (float)((i+20)%1024+1));
}
float check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
for (int i = 0; i < n; i++) ptr[i] /= check;
hipMemcpy(d_ptr, ptr, sizeof(float) * n, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, sizeof(float), hipMemcpyHostToDevice);
sum_kernel<<<DIV_UP(n, 1024), 1024, 100*sizeof(float)>>>(n, d_ptr, d_out);
hipMemcpy(out, d_out, sizeof(float), hipMemcpyDeviceToHost);
check = 0.0;
for (int i = 0; i < n; i++) check += ptr[i];
printf("CPU : %f\n", check);
printf("GPU : %f\n", *out);
printf("DIFF: %.15f\n", check-*out);
return 0;
} | .text
.file "test_cuatomic_add.hip"
.globl _Z25__device_stub__sum_kerneliPKfPf # -- Begin function _Z25__device_stub__sum_kerneliPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__sum_kerneliPKfPf,@function
_Z25__device_stub__sum_kerneliPKfPf: # @_Z25__device_stub__sum_kerneliPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kerneliPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kerneliPKfPf, .Lfunc_end0-_Z25__device_stub__sum_kerneliPKfPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x40052a9930be0ded # double 2.6457999999999999
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $10000, %r15d # imm = 0x2710
cmpl $2, %edi
jne .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB1_2:
movslq %r15d, %rbp
leaq (,%rbp,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $0, (%rax)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %r15d, %r13d
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal 20(%rax), %ecx
andl $1023, %ecx # imm = 0x3FF
incl %ecx
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
movapd %xmm0, %xmm3
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%r14,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_4
.LBB1_5: # %.preheader48
xorpd %xmm0, %xmm0
testl %r15d, %r15d
jle .LBB1_6
# %bb.15: # %.lr.ph52.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_16: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq %rax, %r13
jne .LBB1_16
.LBB1_6: # %.preheader
testl %r15d, %r15d
jle .LBB1_9
# %bb.7: # %.lr.ph54.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph54
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_8
.LBB1_9: # %._crit_edge
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leal -1(%r15), %eax
leal 1022(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $400, %r8d # imm = 0x190
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl %r15d, 20(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10sum_kerneliPKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
testl %r15d, %r15d
jle .LBB1_14
# %bb.12: # %.lr.ph58.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq %rax, %r13
jne .LBB1_13
.LBB1_14: # %._crit_edge59
movss %xmm0, 16(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
subss (%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kerneliPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kerneliPKfPf,@object # @_Z10sum_kerneliPKfPf
.section .rodata,"a",@progbits
.globl _Z10sum_kerneliPKfPf
.p2align 3, 0x0
_Z10sum_kerneliPKfPf:
.quad _Z25__device_stub__sum_kerneliPKfPf
.size _Z10sum_kerneliPKfPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU : %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU : %f\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "DIFF: %.15f\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10sum_kerneliPKfPf"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kerneliPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kerneliPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ad66d_00000000-6_test_cuatomic_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
.type _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf, @function
_Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kerneliPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf, .-_Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
.globl _Z10sum_kerneliPKfPf
.type _Z10sum_kerneliPKfPf, @function
_Z10sum_kerneliPKfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10sum_kerneliPKfPf, .-_Z10sum_kerneliPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "CPU : %f\n"
.LC4:
.string "GPU : %f\n"
.LC5:
.string "DIFF: %.15f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L29
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0x00000000, (%rax)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $10000, %r14d
movl $40000, %ebp
movl $10000, %r12d
.L20:
movl $0, %edx
movsd .LC1(%rip), %xmm3
movsd .LC2(%rip), %xmm2
.L14:
leal 20(%rdx), %eax
movl %eax, %ecx
sarl $31, %ecx
shrl $22, %ecx
addl %ecx, %eax
andl $1023, %eax
subl %ecx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movapd %xmm3, %xmm0
divsd %xmm1, %xmm0
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rdx,4)
addq $1, %rdx
cmpq %rdx, %r12
jne .L14
movq %rbx, %rax
leaq 0(%rbp,%rbx), %rcx
movq %rbx, %rdx
pxor %xmm1, %xmm1
.L15:
addss (%rdx), %xmm1
addq $4, %rdx
cmpq %rcx, %rdx
jne .L15
.L16:
movss (%rax), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L16
.L13:
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $400, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L22
movq %rbx, %rax
addq %rbx, %rbp
movl $0x00000000, 12(%rsp)
.L19:
movss 12(%rsp), %xmm4
addss (%rax), %xmm4
movss %xmm4, 12(%rsp)
addq $4, %rax
cmpq %rbp, %rax
jne .L19
.L18:
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
subss 0(%r13), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r14d
movslq %eax, %r12
leaq 0(,%r12,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0x00000000, (%rax)
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L13
jmp .L20
.L30:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r14d, %edi
call _Z34__device_stub__Z10sum_kerneliPKfPfiPKfPf
jmp .L17
.L22:
movl $0x00000000, 12(%rsp)
jmp .L18
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10sum_kerneliPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kerneliPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 817761773
.long 1074080409
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_cuatomic_add.hip"
.globl _Z25__device_stub__sum_kerneliPKfPf # -- Begin function _Z25__device_stub__sum_kerneliPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__sum_kerneliPKfPf,@function
_Z25__device_stub__sum_kerneliPKfPf: # @_Z25__device_stub__sum_kerneliPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kerneliPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kerneliPKfPf, .Lfunc_end0-_Z25__device_stub__sum_kerneliPKfPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x40052a9930be0ded # double 2.6457999999999999
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $10000, %r15d # imm = 0x2710
cmpl $2, %edi
jne .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB1_2:
movslq %r15d, %rbp
leaq (,%rbp,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $0, (%rax)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %r15d, %r13d
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal 20(%rax), %ecx
andl $1023, %ecx # imm = 0x3FF
incl %ecx
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
movapd %xmm0, %xmm3
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%r14,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_4
.LBB1_5: # %.preheader48
xorpd %xmm0, %xmm0
testl %r15d, %r15d
jle .LBB1_6
# %bb.15: # %.lr.ph52.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_16: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq %rax, %r13
jne .LBB1_16
.LBB1_6: # %.preheader
testl %r15d, %r15d
jle .LBB1_9
# %bb.7: # %.lr.ph54.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph54
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_8
.LBB1_9: # %._crit_edge
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leal -1(%r15), %eax
leal 1022(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $400, %r8d # imm = 0x190
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl %r15d, 20(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10sum_kerneliPKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
testl %r15d, %r15d
jle .LBB1_14
# %bb.12: # %.lr.ph58.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq %rax, %r13
jne .LBB1_13
.LBB1_14: # %._crit_edge59
movss %xmm0, 16(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
subss (%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kerneliPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kerneliPKfPf,@object # @_Z10sum_kerneliPKfPf
.section .rodata,"a",@progbits
.globl _Z10sum_kerneliPKfPf
.p2align 3, 0x0
_Z10sum_kerneliPKfPf:
.quad _Z25__device_stub__sum_kerneliPKfPf
.size _Z10sum_kerneliPKfPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU : %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU : %f\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "DIFF: %.15f\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10sum_kerneliPKfPf"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kerneliPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kerneliPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionColumnsKernel_up_smp( float *d_Dst, float *d_Src, int imageW, int imageH, int n_imageH, int pitch, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the upper halo edge
const int baseX = blockIdx.x * COLUMNS_BLOCKDIM_X + threadIdx.x;
const int baseY = (blockIdx.y * COLUMNS_RESULT_STEPS - Halo_steps) * COLUMNS_BLOCKDIM_Y + threadIdx.y;
if (baseX < imageW)
{
d_Src += baseY * pitch + baseX;
d_Dst += 2 * baseY * pitch + baseX;
//Upper halo
//#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y >= 0) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Lower halo + Main data
//#pragma unroll
for (int i = Halo_steps; i < Halo_steps + COLUMNS_RESULT_STEPS + Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y < imageH) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Compute and store results
__syncthreads();
//#pragma unroll
for (int i = Halo_steps; i < COLUMNS_RESULT_STEPS + Halo_steps; ++i)
{
int Pos_y = 2 * baseY + (2 * i) * COLUMNS_BLOCKDIM_Y;
if (Pos_y < n_imageH)
{
float sum_1 = 0.0f, sum_2 = 0.0f;
//#pragma unroll
for (int l = -(filter_Rad / 2); l <= filter_Rad / 2; ++l)
{
int t = 2 * l;
float temp = s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + l];
sum_1 += c_Kernel[filter_Rad + t] * temp * 2.0f;
sum_2 += c_Kernel[filter_Rad + t - 1] * temp * 2.0f;
}
sum_2 += c_Kernel[2 * filter_Rad] * 2.0f * s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + filter_Rad / 2 + 1];
d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch] = sum_1;
if (Pos_y + 1 < n_imageH)d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch + pitch] = sum_2;
}
}
}
} | .file "tmpxft_000f3886_00000000-6_convolutionColumnsKernel_up_smp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
.type _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii, @function
_Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31convolutionColumnsKernel_up_smpPfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii, .-_Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
.globl _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.type _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, @function
_Z31convolutionColumnsKernel_up_smpPfS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, .-_Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31convolutionColumnsKernel_up_smpPfS_iiiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31convolutionColumnsKernel_up_smpPfS_iiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_Kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8c_Kernel
.comm _ZL8c_Kernel,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionColumnsKernel_up_smp( float *d_Dst, float *d_Src, int imageW, int imageH, int n_imageH, int pitch, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the upper halo edge
const int baseX = blockIdx.x * COLUMNS_BLOCKDIM_X + threadIdx.x;
const int baseY = (blockIdx.y * COLUMNS_RESULT_STEPS - Halo_steps) * COLUMNS_BLOCKDIM_Y + threadIdx.y;
if (baseX < imageW)
{
d_Src += baseY * pitch + baseX;
d_Dst += 2 * baseY * pitch + baseX;
//Upper halo
//#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y >= 0) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Lower halo + Main data
//#pragma unroll
for (int i = Halo_steps; i < Halo_steps + COLUMNS_RESULT_STEPS + Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y < imageH) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Compute and store results
__syncthreads();
//#pragma unroll
for (int i = Halo_steps; i < COLUMNS_RESULT_STEPS + Halo_steps; ++i)
{
int Pos_y = 2 * baseY + (2 * i) * COLUMNS_BLOCKDIM_Y;
if (Pos_y < n_imageH)
{
float sum_1 = 0.0f, sum_2 = 0.0f;
//#pragma unroll
for (int l = -(filter_Rad / 2); l <= filter_Rad / 2; ++l)
{
int t = 2 * l;
float temp = s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + l];
sum_1 += c_Kernel[filter_Rad + t] * temp * 2.0f;
sum_2 += c_Kernel[filter_Rad + t - 1] * temp * 2.0f;
}
sum_2 += c_Kernel[2 * filter_Rad] * 2.0f * s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + filter_Rad / 2 + 1];
d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch] = sum_1;
if (Pos_y + 1 < n_imageH)d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch + pitch] = sum_2;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionColumnsKernel_up_smp( float *d_Dst, float *d_Src, int imageW, int imageH, int n_imageH, int pitch, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the upper halo edge
const int baseX = blockIdx.x * COLUMNS_BLOCKDIM_X + threadIdx.x;
const int baseY = (blockIdx.y * COLUMNS_RESULT_STEPS - Halo_steps) * COLUMNS_BLOCKDIM_Y + threadIdx.y;
if (baseX < imageW)
{
d_Src += baseY * pitch + baseX;
d_Dst += 2 * baseY * pitch + baseX;
//Upper halo
//#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y >= 0) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Lower halo + Main data
//#pragma unroll
for (int i = Halo_steps; i < Halo_steps + COLUMNS_RESULT_STEPS + Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y < imageH) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Compute and store results
__syncthreads();
//#pragma unroll
for (int i = Halo_steps; i < COLUMNS_RESULT_STEPS + Halo_steps; ++i)
{
int Pos_y = 2 * baseY + (2 * i) * COLUMNS_BLOCKDIM_Y;
if (Pos_y < n_imageH)
{
float sum_1 = 0.0f, sum_2 = 0.0f;
//#pragma unroll
for (int l = -(filter_Rad / 2); l <= filter_Rad / 2; ++l)
{
int t = 2 * l;
float temp = s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + l];
sum_1 += c_Kernel[filter_Rad + t] * temp * 2.0f;
sum_2 += c_Kernel[filter_Rad + t - 1] * temp * 2.0f;
}
sum_2 += c_Kernel[2 * filter_Rad] * 2.0f * s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + filter_Rad / 2 + 1];
d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch] = sum_1;
if (Pos_y + 1 < n_imageH)d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch + pitch] = sum_2;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionColumnsKernel_up_smp( float *d_Dst, float *d_Src, int imageW, int imageH, int n_imageH, int pitch, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the upper halo edge
const int baseX = blockIdx.x * COLUMNS_BLOCKDIM_X + threadIdx.x;
const int baseY = (blockIdx.y * COLUMNS_RESULT_STEPS - Halo_steps) * COLUMNS_BLOCKDIM_Y + threadIdx.y;
if (baseX < imageW)
{
d_Src += baseY * pitch + baseX;
d_Dst += 2 * baseY * pitch + baseX;
//Upper halo
//#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y >= 0) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Lower halo + Main data
//#pragma unroll
for (int i = Halo_steps; i < Halo_steps + COLUMNS_RESULT_STEPS + Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y < imageH) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Compute and store results
__syncthreads();
//#pragma unroll
for (int i = Halo_steps; i < COLUMNS_RESULT_STEPS + Halo_steps; ++i)
{
int Pos_y = 2 * baseY + (2 * i) * COLUMNS_BLOCKDIM_Y;
if (Pos_y < n_imageH)
{
float sum_1 = 0.0f, sum_2 = 0.0f;
//#pragma unroll
for (int l = -(filter_Rad / 2); l <= filter_Rad / 2; ++l)
{
int t = 2 * l;
float temp = s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + l];
sum_1 += c_Kernel[filter_Rad + t] * temp * 2.0f;
sum_2 += c_Kernel[filter_Rad + t - 1] * temp * 2.0f;
}
sum_2 += c_Kernel[2 * filter_Rad] * 2.0f * s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + filter_Rad / 2 + 1];
d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch] = sum_1;
if (Pos_y + 1 < n_imageH)d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch + pitch] = sum_2;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.globl _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.p2align 8
.type _Z31convolutionColumnsKernel_up_smpPfS_iiiiii,@function
_Z31convolutionColumnsKernel_up_smpPfS_iiiiii:
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s14, 2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s15, 6
s_waitcnt lgkmcnt(0)
s_lshl_b32 s4, s6, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s2, s5, s4
s_cmp_lt_i32 s6, 1
v_add_nc_u32_e32 v3, s2, v0
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[4:5], null, v3, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_cbranch_scc1 .LBB0_6
s_lshl_b32 s2, s6, 1
v_lshlrev_b32_e32 v8, 2, v0
s_add_i32 s2, s2, 4
s_lshl_b32 s8, s7, 4
v_mul_lo_u32 v6, v2, s2
s_mov_b32 s2, 0
s_mov_b32 s9, 0
s_mov_b32 s10, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 6, v6
v_not_b32_e32 v6, v3
v_add3_u32 v7, v7, v8, 0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
ds_store_b32 v7, v8
v_add_nc_u32_e32 v7, 64, v7
s_add_i32 s10, s10, -1
s_add_i32 s9, s9, 16
s_add_i32 s2, s2, s8
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_6
.LBB0_4:
v_mov_b32_e32 v8, 0
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s9, v6
s_cbranch_execz .LBB0_3
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
v_add_co_u32 v8, vcc_lo, v4, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
global_load_b32 v8, v[8:9], off
s_branch .LBB0_3
.LBB0_6:
s_add_i32 s8, s6, 4
s_cmp_lt_i32 s6, -3
s_cbranch_scc1 .LBB0_11
s_lshl_b32 s2, s6, 1
s_load_b32 s9, s[0:1], 0x14
s_add_i32 s2, s2, 4
s_add_i32 s10, s8, s6
v_mul_lo_u32 v6, v2, s2
s_mul_i32 s2, s6, s7
s_mov_b32 s11, s6
s_lshl_b32 s2, s2, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 4, v6
v_add3_u32 v7, v0, v6, s4
v_add_nc_u32_e32 v6, s5, v0
s_lshl_b32 s5, s7, 4
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v7, v7, 2, 0
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt vmcnt(0)
ds_store_b32 v7, v8
v_add_nc_u32_e32 v6, 16, v6
v_add_nc_u32_e32 v7, 64, v7
s_add_i32 s11, s11, 1
s_add_i32 s2, s2, s5
s_cmp_ge_i32 s11, s10
s_cbranch_scc1 .LBB0_11
.LBB0_9:
v_mov_b32_e32 v8, 0
s_mov_b32 s12, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s9, v6
s_cbranch_execz .LBB0_8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[2:3], 2
v_add_co_u32 v8, vcc_lo, v4, s14
v_add_co_ci_u32_e32 v9, vcc_lo, s15, v5, vcc_lo
global_load_b32 v8, v[8:9], off
s_branch .LBB0_8
.LBB0_11:
s_load_b32 s5, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 1, v3
s_load_b64 s[12:13], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mad_u64_u32 v[4:5], null, v3, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_lshr_b32 s2, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s5, s2
s_ashr_i32 s14, s11, 1
s_cmp_gt_i32 s5, -2
s_cselect_b32 s9, -1, 0
s_lshl_b32 s10, s6, 1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_Kernel@rel32@lo+4
s_addc_u32 s3, s3, c_Kernel@rel32@hi+12
s_add_i32 s10, s10, 4
s_load_b64 s[2:3], s[2:3], 0x0
v_mul_lo_u32 v1, s10, v2
s_load_b32 s10, s[0:1], 0x18
s_lshl_b32 s0, s5, 1
v_add_co_u32 v4, vcc_lo, s12, v4
s_ashr_i32 s1, s0, 31
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 4, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
v_add3_u32 v6, v0, v6, s4
v_add3_u32 v0, v0, s14, 1
s_delay_alu instid0(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s14, v6
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_abs_i32 s4, s14
s_and_b32 s12, s11, -2
v_lshl_add_u32 v6, v6, 2, 0
s_add_i32 s4, s14, s4
s_sub_i32 s12, s5, s12
s_add_i32 s11, s4, 1
s_branch .LBB0_13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v6, 64, v6
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s6, s8
s_cbranch_scc0 .LBB0_19
.LBB0_13:
s_lshl_b32 s14, s6, 5
s_mov_b32 s13, exec_lo
v_add_nc_u32_e32 v8, s14, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v8
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v9, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_17
s_waitcnt vmcnt(0)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v10, v6
v_mov_b32_e32 v9, 0
s_mov_b32 s4, s12
s_mov_b32 s15, s11
.p2align 6
.LBB0_16:
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[4:5], 2
s_add_u32 s16, s2, s16
s_addc_u32 s17, s3, s17
s_add_i32 s15, s15, -1
s_clause 0x1
global_load_b32 v11, v2, s[16:17]
global_load_b32 v12, v2, s[16:17] offset:-4
ds_load_b32 v13, v10
s_add_i32 s4, s4, 2
s_cmp_eq_u32 s15, 0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_dual_mul_f32 v11, v13, v11 :: v_dual_add_nc_u32 v10, 4, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v12, v13, v12 :: v_dual_fmac_f32 v9, 2.0, v11
v_fmac_f32_e32 v7, 2.0, v12
s_cbranch_scc0 .LBB0_16
.LBB0_17:
global_load_b32 v10, v2, s[0:1]
s_mul_i32 s4, s14, s7
v_or_b32_e32 v8, 1, v8
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[4:5], 2
v_add_co_u32 v11, vcc_lo, v4, s14
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s10, v8
global_store_b32 v[11:12], v9, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_12
s_waitcnt vmcnt(0)
v_dual_add_f32 v9, v10, v10 :: v_dual_add_nc_u32 v8, s6, v1
s_add_i32 s4, s4, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s5, s4, 31
v_lshl_add_u32 v8, v8, 4, v0
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v7, v9, v8
v_add_co_u32 v8, vcc_lo, v4, s4
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
global_store_b32 v[8:9], v7, off
s_branch .LBB0_12
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, .Lfunc_end0-_Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_Kernel
.type c_Kernel,@object
.section .bss,"aw",@nobits
.globl c_Kernel
.p2align 3, 0x0
c_Kernel:
.quad 0
.size c_Kernel, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_Kernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z31convolutionColumnsKernel_up_smpPfS_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionColumnsKernel_up_smp( float *d_Dst, float *d_Src, int imageW, int imageH, int n_imageH, int pitch, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the upper halo edge
const int baseX = blockIdx.x * COLUMNS_BLOCKDIM_X + threadIdx.x;
const int baseY = (blockIdx.y * COLUMNS_RESULT_STEPS - Halo_steps) * COLUMNS_BLOCKDIM_Y + threadIdx.y;
if (baseX < imageW)
{
d_Src += baseY * pitch + baseX;
d_Dst += 2 * baseY * pitch + baseX;
//Upper halo
//#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y >= 0) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Lower halo + Main data
//#pragma unroll
for (int i = Halo_steps; i < Halo_steps + COLUMNS_RESULT_STEPS + Halo_steps; i++)
{
s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y] = (baseY + i * COLUMNS_BLOCKDIM_Y < imageH) ? d_Src[i * COLUMNS_BLOCKDIM_Y * pitch] : 0;
}
//Compute and store results
__syncthreads();
//#pragma unroll
for (int i = Halo_steps; i < COLUMNS_RESULT_STEPS + Halo_steps; ++i)
{
int Pos_y = 2 * baseY + (2 * i) * COLUMNS_BLOCKDIM_Y;
if (Pos_y < n_imageH)
{
float sum_1 = 0.0f, sum_2 = 0.0f;
//#pragma unroll
for (int l = -(filter_Rad / 2); l <= filter_Rad / 2; ++l)
{
int t = 2 * l;
float temp = s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + l];
sum_1 += c_Kernel[filter_Rad + t] * temp * 2.0f;
sum_2 += c_Kernel[filter_Rad + t - 1] * temp * 2.0f;
}
sum_2 += c_Kernel[2 * filter_Rad] * 2.0f * s_Data[(threadIdx.x*(COLUMNS_RESULT_STEPS + 2 * Halo_steps) *COLUMNS_BLOCKDIM_Y) + threadIdx.y + i * COLUMNS_BLOCKDIM_Y + filter_Rad / 2 + 1];
d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch] = sum_1;
if (Pos_y + 1 < n_imageH)d_Dst[2 * i * COLUMNS_BLOCKDIM_Y * pitch + pitch] = sum_2;
}
}
}
} | .text
.file "convolutionColumnsKernel_up_smp.hip"
.globl _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii # -- Begin function _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.p2align 4, 0x90
.type _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii,@function
_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii: # @_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31convolutionColumnsKernel_up_smpPfS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii, .Lfunc_end0-_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31convolutionColumnsKernel_up_smpPfS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_Kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_Kernel,@object # @c_Kernel
.local c_Kernel
.comm c_Kernel,8,8
.type _Z31convolutionColumnsKernel_up_smpPfS_iiiiii,@object # @_Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.section .rodata,"a",@progbits
.globl _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.p2align 3, 0x0
_Z31convolutionColumnsKernel_up_smpPfS_iiiiii:
.quad _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.size _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31convolutionColumnsKernel_up_smpPfS_iiiiii"
.size .L__unnamed_1, 46
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_Kernel"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_Kernel
.addrsig_sym _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f3886_00000000-6_convolutionColumnsKernel_up_smp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
.type _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii, @function
_Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31convolutionColumnsKernel_up_smpPfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii, .-_Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
.globl _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.type _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, @function
_Z31convolutionColumnsKernel_up_smpPfS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z59__device_stub__Z31convolutionColumnsKernel_up_smpPfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, .-_Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31convolutionColumnsKernel_up_smpPfS_iiiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31convolutionColumnsKernel_up_smpPfS_iiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_Kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8c_Kernel
.comm _ZL8c_Kernel,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolutionColumnsKernel_up_smp.hip"
.globl _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii # -- Begin function _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.p2align 4, 0x90
.type _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii,@function
_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii: # @_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31convolutionColumnsKernel_up_smpPfS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii, .Lfunc_end0-_Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31convolutionColumnsKernel_up_smpPfS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_Kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_Kernel,@object # @c_Kernel
.local c_Kernel
.comm c_Kernel,8,8
.type _Z31convolutionColumnsKernel_up_smpPfS_iiiiii,@object # @_Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.section .rodata,"a",@progbits
.globl _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.p2align 3, 0x0
_Z31convolutionColumnsKernel_up_smpPfS_iiiiii:
.quad _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.size _Z31convolutionColumnsKernel_up_smpPfS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31convolutionColumnsKernel_up_smpPfS_iiiiii"
.size .L__unnamed_1, 46
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_Kernel"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__convolutionColumnsKernel_up_smpPfS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_Kernel
.addrsig_sym _Z31convolutionColumnsKernel_up_smpPfS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
#include <time.h>
#define blockSize 64
#define Ke 8.99e9
#define Qe -1.602e-19
#define epsilon 1e-8
#define mass 9.11e-31
//macro for error checking
#define cudaCheckError(){ \
cudaError_t err = cudaGetLastError(); \
if(err != cudaSuccess){ \
std::cout << "Error in " << __FILE__ << " at line " << __LINE__ << " : " << cudaGetErrorString(err) << std::endl; \
exit(EXIT_FAILURE); \
} \
}
//calculate bodybody coulomb interactions
__device__ float3 bodyBodyCoulomb(float3 bi, float3 bj, float3 ai){
float3 rij;
//components of rij
rij.x = bj.x - bi.x;
rij.y = bj.y - bi.y;
rij.z = bj.z - bi.z;
//distance squared for solving force equation
float distSquared = rij.x*rij.x + rij.y*rij.y + rij.z*rij.z + epsilon;
if(distSquared > 10){
ai.x = -1;
ai.y = -1;
ai.z = -1;
return ai;
}
//inverse cubed with softening factor
float inverseDist = 1.0f*Qe/sqrtf(distSquared*distSquared*distSquared);
//finish the equation by multiplying by charge
float kernel = Ke*Qe*inverseDist;
//get acceleration for each component
ai.x += rij.x*kernel;
ai.y += rij.y*kernel;
ai.z += rij.z*kernel;
return ai;
}
__device__ float3 tileFunction(float3 position, float3 acceleration, float3* shared){
#pragma unroll
for(int i = 0; i < blockDim.x; i++){
acceleration = bodyBodyCoulomb(position, shared[i], acceleration);
}
return acceleration;
}
__global__ void find_forces(float3* X, float3* A, int numberOfBodies){
float3 position;
float3 acc = {0.0f, 0.0f, 0.0f};
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid < numberOfBodies){
//read into shared memory and calculate tile
position = X[tid];
for(int i = 0, tile = 0; i < gridDim.x; i += blockSize, tile++){
//declare shared memory bank
__shared__ float3 sharedPosition[blockSize];
int idx = tile*blockDim.x + threadIdx.x;
sharedPosition[threadIdx.x] = X[idx];
__syncthreads();
acc = tileFunction(position, acc, sharedPosition);
__syncthreads();
}
//read back to global memory for integration step
A[tid] = acc;
}
}
//main
int main(const int argc, const char** argv){
cudaSetDevice(10);
//declare dt, numberofSteps from the command line
float dt = atof(argv[1]);
int numberOfSteps = atoi(argv[2]);
int numberOfBodies = atoi(argv[3]);
//allocate random data array
float3* x;
x = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* v;
v = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* a;
a = (float3*)malloc(numberOfBodies*sizeof(float3));
srand (time(NULL));
//fill random starting position and acceleration
for(int i = 0; i < numberOfBodies; i++){
x[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
}
//allocate cuda memory
float3 *d_x;
cudaMalloc((void**)&d_x, numberOfBodies*sizeof(float3));
float3 *d_a;
cudaMalloc((void**)&d_a, numberOfBodies*sizeof(float3));
//declare gridSize
int gridSize = (numberOfBodies+blockSize-1)/(blockSize);
//start loop over time steps
for(int k = 0; k < numberOfSteps; k++){
//copy position, acceleration to device
cudaMemcpy(d_x, x, numberOfBodies*sizeof(float3), cudaMemcpyHostToDevice);
cudaCheckError();
cudaMemcpy(d_a, a, numberOfBodies*sizeof(float3), cudaMemcpyHostToDevice);
cudaCheckError();
//call kernel
find_forces<<<gridSize, blockSize>>>(d_x, d_a, numberOfBodies);
//copy position, acceleration off device
cudaMemcpy(x, d_x, numberOfBodies*sizeof(float3), cudaMemcpyDeviceToHost);
cudaCheckError();
cudaMemcpy(a, d_a, numberOfBodies*sizeof(float3), cudaMemcpyDeviceToHost);
cudaCheckError();
for(int i = 0; i < numberOfBodies; i++){
if(a[i].x == -1){
v[i].x += 0;
v[i].y += 0;
v[i].z += 0;
}
else{
v[i].x += 0.5*a[i].x*dt*dt/mass;
v[i].y += 0.5*a[i].y*dt*dt/mass;
v[i].z += 0.5*a[i].z*dt*dt/mass;
x[i].x += v[i].x*dt;
x[i].y += v[i].y*dt;
x[i].z += v[i].z*dt;
}
}
}
//read out some results just for fun
for(int i = 0; i < 10; i++){
std::cout << x[i].x << " " << a[i].x << std::endl;
}
free(x);
free(a);
cudaFree(d_x);
cudaFree(d_a);
} | .file "tmpxft_0006a7a6_00000000-6_Nbody.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4425:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4425:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15bodyBodyCoulomb6float3S_S_
.type _Z15bodyBodyCoulomb6float3S_S_, @function
_Z15bodyBodyCoulomb6float3S_S_:
.LFB4420:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %xmm0, 32(%rsp)
movss %xmm1, 40(%rsp)
movq %xmm2, 16(%rsp)
movss %xmm3, 24(%rsp)
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 60(%rsp)
movl 60(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4420:
.size _Z15bodyBodyCoulomb6float3S_S_, .-_Z15bodyBodyCoulomb6float3S_S_
.globl _Z12tileFunction6float3S_PS_
.type _Z12tileFunction6float3S_PS_, @function
_Z12tileFunction6float3S_PS_:
.LFB4421:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4421:
.size _Z12tileFunction6float3S_PS_, .-_Z12tileFunction6float3S_PS_
.globl _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
.type _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i, @function
_Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i:
.LFB4447:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11find_forcesP6float3S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4447:
.size _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i, .-_Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
.globl _Z11find_forcesP6float3S0_i
.type _Z11find_forcesP6float3S0_i, @function
_Z11find_forcesP6float3S0_i:
.LFB4448:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4448:
.size _Z11find_forcesP6float3S0_i, .-_Z11find_forcesP6float3S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error in "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dgates8/personal-/master/NBody/Nbody.cu"
.section .rodata.str1.1
.LC4:
.string " at line "
.LC5:
.string " : "
.LC10:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4422:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $10, %edi
call cudaSetDevice@PLT
movq 8(%rbx), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 4(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, 24(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movl %eax, 28(%rsp)
cltq
leaq (%rax,%rax,2), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L16
movq %rbp, %rdi
movq %r14, %rbp
movq %r15, %r12
leal -1(%rdi), %eax
leaq (%rax,%rax,2), %rax
leaq 12(%r14,%rax,4), %rax
movq %r14, 40(%rsp)
movq %rax, %r14
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 0(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, (%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%r12)
addq $12, %rbp
addq $12, %r13
addq $12, %r12
cmpq %r14, %rbp
jne .L17
movq 40(%rsp), %r14
.L16:
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 16(%rsp), %rdi
movl %edi, %eax
addl $126, %eax
movl %edi, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 16(%rsp)
cmpl $0, 32(%rsp)
jle .L18
leal -1(%rdi), %eax
leaq (%rax,%rax,2), %rax
movq 8(%rsp), %rdi
leaq 12(%rdi,%rax,4), %rbp
movl $0, %r13d
movl 28(%rsp), %r12d
jmp .L30
.L45:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $144, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L46:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $146, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L47:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
jmp .L21
.L48:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $154, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L23:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $156, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L26:
movss 4(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
divsd .LC9(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax)
pxor %xmm4, %xmm4
cvtss2sd 4(%rsi), %xmm4
mulsd .LC8(%rip), %xmm4
mulsd %xmm5, %xmm4
mulsd %xmm5, %xmm4
divsd .LC9(%rip), %xmm4
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
addsd %xmm1, %xmm4
cvtsd2ss %xmm4, %xmm4
movss %xmm4, 4(%rax)
pxor %xmm1, %xmm1
cvtss2sd 8(%rsi), %xmm1
mulsd .LC8(%rip), %xmm1
mulsd %xmm5, %xmm1
mulsd %xmm5, %xmm1
divsd .LC9(%rip), %xmm1
pxor %xmm5, %xmm5
cvtss2sd 8(%rax), %xmm5
addsd %xmm5, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 8(%rax)
mulss %xmm6, %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
mulss %xmm6, %xmm4
addss 4(%rdx), %xmm4
movss %xmm4, 4(%rdx)
mulss %xmm6, %xmm1
addss 8(%rdx), %xmm1
movss %xmm1, 8(%rdx)
.L28:
addq $12, %rcx
addq $12, %rax
addq $12, %rdx
cmpq %rbp, %rax
je .L25
.L29:
movq %rcx, %rsi
movss (%rcx), %xmm0
ucomiss .LC6(%rip), %xmm0
jp .L26
ucomiss %xmm2, %xmm0
jne .L26
movaps %xmm3, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
movaps %xmm3, %xmm0
addss 4(%rax), %xmm0
movss %xmm0, 4(%rax)
movaps %xmm3, %xmm0
addss 8(%rax), %xmm0
movss %xmm0, 8(%rax)
jmp .L28
.L25:
addl $1, %r13d
movl 24(%rsp), %eax
cmpl %eax, %r13d
je .L18
.L30:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L45
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 16(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L21:
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L48
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movq %r15, %rcx
movq %r14, %rdx
movq 8(%rsp), %rax
movss .LC6(%rip), %xmm2
pxor %xmm3, %xmm3
testl %r12d, %r12d
jg .L29
jmp .L25
.L18:
movl $0, %ebp
leaq .LC10(%rip), %r13
jmp .L35
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L33:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L34:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbp
cmpq $120, %rbp
je .L50
.L35:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L51
cmpb $0, 56(%r12)
je .L33
movzbl 67(%r12), %esi
jmp .L34
.L50:
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4422:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z11find_forcesP6float3S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4450:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11find_forcesP6float3S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4450:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC6:
.long -1082130432
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1071644672
.align 8
.LC9:
.long -1270622874
.long 967997998
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
#include <time.h>
#define blockSize 64
#define Ke 8.99e9
#define Qe -1.602e-19
#define epsilon 1e-8
#define mass 9.11e-31
//macro for error checking
#define cudaCheckError(){ \
cudaError_t err = cudaGetLastError(); \
if(err != cudaSuccess){ \
std::cout << "Error in " << __FILE__ << " at line " << __LINE__ << " : " << cudaGetErrorString(err) << std::endl; \
exit(EXIT_FAILURE); \
} \
}
//calculate bodybody coulomb interactions
__device__ float3 bodyBodyCoulomb(float3 bi, float3 bj, float3 ai){
float3 rij;
//components of rij
rij.x = bj.x - bi.x;
rij.y = bj.y - bi.y;
rij.z = bj.z - bi.z;
//distance squared for solving force equation
float distSquared = rij.x*rij.x + rij.y*rij.y + rij.z*rij.z + epsilon;
if(distSquared > 10){
ai.x = -1;
ai.y = -1;
ai.z = -1;
return ai;
}
//inverse cubed with softening factor
float inverseDist = 1.0f*Qe/sqrtf(distSquared*distSquared*distSquared);
//finish the equation by multiplying by charge
float kernel = Ke*Qe*inverseDist;
//get acceleration for each component
ai.x += rij.x*kernel;
ai.y += rij.y*kernel;
ai.z += rij.z*kernel;
return ai;
}
__device__ float3 tileFunction(float3 position, float3 acceleration, float3* shared){
#pragma unroll
for(int i = 0; i < blockDim.x; i++){
acceleration = bodyBodyCoulomb(position, shared[i], acceleration);
}
return acceleration;
}
__global__ void find_forces(float3* X, float3* A, int numberOfBodies){
float3 position;
float3 acc = {0.0f, 0.0f, 0.0f};
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid < numberOfBodies){
//read into shared memory and calculate tile
position = X[tid];
for(int i = 0, tile = 0; i < gridDim.x; i += blockSize, tile++){
//declare shared memory bank
__shared__ float3 sharedPosition[blockSize];
int idx = tile*blockDim.x + threadIdx.x;
sharedPosition[threadIdx.x] = X[idx];
__syncthreads();
acc = tileFunction(position, acc, sharedPosition);
__syncthreads();
}
//read back to global memory for integration step
A[tid] = acc;
}
}
//main
int main(const int argc, const char** argv){
cudaSetDevice(10);
//declare dt, numberofSteps from the command line
float dt = atof(argv[1]);
int numberOfSteps = atoi(argv[2]);
int numberOfBodies = atoi(argv[3]);
//allocate random data array
float3* x;
x = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* v;
v = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* a;
a = (float3*)malloc(numberOfBodies*sizeof(float3));
srand (time(NULL));
//fill random starting position and acceleration
for(int i = 0; i < numberOfBodies; i++){
x[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
}
//allocate cuda memory
float3 *d_x;
cudaMalloc((void**)&d_x, numberOfBodies*sizeof(float3));
float3 *d_a;
cudaMalloc((void**)&d_a, numberOfBodies*sizeof(float3));
//declare gridSize
int gridSize = (numberOfBodies+blockSize-1)/(blockSize);
//start loop over time steps
for(int k = 0; k < numberOfSteps; k++){
//copy position, acceleration to device
cudaMemcpy(d_x, x, numberOfBodies*sizeof(float3), cudaMemcpyHostToDevice);
cudaCheckError();
cudaMemcpy(d_a, a, numberOfBodies*sizeof(float3), cudaMemcpyHostToDevice);
cudaCheckError();
//call kernel
find_forces<<<gridSize, blockSize>>>(d_x, d_a, numberOfBodies);
//copy position, acceleration off device
cudaMemcpy(x, d_x, numberOfBodies*sizeof(float3), cudaMemcpyDeviceToHost);
cudaCheckError();
cudaMemcpy(a, d_a, numberOfBodies*sizeof(float3), cudaMemcpyDeviceToHost);
cudaCheckError();
for(int i = 0; i < numberOfBodies; i++){
if(a[i].x == -1){
v[i].x += 0;
v[i].y += 0;
v[i].z += 0;
}
else{
v[i].x += 0.5*a[i].x*dt*dt/mass;
v[i].y += 0.5*a[i].y*dt*dt/mass;
v[i].z += 0.5*a[i].z*dt*dt/mass;
x[i].x += v[i].x*dt;
x[i].y += v[i].y*dt;
x[i].z += v[i].z*dt;
}
}
}
//read out some results just for fun
for(int i = 0; i < 10; i++){
std::cout << x[i].x << " " << a[i].x << std::endl;
}
free(x);
free(a);
cudaFree(d_x);
cudaFree(d_a);
} | #include <hip/hip_runtime.h>
#include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
#include <time.h>
#define blockSize 64
#define Ke 8.99e9
#define Qe -1.602e-19
#define epsilon 1e-8
#define mass 9.11e-31
//macro for error checking
#define cudaCheckError(){ \
hipError_t err = hipGetLastError(); \
if(err != hipSuccess){ \
std::cout << "Error in " << __FILE__ << " at line " << __LINE__ << " : " << hipGetErrorString(err) << std::endl; \
exit(EXIT_FAILURE); \
} \
}
//calculate bodybody coulomb interactions
__device__ float3 bodyBodyCoulomb(float3 bi, float3 bj, float3 ai){
float3 rij;
//components of rij
rij.x = bj.x - bi.x;
rij.y = bj.y - bi.y;
rij.z = bj.z - bi.z;
//distance squared for solving force equation
float distSquared = rij.x*rij.x + rij.y*rij.y + rij.z*rij.z + epsilon;
if(distSquared > 10){
ai.x = -1;
ai.y = -1;
ai.z = -1;
return ai;
}
//inverse cubed with softening factor
float inverseDist = 1.0f*Qe/sqrtf(distSquared*distSquared*distSquared);
//finish the equation by multiplying by charge
float kernel = Ke*Qe*inverseDist;
//get acceleration for each component
ai.x += rij.x*kernel;
ai.y += rij.y*kernel;
ai.z += rij.z*kernel;
return ai;
}
__device__ float3 tileFunction(float3 position, float3 acceleration, float3* shared){
#pragma unroll
for(int i = 0; i < blockDim.x; i++){
acceleration = bodyBodyCoulomb(position, shared[i], acceleration);
}
return acceleration;
}
__global__ void find_forces(float3* X, float3* A, int numberOfBodies){
float3 position;
float3 acc = {0.0f, 0.0f, 0.0f};
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid < numberOfBodies){
//read into shared memory and calculate tile
position = X[tid];
for(int i = 0, tile = 0; i < gridDim.x; i += blockSize, tile++){
//declare shared memory bank
__shared__ float3 sharedPosition[blockSize];
int idx = tile*blockDim.x + threadIdx.x;
sharedPosition[threadIdx.x] = X[idx];
__syncthreads();
acc = tileFunction(position, acc, sharedPosition);
__syncthreads();
}
//read back to global memory for integration step
A[tid] = acc;
}
}
//main
int main(const int argc, const char** argv){
hipSetDevice(10);
//declare dt, numberofSteps from the command line
float dt = atof(argv[1]);
int numberOfSteps = atoi(argv[2]);
int numberOfBodies = atoi(argv[3]);
//allocate random data array
float3* x;
x = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* v;
v = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* a;
a = (float3*)malloc(numberOfBodies*sizeof(float3));
srand (time(NULL));
//fill random starting position and acceleration
for(int i = 0; i < numberOfBodies; i++){
x[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
}
//allocate cuda memory
float3 *d_x;
hipMalloc((void**)&d_x, numberOfBodies*sizeof(float3));
float3 *d_a;
hipMalloc((void**)&d_a, numberOfBodies*sizeof(float3));
//declare gridSize
int gridSize = (numberOfBodies+blockSize-1)/(blockSize);
//start loop over time steps
for(int k = 0; k < numberOfSteps; k++){
//copy position, acceleration to device
hipMemcpy(d_x, x, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
hipMemcpy(d_a, a, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
//call kernel
find_forces<<<gridSize, blockSize>>>(d_x, d_a, numberOfBodies);
//copy position, acceleration off device
hipMemcpy(x, d_x, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
hipMemcpy(a, d_a, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
for(int i = 0; i < numberOfBodies; i++){
if(a[i].x == -1){
v[i].x += 0;
v[i].y += 0;
v[i].z += 0;
}
else{
v[i].x += 0.5*a[i].x*dt*dt/mass;
v[i].y += 0.5*a[i].y*dt*dt/mass;
v[i].z += 0.5*a[i].z*dt*dt/mass;
x[i].x += v[i].x*dt;
x[i].y += v[i].y*dt;
x[i].z += v[i].z*dt;
}
}
}
//read out some results just for fun
for(int i = 0; i < 10; i++){
std::cout << x[i].x << " " << a[i].x << std::endl;
}
free(x);
free(a);
hipFree(d_x);
hipFree(d_a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
#include <time.h>
#define blockSize 64
#define Ke 8.99e9
#define Qe -1.602e-19
#define epsilon 1e-8
#define mass 9.11e-31
//macro for error checking
#define cudaCheckError(){ \
hipError_t err = hipGetLastError(); \
if(err != hipSuccess){ \
std::cout << "Error in " << __FILE__ << " at line " << __LINE__ << " : " << hipGetErrorString(err) << std::endl; \
exit(EXIT_FAILURE); \
} \
}
//calculate bodybody coulomb interactions
__device__ float3 bodyBodyCoulomb(float3 bi, float3 bj, float3 ai){
float3 rij;
//components of rij
rij.x = bj.x - bi.x;
rij.y = bj.y - bi.y;
rij.z = bj.z - bi.z;
//distance squared for solving force equation
float distSquared = rij.x*rij.x + rij.y*rij.y + rij.z*rij.z + epsilon;
if(distSquared > 10){
ai.x = -1;
ai.y = -1;
ai.z = -1;
return ai;
}
//inverse cubed with softening factor
float inverseDist = 1.0f*Qe/sqrtf(distSquared*distSquared*distSquared);
//finish the equation by multiplying by charge
float kernel = Ke*Qe*inverseDist;
//get acceleration for each component
ai.x += rij.x*kernel;
ai.y += rij.y*kernel;
ai.z += rij.z*kernel;
return ai;
}
__device__ float3 tileFunction(float3 position, float3 acceleration, float3* shared){
#pragma unroll
for(int i = 0; i < blockDim.x; i++){
acceleration = bodyBodyCoulomb(position, shared[i], acceleration);
}
return acceleration;
}
__global__ void find_forces(float3* X, float3* A, int numberOfBodies){
float3 position;
float3 acc = {0.0f, 0.0f, 0.0f};
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid < numberOfBodies){
//read into shared memory and calculate tile
position = X[tid];
for(int i = 0, tile = 0; i < gridDim.x; i += blockSize, tile++){
//declare shared memory bank
__shared__ float3 sharedPosition[blockSize];
int idx = tile*blockDim.x + threadIdx.x;
sharedPosition[threadIdx.x] = X[idx];
__syncthreads();
acc = tileFunction(position, acc, sharedPosition);
__syncthreads();
}
//read back to global memory for integration step
A[tid] = acc;
}
}
//main
int main(const int argc, const char** argv){
hipSetDevice(10);
//declare dt, numberofSteps from the command line
float dt = atof(argv[1]);
int numberOfSteps = atoi(argv[2]);
int numberOfBodies = atoi(argv[3]);
//allocate random data array
float3* x;
x = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* v;
v = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* a;
a = (float3*)malloc(numberOfBodies*sizeof(float3));
srand (time(NULL));
//fill random starting position and acceleration
for(int i = 0; i < numberOfBodies; i++){
x[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
}
//allocate cuda memory
float3 *d_x;
hipMalloc((void**)&d_x, numberOfBodies*sizeof(float3));
float3 *d_a;
hipMalloc((void**)&d_a, numberOfBodies*sizeof(float3));
//declare gridSize
int gridSize = (numberOfBodies+blockSize-1)/(blockSize);
//start loop over time steps
for(int k = 0; k < numberOfSteps; k++){
//copy position, acceleration to device
hipMemcpy(d_x, x, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
hipMemcpy(d_a, a, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
//call kernel
find_forces<<<gridSize, blockSize>>>(d_x, d_a, numberOfBodies);
//copy position, acceleration off device
hipMemcpy(x, d_x, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
hipMemcpy(a, d_a, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
for(int i = 0; i < numberOfBodies; i++){
if(a[i].x == -1){
v[i].x += 0;
v[i].y += 0;
v[i].z += 0;
}
else{
v[i].x += 0.5*a[i].x*dt*dt/mass;
v[i].y += 0.5*a[i].y*dt*dt/mass;
v[i].z += 0.5*a[i].z*dt*dt/mass;
x[i].x += v[i].x*dt;
x[i].y += v[i].y*dt;
x[i].z += v[i].z*dt;
}
}
}
//read out some results just for fun
for(int i = 0; i < 10; i++){
std::cout << x[i].x << " " << a[i].x << std::endl;
}
free(x);
free(a);
hipFree(d_x);
hipFree(d_a);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.globl _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.p2align 8
.type _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i,@function
_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[7:8], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v7
s_cbranch_execz .LBB0_23
s_load_b32 s2, s[2:3], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v6, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_22
s_load_b64 s[4:5], s[0:1], 0x0
s_add_i32 s2, s2, -1
s_and_b32 s14, s12, 0xfffe
s_lshr_b32 s13, s2, 6
v_mul_u32_u24_e32 v8, 12, v0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v6, 0
s_bitcmp1_b32 s12, 0
s_mov_b32 s7, 0x3e45798e
s_cselect_b32 s15, -1, 0
s_mov_b32 s6, 0xe2308c3a
s_mov_b32 s9, 0xbc07a42f
s_mov_b32 s8, 0x549647fb
s_mov_b32 s11, 0xbe18be0e
s_mov_b32 s10, 0xcb45df97
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[1:2], null, v7, 12, s[4:5]
global_load_b96 v[1:3], v[1:2], off
.LBB0_3:
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, s3, s12, v[0:1]
v_cmp_lt_i16_e64 s2, s12, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s2
v_mad_i64_i32 v[10:11], null, v9, 12, s[4:5]
global_load_b96 v[9:11], v[10:11], off
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v8, v9, v10 offset1:1
ds_store_b32 v8, v11 offset:8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_5
v_cmp_ne_u16_e64 s17, s12, 1
s_mov_b32 s2, -1
s_mov_b32 s16, 0
s_cbranch_execz .LBB0_6
s_branch .LBB0_7
.LBB0_5:
s_mov_b32 s2, 0
s_mov_b32 s17, 0
.LBB0_6:
v_cmp_ne_u16_e64 s17, s12, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccz .LBB0_9
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_16
s_branch .LBB0_20
.LBB0_9:
s_mov_b32 s17, 0
s_mov_b32 s16, 0
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s18
s_add_i32 s16, s16, 2
s_add_i32 s17, s17, 24
s_cmp_lg_u32 s14, s16
s_cbranch_scc0 .LBB0_15
.LBB0_11:
v_mov_b32_e32 v11, s17
s_mov_b32 s18, exec_lo
ds_load_2addr_b32 v[9:10], v11 offset1:1
ds_load_b32 v11, v11 offset:8
s_waitcnt lgkmcnt(1)
v_sub_f32_e32 v12, v10, v2
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v14, v9, v1 :: v_dual_sub_f32 v13, v11, v3
v_mov_b32_e32 v11, -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v12, v12
v_fmac_f32_e32 v9, v14, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v13, v13
v_cvt_f64_f32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], s[6:7]
v_cvt_f32_f64_e32 v15, v[9:10]
v_dual_mov_b32 v10, -1.0 :: v_dual_mov_b32 v9, -1.0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f32_e32 0x41200000, v15
s_cbranch_execz .LBB0_13
v_mul_f32_e32 v9, v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v9, v15
v_mul_f32_e32 v10, 0x4f800000, v9
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
v_sqrt_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v11, -1, v10
v_add_nc_u32_e32 v15, 1, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v11, v10, v9
v_fma_f32 v17, -v15, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v16
v_cndmask_b32_e64 v10, v10, v11, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v17
v_cndmask_b32_e64 v10, v10, v15, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x37800000, v10
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v9, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_cvt_f64_f32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[15:16], null, v[9:10], v[9:10], s[8:9]
v_div_scale_f64 v[21:22], vcc_lo, s[8:9], v[9:10], s[8:9]
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_mul_f64 v[19:20], v[21:22], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[9:10], v[15:16], v[9:10], s[8:9]
v_cvt_f32_f64_e32 v9, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_mul_f64 v[9:10], v[9:10], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v9, v[9:10]
v_fmac_f32_e32 v6, v13, v9
v_fmac_f32_e32 v4, v14, v9
v_fmac_f32_e32 v5, v12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v6
v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v10, v5
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s18
v_mov_b32_e32 v6, s17
s_mov_b32 s18, exec_lo
ds_load_2addr_b32 v[4:5], v6 offset0:3 offset1:4
ds_load_b32 v6, v6 offset:20
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v12, v5, v2 :: v_dual_sub_f32 v13, v6, v3
v_sub_f32_e32 v14, v4, v1
v_mov_b32_e32 v6, -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v12, v12
v_fmac_f32_e32 v4, v14, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v13, v13
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], s[6:7]
v_cvt_f32_f64_e32 v15, v[4:5]
v_dual_mov_b32 v4, -1.0 :: v_dual_mov_b32 v5, -1.0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f32_e32 0x41200000, v15
s_cbranch_execz .LBB0_10
v_mul_f32_e32 v4, v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v15
v_mul_f32_e32 v5, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_sqrt_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v15, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v6, v5, v4
v_fma_f32 v17, -v15, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v16
v_cndmask_b32_e64 v5, v5, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v17
v_cndmask_b32_e64 v5, v5, v15, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[15:16], null, v[4:5], v[4:5], s[8:9]
v_div_scale_f64 v[21:22], vcc_lo, s[8:9], v[4:5], s[8:9]
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_mul_f64 v[19:20], v[21:22], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[15:16], v[4:5], s[8:9]
v_cvt_f32_f64_e32 v4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v4
v_mul_f64 v[4:5], v[4:5], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[4:5]
v_fmac_f32_e32 v11, v13, v4
v_fmac_f32_e32 v9, v14, v4
v_fmac_f32_e32 v10, v12, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v11
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_branch .LBB0_10
.LBB0_15:
s_cbranch_execz .LBB0_20
.LBB0_16:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_20
s_mul_i32 s2, s16, 12
s_mov_b32 s16, exec_lo
v_mov_b32_e32 v11, s2
ds_load_2addr_b32 v[9:10], v11 offset1:1
ds_load_b32 v11, v11 offset:8
s_waitcnt lgkmcnt(1)
v_dual_mov_b32 v15, -1.0 :: v_dual_sub_f32 v10, v10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v1 :: v_dual_mul_f32 v12, v10, v10
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v11, v11, v3 :: v_dual_fmac_f32 v12, v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v11, v11
v_cvt_f64_f32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], s[6:7]
v_cvt_f32_f64_e32 v14, v[12:13]
v_dual_mov_b32 v13, -1.0 :: v_dual_mov_b32 v12, -1.0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f32_e32 0x41200000, v14
s_cbranch_execz .LBB0_19
v_mul_f32_e32 v12, v14, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v12, v14
v_mul_f32_e32 v13, 0x4f800000, v12
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
v_sqrt_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v14, -1, v13
v_add_nc_u32_e32 v15, 1, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v14, v13, v12
v_fma_f32 v17, -v15, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v16
v_cndmask_b32_e64 v13, v13, v14, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v17
v_cndmask_b32_e64 v13, v13, v15, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, 0x37800000, v13
v_cndmask_b32_e32 v13, v13, v14, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v12, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, v13, v12, vcc_lo
v_cvt_f64_f32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], s[8:9]
v_div_scale_f64 v[20:21], vcc_lo, s[8:9], v[12:13], s[8:9]
v_rcp_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_mul_f64 v[18:19], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[14:15], v[18:19], v[20:21]
v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[12:13], v[14:15], v[12:13], s[8:9]
v_cvt_f32_f64_e32 v12, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[12:13], v12
v_mul_f64 v[12:13], v[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v12, v[12:13]
v_fmac_f32_e32 v6, v11, v12
v_fmac_f32_e32 v5, v10, v12
v_fmac_f32_e32 v4, v9, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v13, v5
v_mov_b32_e32 v15, v4
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v12 :: v_dual_mov_b32 v5, v13
v_mov_b32_e32 v4, v15
.LBB0_20:
s_add_i32 s2, s3, 1
s_cmp_eq_u32 s3, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_22
s_mov_b32 s3, s2
s_branch .LBB0_3
.LBB0_22:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v7, 12, s[0:1]
global_store_b96 v[0:1], v[4:6], off
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.amdhsa_group_segment_fixed_size 768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, .Lfunc_end0-_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 768
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
#include <time.h>
#define blockSize 64
#define Ke 8.99e9
#define Qe -1.602e-19
#define epsilon 1e-8
#define mass 9.11e-31
//macro for error checking
#define cudaCheckError(){ \
hipError_t err = hipGetLastError(); \
if(err != hipSuccess){ \
std::cout << "Error in " << __FILE__ << " at line " << __LINE__ << " : " << hipGetErrorString(err) << std::endl; \
exit(EXIT_FAILURE); \
} \
}
//calculate bodybody coulomb interactions
__device__ float3 bodyBodyCoulomb(float3 bi, float3 bj, float3 ai){
float3 rij;
//components of rij
rij.x = bj.x - bi.x;
rij.y = bj.y - bi.y;
rij.z = bj.z - bi.z;
//distance squared for solving force equation
float distSquared = rij.x*rij.x + rij.y*rij.y + rij.z*rij.z + epsilon;
if(distSquared > 10){
ai.x = -1;
ai.y = -1;
ai.z = -1;
return ai;
}
//inverse cubed with softening factor
float inverseDist = 1.0f*Qe/sqrtf(distSquared*distSquared*distSquared);
//finish the equation by multiplying by charge
float kernel = Ke*Qe*inverseDist;
//get acceleration for each component
ai.x += rij.x*kernel;
ai.y += rij.y*kernel;
ai.z += rij.z*kernel;
return ai;
}
__device__ float3 tileFunction(float3 position, float3 acceleration, float3* shared){
#pragma unroll
for(int i = 0; i < blockDim.x; i++){
acceleration = bodyBodyCoulomb(position, shared[i], acceleration);
}
return acceleration;
}
__global__ void find_forces(float3* X, float3* A, int numberOfBodies){
float3 position;
float3 acc = {0.0f, 0.0f, 0.0f};
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid < numberOfBodies){
//read into shared memory and calculate tile
position = X[tid];
for(int i = 0, tile = 0; i < gridDim.x; i += blockSize, tile++){
//declare shared memory bank
__shared__ float3 sharedPosition[blockSize];
int idx = tile*blockDim.x + threadIdx.x;
sharedPosition[threadIdx.x] = X[idx];
__syncthreads();
acc = tileFunction(position, acc, sharedPosition);
__syncthreads();
}
//read back to global memory for integration step
A[tid] = acc;
}
}
//main
int main(const int argc, const char** argv){
hipSetDevice(10);
//declare dt, numberofSteps from the command line
float dt = atof(argv[1]);
int numberOfSteps = atoi(argv[2]);
int numberOfBodies = atoi(argv[3]);
//allocate random data array
float3* x;
x = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* v;
v = (float3*)malloc(numberOfBodies*sizeof(float3));
float3* a;
a = (float3*)malloc(numberOfBodies*sizeof(float3));
srand (time(NULL));
//fill random starting position and acceleration
for(int i = 0; i < numberOfBodies; i++){
x[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
x[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
v[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].x = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].y = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
a[i].z = 2.0f * (rand() / (float)RAND_MAX) - 1.0f;
}
//allocate cuda memory
float3 *d_x;
hipMalloc((void**)&d_x, numberOfBodies*sizeof(float3));
float3 *d_a;
hipMalloc((void**)&d_a, numberOfBodies*sizeof(float3));
//declare gridSize
int gridSize = (numberOfBodies+blockSize-1)/(blockSize);
//start loop over time steps
for(int k = 0; k < numberOfSteps; k++){
//copy position, acceleration to device
hipMemcpy(d_x, x, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
hipMemcpy(d_a, a, numberOfBodies*sizeof(float3), hipMemcpyHostToDevice);
cudaCheckError();
//call kernel
find_forces<<<gridSize, blockSize>>>(d_x, d_a, numberOfBodies);
//copy position, acceleration off device
hipMemcpy(x, d_x, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
hipMemcpy(a, d_a, numberOfBodies*sizeof(float3), hipMemcpyDeviceToHost);
cudaCheckError();
for(int i = 0; i < numberOfBodies; i++){
if(a[i].x == -1){
v[i].x += 0;
v[i].y += 0;
v[i].z += 0;
}
else{
v[i].x += 0.5*a[i].x*dt*dt/mass;
v[i].y += 0.5*a[i].y*dt*dt/mass;
v[i].z += 0.5*a[i].z*dt*dt/mass;
x[i].x += v[i].x*dt;
x[i].y += v[i].y*dt;
x[i].z += v[i].z*dt;
}
}
}
//read out some results just for fun
for(int i = 0; i < 10; i++){
std::cout << x[i].x << " " << a[i].x << std::endl;
}
free(x);
free(a);
hipFree(d_x);
hipFree(d_a);
} | .text
.file "Nbody.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i # -- Begin function _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.p2align 4, 0x90
.type _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i,@function
_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i: # @_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i, .Lfunc_end0-_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_3:
.quad 0x39b27a2eb443d566 # double 9.1100000000000003E-31
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $10, %edi
callq hipSetDevice
movq 8(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r15
leaq (,%r15,4), %rax
leaq (%rax,%rax,2), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl 8(%rsp), %eax # 4-byte Reload
shlq $2, %rax
leaq (%rax,%rax,2), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss %xmm0, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%r14,%r12)
addq $12, %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %r12
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpl $0, 48(%rsp) # 4-byte Folded Reload
jle .LBB1_4
# %bb.7: # %.lr.ph137
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movq 8(%rsp), %rcx # 8-byte Reload
leal 63(%rcx), %eax
leal 126(%rcx), %edx
testl %eax, %eax
cmovnsl %eax, %edx
movabsq $4294967296, %rsi # imm = 0x100000000
sarl $6, %edx
orq %rsi, %rdx
movq %rdx, 72(%rsp) # 8-byte Spill
cvtss2sd %xmm4, %xmm5
movl %ecx, %eax
shlq $2, %rax
leaq (%rax,%rax,2), %r15
xorl %eax, %eax
addq $64, %rsi
movq %rsi, 64(%rsp) # 8-byte Spill
movss %xmm4, 40(%rsp) # 4-byte Spill
movsd %xmm5, 56(%rsp) # 8-byte Spill
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_26: # %._crit_edge134
# in Loop: Header=BB1_8 Depth=1
movq 32(%rsp), %rax # 8-byte Reload
incl %eax
cmpl 48(%rsp), %eax # 4-byte Folded Reload
je .LBB1_4
.LBB1_8: # =>This Loop Header: Depth=1
# Child Loop BB1_21 Depth 2
movq %rax, 32(%rsp) # 8-byte Spill
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.14: # in Loop: Header=BB1_8 Depth=1
movq 72(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %edi
leaq 144(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.19: # %.preheader121
# in Loop: Header=BB1_8 Depth=1
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movss 40(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movsd 56(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
movss .LCPI1_1(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movsd .LCPI1_2(%rip), %xmm7 # xmm7 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm8 # xmm8 = mem[0],zero
jle .LBB1_26
# %bb.20: # %.lr.ph133.preheader
# in Loop: Header=BB1_8 Depth=1
xorl %eax, %eax
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_21 Depth=2
xorps %xmm1, %xmm1
movss (%rbp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%rbp,%rax)
movss 4(%rbp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, 4(%rbp,%rax)
movq %rbp, %rcx
.LBB1_25: # in Loop: Header=BB1_21 Depth=2
addss 8(%rcx,%rax), %xmm1
movss %xmm1, 8(%rcx,%rax)
addq $12, %rax
cmpq %rax, %r15
je .LBB1_26
.LBB1_21: # %.lr.ph133
# Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm6, %xmm0
jne .LBB1_24
jnp .LBB1_22
.LBB1_24: # in Loop: Header=BB1_21 Depth=2
cvtss2sd %xmm0, %xmm0
mulsd %xmm7, %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
divsd %xmm8, %xmm0
movss (%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss 4(%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm0, (%rbp,%rax)
movss 4(%r14,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm7, %xmm2
mulsd %xmm5, %xmm2
mulsd %xmm5, %xmm2
divsd %xmm8, %xmm2
cvtss2sd %xmm1, %xmm1
addsd %xmm2, %xmm1
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movss %xmm2, 4(%rbp,%rax)
movss 8(%r14,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm7, %xmm1
mulsd %xmm5, %xmm1
mulsd %xmm5, %xmm1
divsd %xmm8, %xmm1
movss 8(%rbp,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsd2ss %xmm3, %xmm1
mulss %xmm4, %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
mulss %xmm4, %xmm2
addss 4(%rbx,%rax), %xmm2
movss %xmm1, 8(%rbp,%rax)
movss %xmm2, 4(%rbx,%rax)
mulss %xmm4, %xmm1
movq %rbx, %rcx
jmp .LBB1_25
.LBB1_4: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r15), %ecx
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r12
cmpq $120, %r12
je .LBB1_31
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_6
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r15)
jne .LBB1_28
# %bb.29: # in Loop: Header=BB1_5 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
jmp .LBB1_30
.LBB1_31:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.LBB1_23:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $158, %esi
jmp .LBB1_12
.LBB1_17:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $156, %esi
jmp .LBB1_12
.LBB1_11:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $148, %esi
.LBB1_12:
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
jmp .LBB1_13
.LBB1_9:
movl %eax, %r13d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $146, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl %r13d, %edi
callq hipGetErrorString
movq %rbx, %rdi
.LBB1_13:
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i,@object # @_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.section .rodata,"a",@progbits
.globl _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.p2align 3, 0x0
_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i:
.quad _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.size _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dgates8/personal-/master/NBody/Nbody.hip"
.size .L.str.1, 98
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " at line "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " : "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a7a6_00000000-6_Nbody.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4425:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4425:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15bodyBodyCoulomb6float3S_S_
.type _Z15bodyBodyCoulomb6float3S_S_, @function
_Z15bodyBodyCoulomb6float3S_S_:
.LFB4420:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %xmm0, 32(%rsp)
movss %xmm1, 40(%rsp)
movq %xmm2, 16(%rsp)
movss %xmm3, 24(%rsp)
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 60(%rsp)
movl 60(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4420:
.size _Z15bodyBodyCoulomb6float3S_S_, .-_Z15bodyBodyCoulomb6float3S_S_
.globl _Z12tileFunction6float3S_PS_
.type _Z12tileFunction6float3S_PS_, @function
_Z12tileFunction6float3S_PS_:
.LFB4421:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4421:
.size _Z12tileFunction6float3S_PS_, .-_Z12tileFunction6float3S_PS_
.globl _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
.type _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i, @function
_Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i:
.LFB4447:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11find_forcesP6float3S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4447:
.size _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i, .-_Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
.globl _Z11find_forcesP6float3S0_i
.type _Z11find_forcesP6float3S0_i, @function
_Z11find_forcesP6float3S0_i:
.LFB4448:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4448:
.size _Z11find_forcesP6float3S0_i, .-_Z11find_forcesP6float3S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error in "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dgates8/personal-/master/NBody/Nbody.cu"
.section .rodata.str1.1
.LC4:
.string " at line "
.LC5:
.string " : "
.LC10:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4422:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $10, %edi
call cudaSetDevice@PLT
movq 8(%rbx), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 4(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, 24(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movl %eax, 28(%rsp)
cltq
leaq (%rax,%rax,2), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L16
movq %rbp, %rdi
movq %r14, %rbp
movq %r15, %r12
leal -1(%rdi), %eax
leaq (%rax,%rax,2), %rax
leaq 12(%r14,%rax,4), %rax
movq %r14, 40(%rsp)
movq %rax, %r14
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 0(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, (%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 4(%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss %xmm0, %xmm0
subss .LC1(%rip), %xmm0
movss %xmm0, 8(%r12)
addq $12, %rbp
addq $12, %r13
addq $12, %r12
cmpq %r14, %rbp
jne .L17
movq 40(%rsp), %r14
.L16:
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 16(%rsp), %rdi
movl %edi, %eax
addl $126, %eax
movl %edi, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 16(%rsp)
cmpl $0, 32(%rsp)
jle .L18
leal -1(%rdi), %eax
leaq (%rax,%rax,2), %rax
movq 8(%rsp), %rdi
leaq 12(%rdi,%rax,4), %rbp
movl $0, %r13d
movl 28(%rsp), %r12d
jmp .L30
.L45:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $144, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L46:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $146, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L47:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z41__device_stub__Z11find_forcesP6float3S0_iP6float3S0_i
jmp .L21
.L48:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $154, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L23:
movl %eax, %r12d
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $156, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L26:
movss 4(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
divsd .LC9(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rax)
pxor %xmm4, %xmm4
cvtss2sd 4(%rsi), %xmm4
mulsd .LC8(%rip), %xmm4
mulsd %xmm5, %xmm4
mulsd %xmm5, %xmm4
divsd .LC9(%rip), %xmm4
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
addsd %xmm1, %xmm4
cvtsd2ss %xmm4, %xmm4
movss %xmm4, 4(%rax)
pxor %xmm1, %xmm1
cvtss2sd 8(%rsi), %xmm1
mulsd .LC8(%rip), %xmm1
mulsd %xmm5, %xmm1
mulsd %xmm5, %xmm1
divsd .LC9(%rip), %xmm1
pxor %xmm5, %xmm5
cvtss2sd 8(%rax), %xmm5
addsd %xmm5, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 8(%rax)
mulss %xmm6, %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
mulss %xmm6, %xmm4
addss 4(%rdx), %xmm4
movss %xmm4, 4(%rdx)
mulss %xmm6, %xmm1
addss 8(%rdx), %xmm1
movss %xmm1, 8(%rdx)
.L28:
addq $12, %rcx
addq $12, %rax
addq $12, %rdx
cmpq %rbp, %rax
je .L25
.L29:
movq %rcx, %rsi
movss (%rcx), %xmm0
ucomiss .LC6(%rip), %xmm0
jp .L26
ucomiss %xmm2, %xmm0
jne .L26
movaps %xmm3, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
movaps %xmm3, %xmm0
addss 4(%rax), %xmm0
movss %xmm0, 4(%rax)
movaps %xmm3, %xmm0
addss 8(%rax), %xmm0
movss %xmm0, 8(%rax)
jmp .L28
.L25:
addl $1, %r13d
movl 24(%rsp), %eax
cmpl %eax, %r13d
je .L18
.L30:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L45
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 16(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L21:
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L48
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movq %r15, %rcx
movq %r14, %rdx
movq 8(%rsp), %rax
movss .LC6(%rip), %xmm2
pxor %xmm3, %xmm3
testl %r12d, %r12d
jg .L29
jmp .L25
.L18:
movl $0, %ebp
leaq .LC10(%rip), %r13
jmp .L35
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L33:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L34:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbp
cmpq $120, %rbp
je .L50
.L35:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L51
cmpb $0, 56(%r12)
je .L33
movzbl 67(%r12), %esi
jmp .L34
.L50:
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4422:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z11find_forcesP6float3S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4450:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11find_forcesP6float3S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4450:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC6:
.long -1082130432
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1071644672
.align 8
.LC9:
.long -1270622874
.long 967997998
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Nbody.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i # -- Begin function _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.p2align 4, 0x90
.type _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i,@function
_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i: # @_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i, .Lfunc_end0-_Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_3:
.quad 0x39b27a2eb443d566 # double 9.1100000000000003E-31
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $10, %edi
callq hipSetDevice
movq 8(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r15
leaq (,%r15,4), %rax
leaq (%rax,%rax,2), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl 8(%rsp), %eax # 4-byte Reload
shlq $2, %rax
leaq (%rax,%rax,2), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss %xmm0, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%rbp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss %xmm0, %xmm0
addss .LCPI1_1(%rip), %xmm0
movss %xmm0, 8(%r14,%r12)
addq $12, %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %r12
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpl $0, 48(%rsp) # 4-byte Folded Reload
jle .LBB1_4
# %bb.7: # %.lr.ph137
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movq 8(%rsp), %rcx # 8-byte Reload
leal 63(%rcx), %eax
leal 126(%rcx), %edx
testl %eax, %eax
cmovnsl %eax, %edx
movabsq $4294967296, %rsi # imm = 0x100000000
sarl $6, %edx
orq %rsi, %rdx
movq %rdx, 72(%rsp) # 8-byte Spill
cvtss2sd %xmm4, %xmm5
movl %ecx, %eax
shlq $2, %rax
leaq (%rax,%rax,2), %r15
xorl %eax, %eax
addq $64, %rsi
movq %rsi, 64(%rsp) # 8-byte Spill
movss %xmm4, 40(%rsp) # 4-byte Spill
movsd %xmm5, 56(%rsp) # 8-byte Spill
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_26: # %._crit_edge134
# in Loop: Header=BB1_8 Depth=1
movq 32(%rsp), %rax # 8-byte Reload
incl %eax
cmpl 48(%rsp), %eax # 4-byte Folded Reload
je .LBB1_4
.LBB1_8: # =>This Loop Header: Depth=1
# Child Loop BB1_21 Depth 2
movq %rax, 32(%rsp) # 8-byte Spill
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.14: # in Loop: Header=BB1_8 Depth=1
movq 72(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %edi
leaq 144(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.19: # %.preheader121
# in Loop: Header=BB1_8 Depth=1
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movss 40(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movsd 56(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
movss .LCPI1_1(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movsd .LCPI1_2(%rip), %xmm7 # xmm7 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm8 # xmm8 = mem[0],zero
jle .LBB1_26
# %bb.20: # %.lr.ph133.preheader
# in Loop: Header=BB1_8 Depth=1
xorl %eax, %eax
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_21 Depth=2
xorps %xmm1, %xmm1
movss (%rbp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%rbp,%rax)
movss 4(%rbp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, 4(%rbp,%rax)
movq %rbp, %rcx
.LBB1_25: # in Loop: Header=BB1_21 Depth=2
addss 8(%rcx,%rax), %xmm1
movss %xmm1, 8(%rcx,%rax)
addq $12, %rax
cmpq %rax, %r15
je .LBB1_26
.LBB1_21: # %.lr.ph133
# Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm6, %xmm0
jne .LBB1_24
jnp .LBB1_22
.LBB1_24: # in Loop: Header=BB1_21 Depth=2
cvtss2sd %xmm0, %xmm0
mulsd %xmm7, %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
divsd %xmm8, %xmm0
movss (%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss 4(%rbp,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm0, (%rbp,%rax)
movss 4(%r14,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
mulsd %xmm7, %xmm2
mulsd %xmm5, %xmm2
mulsd %xmm5, %xmm2
divsd %xmm8, %xmm2
cvtss2sd %xmm1, %xmm1
addsd %xmm2, %xmm1
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movss %xmm2, 4(%rbp,%rax)
movss 8(%r14,%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm7, %xmm1
mulsd %xmm5, %xmm1
mulsd %xmm5, %xmm1
divsd %xmm8, %xmm1
movss 8(%rbp,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
addsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsd2ss %xmm3, %xmm1
mulss %xmm4, %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
mulss %xmm4, %xmm2
addss 4(%rbx,%rax), %xmm2
movss %xmm1, 8(%rbp,%rax)
movss %xmm2, 4(%rbx,%rax)
mulss %xmm4, %xmm1
movq %rbx, %rcx
jmp .LBB1_25
.LBB1_4: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r15), %ecx
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r12
cmpq $120, %r12
je .LBB1_31
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_6
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r15)
jne .LBB1_28
# %bb.29: # in Loop: Header=BB1_5 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
jmp .LBB1_30
.LBB1_31:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.LBB1_23:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $158, %esi
jmp .LBB1_12
.LBB1_17:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $156, %esi
jmp .LBB1_12
.LBB1_11:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $148, %esi
.LBB1_12:
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
jmp .LBB1_13
.LBB1_9:
movl %eax, %r13d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $146, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl %r13d, %edi
callq hipGetErrorString
movq %rbx, %rdi
.LBB1_13:
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i,@object # @_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.section .rodata,"a",@progbits
.globl _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.p2align 3, 0x0
_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i:
.quad _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.size _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dgates8/personal-/master/NBody/Nbody.hip"
.size .L.str.1, 98
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " at line "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " : "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11find_forcesP15HIP_vector_typeIfLj3EES1_i"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__find_forcesP15HIP_vector_typeIfLj3EES1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11find_forcesP15HIP_vector_typeIfLj3EES1_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} | code for sm_80
Function : _Z13copySharedMemPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0xc] ; /* 0x00000300000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R2, R13.reuse, 0x5, RZ ; /* 0x000000050d027819 */
/* 0x040fe400000006ff */
/*0070*/ SHF.L.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7819 */
/* 0x000fe200000006ff */
/*0080*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0090*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000e620000002200 */
/*00a0*/ LEA R0, R0, R11, 0x5 ; /* 0x0000000b00007211 */
/* 0x001fc400078e28ff */
/*00b0*/ LEA R3, R3, R18, 0x5 ; /* 0x0000001203037211 */
/* 0x002fca00078e28ff */
/*00c0*/ IMAD R0, R3, R2, R0 ; /* 0x0000000203007224 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R23, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0217 */
/*00e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x0002e2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000962000c1e1900 */
/*0130*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fca00078e0206 */
/*0140*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000962000c1e1900 */
/*0150*/ LEA R11, R18, R11, 0x5 ; /* 0x0000000b120b7211 */
/* 0x000fe200078e28ff */
/*0160*/ IMAD.WIDE R2, R0, R23, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0217 */
/*0170*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x002fcc00078e0202 */
/*0180*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x010fcc00078e0204 */
/*0190*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fe200078e0206 */
/*01a0*/ STS [R11.X4], R10 ; /* 0x0000000a0b007388 */
/* 0x004fe80000004800 */
/*01b0*/ STS [R11.X4+0x400], R12 ; /* 0x0004000c0b007388 */
/* 0x008fe80000004800 */
/*01c0*/ STS [R11.X4+0x800], R14 ; /* 0x0008000e0b007388 */
/* 0x020fe80000004800 */
/*01d0*/ STS [R11.X4+0xc00], R16 ; /* 0x000c00100b007388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ LDS R15, [R11.X4] ; /* 0x000000000b0f7984 */
/* 0x000e280000004800 */
/*0200*/ LDS R17, [R11.X4+0x400] ; /* 0x000400000b117984 */
/* 0x000e680000004800 */
/*0210*/ LDS R19, [R11.X4+0x800] ; /* 0x000800000b137984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R21, [R11.X4+0xc00] ; /* 0x000c00000b157984 */
/* 0x000ee80000004800 */
/*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x001fe8000c101904 */
/*0240*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x002fe8000c101904 */
/*0250*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x004fe8000c101904 */
/*0260*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x008fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} | .file "tmpxft_0003a2b6_00000000-6_copySharedMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.type _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, @function
_Z36__device_stub__Z13copySharedMemPfPKfPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13copySharedMemPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, .-_Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.globl _Z13copySharedMemPfPKf
.type _Z13copySharedMemPfPKf, @function
_Z13copySharedMemPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13copySharedMemPfPKf, .-_Z13copySharedMemPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13copySharedMemPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13copySharedMemPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13copySharedMemPfPKf
.globl _Z13copySharedMemPfPKf
.p2align 8
.type _Z13copySharedMemPfPKf,@function
_Z13copySharedMemPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_mov_b32 s7, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 5, v2
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v5, v2, 7, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, s4, v1
s_lshl_b32 s6, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v4
v_add3_u32 v0, v3, v1, s5
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s7, s7, 8
s_cmp_gt_u32 s7, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
v_add_nc_u32_e32 v5, 0x400, v5
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 5, v4
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, v3, v0, s5
v_lshl_add_u32 v2, v2, 7, v1
s_barrier
buffer_gl0_inv
.LBB0_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 0x400, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB0_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copySharedMemPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13copySharedMemPfPKf, .Lfunc_end0-_Z13copySharedMemPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copySharedMemPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copySharedMemPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copySharedMem(float *odata, const float *idata)
{
__shared__ float tile[TILE_DIM * TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x] = idata[(y+j)*width + x];
__syncthreads();
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
odata[(y+j)*width + x] = tile[(threadIdx.y+j)*TILE_DIM + threadIdx.x];
} | .text
.file "copySharedMem.hip"
.globl _Z28__device_stub__copySharedMemPfPKf # -- Begin function _Z28__device_stub__copySharedMemPfPKf
.p2align 4, 0x90
.type _Z28__device_stub__copySharedMemPfPKf,@function
_Z28__device_stub__copySharedMemPfPKf: # @_Z28__device_stub__copySharedMemPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13copySharedMemPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__copySharedMemPfPKf, .Lfunc_end0-_Z28__device_stub__copySharedMemPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13copySharedMemPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13copySharedMemPfPKf,@object # @_Z13copySharedMemPfPKf
.section .rodata,"a",@progbits
.globl _Z13copySharedMemPfPKf
.p2align 3, 0x0
_Z13copySharedMemPfPKf:
.quad _Z28__device_stub__copySharedMemPfPKf
.size _Z13copySharedMemPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13copySharedMemPfPKf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__copySharedMemPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13copySharedMemPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13copySharedMemPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0xc] ; /* 0x00000300000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R2, R13.reuse, 0x5, RZ ; /* 0x000000050d027819 */
/* 0x040fe400000006ff */
/*0070*/ SHF.L.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7819 */
/* 0x000fe200000006ff */
/*0080*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0090*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000e620000002200 */
/*00a0*/ LEA R0, R0, R11, 0x5 ; /* 0x0000000b00007211 */
/* 0x001fc400078e28ff */
/*00b0*/ LEA R3, R3, R18, 0x5 ; /* 0x0000001203037211 */
/* 0x002fca00078e28ff */
/*00c0*/ IMAD R0, R3, R2, R0 ; /* 0x0000000203007224 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R23, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0217 */
/*00e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x0002e2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000962000c1e1900 */
/*0130*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fca00078e0206 */
/*0140*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000962000c1e1900 */
/*0150*/ LEA R11, R18, R11, 0x5 ; /* 0x0000000b120b7211 */
/* 0x000fe200078e28ff */
/*0160*/ IMAD.WIDE R2, R0, R23, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0217 */
/*0170*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x002fcc00078e0202 */
/*0180*/ IMAD.WIDE R6, R13, 0x4, R4 ; /* 0x000000040d067825 */
/* 0x010fcc00078e0204 */
/*0190*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fe200078e0206 */
/*01a0*/ STS [R11.X4], R10 ; /* 0x0000000a0b007388 */
/* 0x004fe80000004800 */
/*01b0*/ STS [R11.X4+0x400], R12 ; /* 0x0004000c0b007388 */
/* 0x008fe80000004800 */
/*01c0*/ STS [R11.X4+0x800], R14 ; /* 0x0008000e0b007388 */
/* 0x020fe80000004800 */
/*01d0*/ STS [R11.X4+0xc00], R16 ; /* 0x000c00100b007388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ LDS R15, [R11.X4] ; /* 0x000000000b0f7984 */
/* 0x000e280000004800 */
/*0200*/ LDS R17, [R11.X4+0x400] ; /* 0x000400000b117984 */
/* 0x000e680000004800 */
/*0210*/ LDS R19, [R11.X4+0x800] ; /* 0x000800000b137984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R21, [R11.X4+0xc00] ; /* 0x000c00000b157984 */
/* 0x000ee80000004800 */
/*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x001fe8000c101904 */
/*0240*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x002fe8000c101904 */
/*0250*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x004fe8000c101904 */
/*0260*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x008fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13copySharedMemPfPKf
.globl _Z13copySharedMemPfPKf
.p2align 8
.type _Z13copySharedMemPfPKf,@function
_Z13copySharedMemPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_mov_b32 s7, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 5, v2
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v5, v2, 7, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, s4, v1
s_lshl_b32 s6, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v4
v_add3_u32 v0, v3, v1, s5
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s7, s7, 8
s_cmp_gt_u32 s7, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
v_add_nc_u32_e32 v5, 0x400, v5
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 5, v4
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, v3, v0, s5
v_lshl_add_u32 v2, v2, 7, v1
s_barrier
buffer_gl0_inv
.LBB0_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 0x400, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB0_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13copySharedMemPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13copySharedMemPfPKf, .Lfunc_end0-_Z13copySharedMemPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13copySharedMemPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13copySharedMemPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003a2b6_00000000-6_copySharedMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.type _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, @function
_Z36__device_stub__Z13copySharedMemPfPKfPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13copySharedMemPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13copySharedMemPfPKfPfPKf, .-_Z36__device_stub__Z13copySharedMemPfPKfPfPKf
.globl _Z13copySharedMemPfPKf
.type _Z13copySharedMemPfPKf, @function
_Z13copySharedMemPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13copySharedMemPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13copySharedMemPfPKf, .-_Z13copySharedMemPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13copySharedMemPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13copySharedMemPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copySharedMem.hip"
.globl _Z28__device_stub__copySharedMemPfPKf # -- Begin function _Z28__device_stub__copySharedMemPfPKf
.p2align 4, 0x90
.type _Z28__device_stub__copySharedMemPfPKf,@function
_Z28__device_stub__copySharedMemPfPKf: # @_Z28__device_stub__copySharedMemPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13copySharedMemPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__copySharedMemPfPKf, .Lfunc_end0-_Z28__device_stub__copySharedMemPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13copySharedMemPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13copySharedMemPfPKf,@object # @_Z13copySharedMemPfPKf
.section .rodata,"a",@progbits
.globl _Z13copySharedMemPfPKf
.p2align 3, 0x0
_Z13copySharedMemPfPKf:
.quad _Z28__device_stub__copySharedMemPfPKf
.size _Z13copySharedMemPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13copySharedMemPfPKf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__copySharedMemPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13copySharedMemPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
typedef signed char schar;
typedef unsigned char uchar;
typedef short shrt;
typedef unsigned short ushrt;
typedef unsigned uint;
typedef unsigned long ulong;
typedef long long llong;
typedef unsigned long long ullong;
typedef float flt;
typedef double dbl;
typedef long double ldbl;
class Compare
{
public:
__host__ __device__ bool operator()(const dbl a, const dbl b) const
{
return fabs(a) < fabs(b);
}
};
__global__ static void row_switching(dbl * __restrict__, uint,
uint, uint);
__global__ static void column_to_null_down(dbl * __restrict__, uint,
uint);
__global__ static void column_to_null_up(dbl * __restrict__, uint,
uint);
__global__ static void solve(dbl * __restrict__, uint);
__host__ static uint matrix_in(dbl ** __restrict__);
__host__ static void matrix_out(dbl * __restrict__, uint);
__host__ static void gauss_jordan_elimination(dbl * __restrict__, uint) noexcept;
int main()
{
dbl *matrix;
const uint n = matrix_in(&matrix);
gauss_jordan_elimination(matrix, n);
matrix_out(matrix, n);
return 0;
}
__host__ static void gauss_jordan_elimination(
dbl * __restrict__ const host_matrix, const uint n) noexcept
{
const Compare compare;
const dim3 block = dim3(32U, 16U), thread = dim3(32U, 16U);
dbl *device_matrix;
cudaMalloc(&device_matrix, sizeof(dbl) * n * (n + 1));
cudaMemcpy(device_matrix, host_matrix, sizeof(dbl) * n * (n + 1),
cudaMemcpyHostToDevice);
const thrust::device_ptr<dbl> ptr = thrust::device_pointer_cast(device_matrix);
for (uint i = 0; i < n - 1; ++i)
{
const uint max_idx = thrust::max_element(
ptr + i * n + i,
ptr + (i + 1) * n, compare) - ptr - i * n;
if (max_idx != i)
{
row_switching<<<512U, 512U>>>(device_matrix, n, i, max_idx);
}
column_to_null_down<<<block, thread>>>(device_matrix, n, i);
}
for (uint i = n - 1; i > 0; --i)
{
column_to_null_up<<<512U, 512U>>>(device_matrix, n, i);
}
solve<<<512U, 512U>>>(device_matrix, n);
cudaMemcpy(host_matrix + n * n, device_matrix + n * n, sizeof(dbl) * n,
cudaMemcpyDeviceToHost);
cudaFree(device_matrix);
}
__global__ static void row_switching(dbl * __restrict__ const m,
const uint n, const uint i, const uint j)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
for (uint k = i + idx; k <= n; k += offset)
{
const dbl temp = m[k * n + i];
m[k * n + i] = m[k * n + j];
m[k * n + j] = temp;
}
}
__global__ static void column_to_null_down(dbl * __restrict__ const m,
const uint n, const uint k)
{
const uint
idxX = threadIdx.x + blockDim.x * blockIdx.x,
idxY = threadIdx.y + blockDim.y * blockIdx.y,
offsetX = blockDim.x * gridDim.x,
offsetY = blockDim.y * gridDim.y;
const dbl m_k_k = m[k * n + k];
for (uint j = k + 1 + idxY; j <= n; j += offsetY)
{
for (uint i = k + 1 + idxX; i < n; i += offsetX)
{
m[j * n + i] = fma(-m[k * n + i] / m_k_k,
m[j * n + k], m[j * n + i]);
}
}
}
__global__ static void column_to_null_up(dbl * __restrict__ const m,
const uint n, const uint k)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
const dbl m_k_k = m[k * n + k], m_k_n = m[n * n + k];
for (uint i = idx; i < k; i += offset)
{
m[n * n + i] = fma(-m[k * n + i] / m_k_k, m_k_n, m[n * n + i]);
}
}
__global__ static void solve(dbl * __restrict__ const m,
const uint n)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
for (uint k = idx; k < n; k += offset)
{
m[n * n + k] /= m[k * n + k];
}
}
__host__ static uint matrix_in(dbl ** const __restrict__ matrix_ptr)
{
uint n;
scanf("%u", &n);
dbl * const matrix = (dbl *) malloc(sizeof(dbl) * n * (n + 1));
for (uint i = 0; i < n; ++i)
{
for (uint j = 0; j < n; ++j)
{
scanf("%lf", matrix + j * n + i);
}
}
for (uint i = 0; i < n; ++i)
{
scanf("%lf", matrix + n * n + i);
}
*matrix_ptr = matrix;
return n;
}
__host__ static void matrix_out(dbl * __restrict__ const matrix, const uint n)
{
for (uint i = 0; i < n; ++i)
{
printf("%.10le ", matrix[n * n + i]);
}
putchar('\n');
free(matrix);
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
typedef signed char schar;
typedef unsigned char uchar;
typedef short shrt;
typedef unsigned short ushrt;
typedef unsigned uint;
typedef unsigned long ulong;
typedef long long llong;
typedef unsigned long long ullong;
typedef float flt;
typedef double dbl;
typedef long double ldbl;
class Compare
{
public:
__host__ __device__ bool operator()(const dbl a, const dbl b) const
{
return fabs(a) < fabs(b);
}
};
__global__ static void row_switching(dbl * __restrict__, uint,
uint, uint);
__global__ static void column_to_null_down(dbl * __restrict__, uint,
uint);
__global__ static void column_to_null_up(dbl * __restrict__, uint,
uint);
__global__ static void solve(dbl * __restrict__, uint);
__host__ static uint matrix_in(dbl ** __restrict__);
__host__ static void matrix_out(dbl * __restrict__, uint);
__host__ static void gauss_jordan_elimination(dbl * __restrict__, uint) noexcept;
int main()
{
dbl *matrix;
const uint n = matrix_in(&matrix);
gauss_jordan_elimination(matrix, n);
matrix_out(matrix, n);
return 0;
}
__host__ static void gauss_jordan_elimination(
dbl * __restrict__ const host_matrix, const uint n) noexcept
{
const Compare compare;
const dim3 block = dim3(32U, 16U), thread = dim3(32U, 16U);
dbl *device_matrix;
hipMalloc(&device_matrix, sizeof(dbl) * n * (n + 1));
hipMemcpy(device_matrix, host_matrix, sizeof(dbl) * n * (n + 1),
hipMemcpyHostToDevice);
const thrust::device_ptr<dbl> ptr = thrust::device_pointer_cast(device_matrix);
for (uint i = 0; i < n - 1; ++i)
{
const uint max_idx = thrust::max_element(
ptr + i * n + i,
ptr + (i + 1) * n, compare) - ptr - i * n;
if (max_idx != i)
{
row_switching<<<512U, 512U>>>(device_matrix, n, i, max_idx);
}
column_to_null_down<<<block, thread>>>(device_matrix, n, i);
}
for (uint i = n - 1; i > 0; --i)
{
column_to_null_up<<<512U, 512U>>>(device_matrix, n, i);
}
solve<<<512U, 512U>>>(device_matrix, n);
hipMemcpy(host_matrix + n * n, device_matrix + n * n, sizeof(dbl) * n,
hipMemcpyDeviceToHost);
hipFree(device_matrix);
}
__global__ static void row_switching(dbl * __restrict__ const m,
const uint n, const uint i, const uint j)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
for (uint k = i + idx; k <= n; k += offset)
{
const dbl temp = m[k * n + i];
m[k * n + i] = m[k * n + j];
m[k * n + j] = temp;
}
}
__global__ static void column_to_null_down(dbl * __restrict__ const m,
const uint n, const uint k)
{
const uint
idxX = threadIdx.x + blockDim.x * blockIdx.x,
idxY = threadIdx.y + blockDim.y * blockIdx.y,
offsetX = blockDim.x * gridDim.x,
offsetY = blockDim.y * gridDim.y;
const dbl m_k_k = m[k * n + k];
for (uint j = k + 1 + idxY; j <= n; j += offsetY)
{
for (uint i = k + 1 + idxX; i < n; i += offsetX)
{
m[j * n + i] = fma(-m[k * n + i] / m_k_k,
m[j * n + k], m[j * n + i]);
}
}
}
__global__ static void column_to_null_up(dbl * __restrict__ const m,
const uint n, const uint k)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
const dbl m_k_k = m[k * n + k], m_k_n = m[n * n + k];
for (uint i = idx; i < k; i += offset)
{
m[n * n + i] = fma(-m[k * n + i] / m_k_k, m_k_n, m[n * n + i]);
}
}
__global__ static void solve(dbl * __restrict__ const m,
const uint n)
{
const uint idx = threadIdx.x + blockDim.x * blockIdx.x,
offset = blockDim.x * gridDim.x;
for (uint k = idx; k < n; k += offset)
{
m[n * n + k] /= m[k * n + k];
}
}
__host__ static uint matrix_in(dbl ** const __restrict__ matrix_ptr)
{
uint n;
scanf("%u", &n);
dbl * const matrix = (dbl *) malloc(sizeof(dbl) * n * (n + 1));
for (uint i = 0; i < n; ++i)
{
for (uint j = 0; j < n; ++j)
{
scanf("%lf", matrix + j * n + i);
}
}
for (uint i = 0; i < n; ++i)
{
scanf("%lf", matrix + n * n + i);
}
*matrix_ptr = matrix;
return n;
}
__host__ static void matrix_out(dbl * __restrict__ const matrix, const uint n)
{
for (uint i = 0; i < n; ++i)
{
printf("%.10le ", matrix[n * n + i]);
}
putchar('\n');
free(matrix);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#define CHECK(res) if(res!=cudaSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
cudaError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = cudaMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = cudaMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = cudaMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), cudaMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = cudaMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), cudaMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
cudaFree((void*)da);
cudaFree((void*)dr);
free(ha);
free(hr);
return 0;
} | code for sm_80
Function : _Z10KerneltestPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.U32.AND P0, PT, R4, 0x9, PT ; /* 0x000000090400780c */
/* 0x001fda0003f04070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0080*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007f1e0ff */
/*0090*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff057624 */
/* 0x000fe200000e06ff */
/*00a0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#define CHECK(res) if(res!=cudaSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
cudaError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = cudaMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = cudaMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = cudaMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), cudaMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = cudaMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), cudaMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
cudaFree((void*)da);
cudaFree((void*)dr);
free(ha);
free(hr);
return 0;
} | .file "tmpxft_0001a31d_00000000-6_addfunc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10KerneltestPcS_PcS_
.type _Z32__device_stub__Z10KerneltestPcS_PcS_, @function
_Z32__device_stub__Z10KerneltestPcS_PcS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10KerneltestPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10KerneltestPcS_PcS_, .-_Z32__device_stub__Z10KerneltestPcS_PcS_
.globl _Z10KerneltestPcS_
.type _Z10KerneltestPcS_, @function
_Z10KerneltestPcS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10KerneltestPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10KerneltestPcS_, .-_Z10KerneltestPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2.GPU recieve :\n %s\n"
.LC1:
.string "3.GPU func result:\n %s\n"
.text
.globl func
.type func, @function
func:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L21
leaq 8(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L22
movl $10, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L14:
movzbl 0(%rbp,%rax), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq $10, %rax
jne .L14
movl $1, %ecx
movl $10, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L23
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl $2, %ecx
movl $10, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L25
movq (%r12), %rax
movq %rax, 0(%r13)
movzwl 8(%r12), %eax
movw %ax, 8(%r13)
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $-1, %edi
call exit@PLT
.L22:
movl $-1, %edi
call exit@PLT
.L23:
movl $-1, %edi
call exit@PLT
.L24:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z10KerneltestPcS_PcS_
jmp .L16
.L25:
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size func, .-func
.section .rodata.str1.1
.LC2:
.string "_Z10KerneltestPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10KerneltestPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda_runtime.h>
#define CHECK(res) if(res!=cudaSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
cudaError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = cudaMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = cudaMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = cudaMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), cudaMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = cudaMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), cudaMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
cudaFree((void*)da);
cudaFree((void*)dr);
free(ha);
free(hr);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(res) if(res!=hipSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
hipError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = hipMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = hipMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = hipMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), hipMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = hipMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), hipMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
hipFree((void*)da);
hipFree((void*)dr);
free(ha);
free(hr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(res) if(res!=hipSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
hipError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = hipMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = hipMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = hipMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), hipMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = hipMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), hipMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
hipFree((void*)da);
hipFree((void*)dr);
free(ha);
free(hr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10KerneltestPcS_
.globl _Z10KerneltestPcS_
.p2align 8
.type _Z10KerneltestPcS_,@function
_Z10KerneltestPcS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10KerneltestPcS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10KerneltestPcS_, .Lfunc_end0-_Z10KerneltestPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10KerneltestPcS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10KerneltestPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(res) if(res!=hipSuccess){exit(-1);}
__global__ void Kerneltest(char *da, char *dr)
{
unsigned int i= threadIdx.x;
if (i <10)
{
dr[i] = da[i]+1;
}
}
extern "C" int func(char *data, char *result)
{
char *da = NULL;
char *ha = NULL;
char *dr = NULL;
char *hr = NULL;
hipError_t res;
int r;
printf("2.GPU recieve :\n %s\n",data );
res = hipMalloc((void**)(&da), 10*sizeof(char));CHECK(res)
res = hipMalloc((void**)(&dr), 10*sizeof(char));CHECK(res)
ha = (char*)malloc(10*sizeof(char));
hr = (char*)malloc(10*sizeof(char));
for (r = 0; r < 10; r++)
{
ha[r] = data[r];
}
res = hipMemcpy((void*)(da), (void*)(ha), 10*sizeof(char), hipMemcpyHostToDevice);CHECK(res)
Kerneltest<<<1, 10>>>(da, dr);
res = hipMemcpy((void*)(hr), (void*)(dr), 10*sizeof(char), hipMemcpyDeviceToHost);CHECK(res)
memcpy(result,hr,10);
printf("3.GPU func result:\n %s\n", result );
hipFree((void*)da);
hipFree((void*)dr);
free(ha);
free(hr);
return 0;
} | .text
.file "addfunc.hip"
.globl _Z25__device_stub__KerneltestPcS_ # -- Begin function _Z25__device_stub__KerneltestPcS_
.p2align 4, 0x90
.type _Z25__device_stub__KerneltestPcS_,@function
_Z25__device_stub__KerneltestPcS_: # @_Z25__device_stub__KerneltestPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10KerneltestPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__KerneltestPcS_, .Lfunc_end0-_Z25__device_stub__KerneltestPcS_
.cfi_endproc
# -- End function
.globl func # -- Begin function func
.p2align 4, 0x90
.type func,@function
func: # @func
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r12
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $.L.str, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.1:
movq %rsp, %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.2:
movl $10, %edi
callq malloc
movq %rax, %r14
movl $10, %edi
callq malloc
movq %rax, %r15
movq (%r12), %rax
movq %rax, (%r14)
movzwl 8(%r12), %eax
movw %ax, 8(%r14)
movq 8(%rsp), %rdi
movl $10, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.3:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10KerneltestPcS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
movl $10, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movzwl 8(%r15), %eax
movw %ax, 8(%rbx)
movq (%r15), %rax
movq %rax, (%rbx)
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
movl $-1, %edi
callq exit
.Lfunc_end1:
.size func, .Lfunc_end1-func
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10KerneltestPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10KerneltestPcS_,@object # @_Z10KerneltestPcS_
.section .rodata,"a",@progbits
.globl _Z10KerneltestPcS_
.p2align 3, 0x0
_Z10KerneltestPcS_:
.quad _Z25__device_stub__KerneltestPcS_
.size _Z10KerneltestPcS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2.GPU recieve :\n %s\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "3.GPU func result:\n %s\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10KerneltestPcS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__KerneltestPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10KerneltestPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10KerneltestPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.U32.AND P0, PT, R4, 0x9, PT ; /* 0x000000090400780c */
/* 0x001fda0003f04070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0080*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007f1e0ff */
/*0090*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff057624 */
/* 0x000fe200000e06ff */
/*00a0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10KerneltestPcS_
.globl _Z10KerneltestPcS_
.p2align 8
.type _Z10KerneltestPcS_,@function
_Z10KerneltestPcS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 10, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10KerneltestPcS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10KerneltestPcS_, .Lfunc_end0-_Z10KerneltestPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10KerneltestPcS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10KerneltestPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001a31d_00000000-6_addfunc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10KerneltestPcS_PcS_
.type _Z32__device_stub__Z10KerneltestPcS_PcS_, @function
_Z32__device_stub__Z10KerneltestPcS_PcS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10KerneltestPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z10KerneltestPcS_PcS_, .-_Z32__device_stub__Z10KerneltestPcS_PcS_
.globl _Z10KerneltestPcS_
.type _Z10KerneltestPcS_, @function
_Z10KerneltestPcS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10KerneltestPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10KerneltestPcS_, .-_Z10KerneltestPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2.GPU recieve :\n %s\n"
.LC1:
.string "3.GPU func result:\n %s\n"
.text
.globl func
.type func, @function
func:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L21
leaq 8(%rsp), %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L22
movl $10, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L14:
movzbl 0(%rbp,%rax), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq $10, %rax
jne .L14
movl $1, %ecx
movl $10, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L23
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl $2, %ecx
movl $10, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L25
movq (%r12), %rax
movq %rax, 0(%r13)
movzwl 8(%r12), %eax
movw %ax, 8(%r13)
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $-1, %edi
call exit@PLT
.L22:
movl $-1, %edi
call exit@PLT
.L23:
movl $-1, %edi
call exit@PLT
.L24:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z10KerneltestPcS_PcS_
jmp .L16
.L25:
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size func, .-func
.section .rodata.str1.1
.LC2:
.string "_Z10KerneltestPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10KerneltestPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addfunc.hip"
.globl _Z25__device_stub__KerneltestPcS_ # -- Begin function _Z25__device_stub__KerneltestPcS_
.p2align 4, 0x90
.type _Z25__device_stub__KerneltestPcS_,@function
_Z25__device_stub__KerneltestPcS_: # @_Z25__device_stub__KerneltestPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10KerneltestPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__KerneltestPcS_, .Lfunc_end0-_Z25__device_stub__KerneltestPcS_
.cfi_endproc
# -- End function
.globl func # -- Begin function func
.p2align 4, 0x90
.type func,@function
func: # @func
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r12
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $.L.str, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.1:
movq %rsp, %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.2:
movl $10, %edi
callq malloc
movq %rax, %r14
movl $10, %edi
callq malloc
movq %rax, %r15
movq (%r12), %rax
movq %rax, (%r14)
movzwl 8(%r12), %eax
movw %ax, 8(%r14)
movq 8(%rsp), %rdi
movl $10, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.3:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10KerneltestPcS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
movl $10, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movzwl 8(%r15), %eax
movw %ax, 8(%rbx)
movq (%r15), %rax
movq %rax, (%rbx)
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
movl $-1, %edi
callq exit
.Lfunc_end1:
.size func, .Lfunc_end1-func
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10KerneltestPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10KerneltestPcS_,@object # @_Z10KerneltestPcS_
.section .rodata,"a",@progbits
.globl _Z10KerneltestPcS_
.p2align 3, 0x0
_Z10KerneltestPcS_:
.quad _Z25__device_stub__KerneltestPcS_
.size _Z10KerneltestPcS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2.GPU recieve :\n %s\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "3.GPU func result:\n %s\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10KerneltestPcS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__KerneltestPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10KerneltestPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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